3 files changed, 6 insertions, 52 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
index 7d30c0dcf6..2d79075f50 100644
--- a/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
+++ b/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
@@ -282,7 +282,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	print_debug("after enable_fid_change\r\n");
 
 	/* FIXME does not work yet */
-//	init_fidvid_bsp(bsp_apicid);
+	init_fidvid_bsp(bsp_apicid);
 
 	/* Stop the APs so we can start them later in init. */
 	allow_all_aps_stop(bsp_apicid);
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index 7b85a1979a..49f3d90020 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -236,20 +236,10 @@ void vt8237_sb_enable_fid_vid(void)
 
 		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 					   PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
+
 		if (devctl == PCI_DEV_INVALID)
 			return;
 
-		/* TODO: Why is this an extra block? */
-		{
-			u8 tmp;
-			tmp = pci_read_config8(devctl, 0xec);
-			print_debug("EC is ");
-			print_debug_hex8(tmp);
-			print_debug(" E5 is ");
-			tmp = pci_read_config8(dev, 0xe5);
-			print_debug_hex8(tmp);
-		}
-
 		/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
 		pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
 
@@ -261,47 +251,15 @@ void vt8237_sb_enable_fid_vid(void)
 		 * Will work for C3 and for FID/VID change.
 		 */
 
-		/* FIXME */
-		outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
-//              outb(0x4, VT8237R_ACPI_IO_BASE + 0x50);  /* Maybe unneeded? */
-
-		/* It seems for AMD LDTSTP is connected not to SLP anymore. */
-		/* Enable 0: DPSLP# / DPRSTP# / VRDSLP */
-
-		/*
-		 * Enable SATA LED, VR timer = 100us.
-		 * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs
-		 * to some of those pins! (and not to SLP as on R ver).
-		 */
-		pci_write_config8(dev, 0xe5, 0x69);	/* FIXME */
-
-		/*
-		 * REQ5 as PCI request input - should be together with
-		 * INTE-INTH. Fast VR timer disable - need for LDTSTP signal.
-		 */
-		pci_write_config8(dev, 0xe4, 0xa5);
+		outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
 
 		/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 		pci_write_config8(dev, 0xec, 0x4);
 
-		/* Host Bus Power Management Control, maybe not needed. */
-		pci_write_config8(dev, 0x8c, 0x5);
-
 		/* So the chip knows we are on AMD. */
-		pci_write_config8(devctl, 0x7c, 0x77);
-
-		devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-						  0x2336), 0);
-		if (devctl == PCI_DEV_INVALID)
-			return;
+		pci_write_config8(devctl, 0x7c, 0x7f);
 
-		/*
-		 * Enable C2NOW delay to PSTATECTL VID / FID Change Delay
-		 * to P-State Control.
-		 */
-		pci_write_config8(devctl, 0xa6, 0x83);
-
-		// return; // FIXME: Fall through some revs have it old way.
+		return;
 	}
 
 	/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 10d8c35c19..78c973fba0 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -264,14 +264,10 @@ static void vt8237s_init(struct device *dev)
 	pci_write_config32(dev, 0xbc,
 			   (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
 
-	/* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */
-	pci_write_config8(dev, 0xe5, 0x69);
-
 	/*
 	 * REQ5 as PCI request input - should be together with INTE-INTH. 
-	 * Fast VR timer disable - need for LDTSTOP_L signal.
 	 */
-	pci_write_config8(dev, 0xe4, 0xa5);
+	pci_write_config8(dev, 0xe4, 0x04);
 
 	/* Reduce further the STPCLK/LDTSTP signal to 5us. */
 	pci_write_config8(dev, 0xec, 0x4);