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-rw-r--r--src/soc/intel/fsp_baytrail/baytrail/gpio.h8
-rw-r--r--src/soc/intel/fsp_baytrail/bootblock/bootblock.c15
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index 600f4e97f4..e13b663273 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -286,6 +286,8 @@
#define GPSSUS_GPIO_F1_RANGE_START 11
#define GPSSUS_GPIO_F1_RANGE_END 21
+#ifndef __BOOT_BLOCK__
+
struct soc_gpio_map {
u32 pad_conf0;
u32 pad_conf1;
@@ -328,6 +330,8 @@ uint8_t read_ssus_gpio(uint8_t gpio_num);
void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
+#endif /* #ifndef __BOOT_BLOCK__ */
+
/* Functions / defines for changing GPIOs in romstage */
/* SCORE Pad definitions. */
#define UART_RXD_PAD 82
@@ -367,6 +371,8 @@ static inline void ssus_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
+#ifndef __BOOT_BLOCK__
+
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
@@ -388,4 +394,6 @@ static inline void ssus_disable_internal_pull(int pad)
write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
}
+#endif /* #ifndef __BOOT_BLOCK__ */
+
#endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 1623f04da1..e8f5572ef7 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -27,6 +27,7 @@
#include <baytrail/spi.h>
#include <baytrail/iomap.h>
#include <baytrail/lpc.h>
+#include <baytrail/gpio.h>
#include <reset.h>
/*
@@ -100,6 +101,19 @@ static void setup_mmconfig(void)
pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
}
+static const uint8_t lpc_pads[12] = {
+ 70, 68, 67, 66, 69, 71, 65, 72, 86, 90, 88, 92,
+};
+
+static void set_up_lpc_pads(void)
+{
+ uint32_t reg = IO_BASE_ADDRESS | SET_BAR_ENABLE;
+ pci_write_config32(LPC_BDF, IOBASE, reg);
+
+ for (reg = 0; reg < 12; reg++)
+ score_select_func(lpc_pads[reg], 1);
+}
+
static void bootblock_cpu_init(void)
{
@@ -109,4 +123,5 @@ static void bootblock_cpu_init(void)
setup_mmconfig();
enable_rom_caching();
enable_spi_prefetch();
+ set_up_lpc_pads();
}