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-rw-r--r--src/soc/nvidia/tegra210/i2c6.c3
-rw-r--r--src/soc/nvidia/tegra210/include/soc/clock.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c
index 915a5386e9..92130577c3 100644
--- a/src/soc/nvidia/tegra210/i2c6.c
+++ b/src/soc/nvidia/tegra210/i2c6.c
@@ -65,6 +65,9 @@ void soc_configure_i2c6pad(void)
*/
soc_configure_host1x();
+ /* enable SOR_SAFE and DPAUX_1 clocks */
+ clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE);
+
/* Now we can write the I2C6 mux in DPAUX */
write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL);
/* Finally, power up the pads */
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index ff9b282eaa..8564c83df3 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -158,7 +158,9 @@ enum {
CLK_X_SPARE = 0x1 << 0,
CLK_Y_APE = 0x1 << 6,
+ CLK_Y_DPAUX1 = 0x1 << 15,
CLK_Y_QSPI = 0x1 << 19,
+ CLK_Y_SOR_SAFE = 0x1 << 30,
};
enum {