diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_dmi.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 35 |
3 files changed, 26 insertions, 25 deletions
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 287c4414d2..d4cbec8aa7 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -157,8 +157,8 @@ void early_init_dmi(void) DMIBAR32(0x0914 + (i << 5)) = 0x98200280; } - DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; + DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 + DMIBAR32(DMIL0SLAT) = 0x00c2403c; early_pch_init_native_dmi_pre(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e670c09cf0..541bf73bee 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -262,8 +262,8 @@ static void northbridge_dmi_init(struct device *dev) u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -273,9 +273,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x250) = reg32; } - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; if (bridge_silicon_revision() >= SNB_STEP_D0) { reg32 = DMIBAR32(0x1f8); @@ -300,9 +300,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0xd04) = reg32; } - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9db5ae3978..5318d0b245 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -87,9 +87,6 @@ enum platform_type { #define EPVC1RCTL 0x020 /* 32bit */ #define EPVC1RSTS 0x026 /* 16bit */ -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1IST 0x038 /* 64bit */ - #define EPESD 0x044 /* 32bit */ #define EPLE1D 0x050 /* 32bit */ @@ -97,8 +94,6 @@ enum platform_type { #define EPLE2D 0x060 /* 32bit */ #define EPLE2A 0x068 /* 64bit */ -#define PORTARB 0x100 /* 256bit */ - /* * DMIBAR */ @@ -110,27 +105,30 @@ enum platform_type { #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP2 0x008 /* 32bit */ - #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ #define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP 0x2 +#define VC0NP (1 << 1) #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP 0x2 +#define VC1NP (1 << 1) +#define DMIVCPRCAP 0x028 /* 32bit */ #define DMIVCPRCTL 0x02c /* 32bit */ - #define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP 0x2 +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) -#define DMIVCMRCTL 0x0038 /* 32 bit */ -#define DMIVCMRSTS 0x003e /* 16 bit */ -#define VCMNP 0x2 +#define DMIRCLDECH 0x040 /* 32bit */ +#define DMIESD 0x044 /* 32bit */ #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -141,12 +139,15 @@ enum platform_type { #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ #define TXTRN (1 << 11) -#define DMICTL1 0x0f0 /* 32bit */ -#define DMICTL2 0x0fc /* 32bit */ -#define DMICC 0x208 /* 32bit */ +#define DMILCTL2 0x098 /* 16bit */ +#define DMILSTS2 0x09a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ -#define DMIDRCCFG 0xeb4 /* 32bit */ +#define DMIL0SLAT 0x22c /* 32bit */ +#define DMILLTC 0x238 /* 32bit */ #ifndef __ASSEMBLER__ |