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-rw-r--r--src/southbridge/intel/i82801gx/lpc.c42
1 files changed, 14 insertions, 28 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 777a6d772f..9285080f19 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -39,37 +39,23 @@
typedef struct southbridge_intel_i82801gx_config config_t;
-static void i82801gx_enable_apic(struct device *dev)
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801gx_enable_ioapic(struct device *dev)
{
- int i;
- u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
- /* Enable ACPI I/O and power management.
- * Set SCI IRQ to IRQ9
- */
+ /* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- *ioapic_index = 0;
- *ioapic_data = (2 << 24);
-
- *ioapic_index = 0;
- reg32 = *ioapic_data;
- printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
- if (reg32 != (2 << 24))
- die("APIC Error\n");
-
- printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
- for (i=0; i<3; i++) {
- *ioapic_index = i;
- printk(BIOS_SPEW, " reg 0x%04x:", i);
- reg32 = *ioapic_data;
- printk(BIOS_SPEW, " 0x%08x\n", reg32);
- }
+ set_ioapic_id(IO_APIC_ADDR, 0x02);
- *ioapic_index = 3; /* Select Boot Configuration register. */
- *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+ /*
+ * Select Boot Configuration register (0x03) and
+ * use Processor System Bus (0x01) to deliver interrupts.
+ */
+ io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
}
static void i82801gx_enable_serial_irqs(struct device *dev)
@@ -422,7 +408,7 @@ static void lpc_init(struct device *dev)
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
- i82801gx_enable_apic(dev);
+ i82801gx_enable_ioapic(dev);
i82801gx_enable_serial_irqs(dev);