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-rw-r--r--src/soc/amd/picasso/chip.h2
-rw-r--r--src/soc/amd/picasso/fch.c8
2 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index c0a64576de..66ac98ded0 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -219,6 +219,8 @@ struct soc_amd_picasso_config {
/* The array index is the general purpose PCIe clock output number. */
enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
+ /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
+ bool acp_i2s_use_external_48mhz_osc;
};
#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c
index cda509b0a5..0fe176b21a 100644
--- a/src/soc/amd/picasso/fch.c
+++ b/src/soc/amd/picasso/fch.c
@@ -89,9 +89,15 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
void sb_clk_output_48Mhz(void)
{
u32 ctrl;
+ const struct soc_amd_picasso_config *cfg;
+ cfg = config_of_soc();
ctrl = misc_read32(MISC_CLK_CNTL1);
- ctrl |= BP_X48M0_OUTPUT_EN;
+ /* If used external clock source for I2S, disable the internal clock output */
+ if (cfg->acp_i2s_use_external_48mhz_osc && cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
+ ctrl &= ~BP_X48M0_OUTPUT_EN;
+ else
+ ctrl |= BP_X48M0_OUTPUT_EN;
misc_write32(MISC_CLK_CNTL1, ctrl);
}