4 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index bb173c09d6..7c01a30604 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -19,6 +19,38 @@
 
 #include <soc/romstage.h>
 
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/nvidia/tegra132/gpio.h>
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static void configure_tpm_i2c_bus(void)
+{
+	clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
+
+	i2c_init(2);
+}
+
+void mainboard_init_tpm_i2c(void)
+{
+	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
+
+	gpio_output(GPIO(I5), 1);
+
+	// I2C3 (cam) clock.
+	pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
+			  PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+	// I2C3 (cam) data.
+	pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
+			  PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
+
+
+	configure_tpm_i2c_bus();
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index bb173c09d6..9a41247dd8 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -19,6 +19,10 @@
 
 #include <soc/romstage.h>
 
+void mainboard_init_tpm_i2c(void)
+{
+}
+
 void mainboard_configure_pmc(void)
 {
 }
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index f9eac26e0d..f66912151e 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -22,5 +22,6 @@
 
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
+void mainboard_init_tpm_i2c(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 812d14798c..69271f0088 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -30,6 +30,7 @@
 #include "ccplex.h"
 
 #include <soc/clock.h>
+#include <soc/romstage.h>
 
 void romstage(void);
 void romstage(void)
@@ -66,6 +67,8 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
+	mainboard_init_tpm_i2c();
+
 	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				CONFIG_CBFS_PREFIX "/ramstage");