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-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c38
-rw-r--r--src/include/cpu/amd/mtrr.h5
-rw-r--r--src/northbridge/amd/agesa/family10/northbridge.c1
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.c23
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c23
-rw-r--r--src/northbridge/amd/agesa/family15/northbridge.c22
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c23
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c22
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c21
9 files changed, 74 insertions, 104 deletions
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index f639d59bad..9349ad4a3b 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -116,6 +116,44 @@ static void uma_fb_resource(void *gp, struct device *dev, struct resource *res)
}
}
+/* These will likely move to some device node or cbmem. */
+static uint64_t amd_topmem = 0;
+static uint64_t amd_topmem2 = 0;
+
+uint64_t bsp_topmem(void)
+{
+ return amd_topmem;
+}
+
+uint64_t bsp_topmem2(void)
+{
+ return amd_topmem2;
+}
+
+/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers,
+ * so they can be distributed to AP CPUs. Not strictly MTRRs,
+ * but this is not that bad a place to have this code.
+ */
+void setup_bsp_ramtop(void)
+{
+ msr_t msr, msr2;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk(BIOS_INFO,
+ "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk(BIOS_INFO,
+ "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ amd_topmem = (uint64_t) msr.hi<<32 | msr.lo;
+ amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo;
+}
+
void amd_setup_mtrrs(void)
{
unsigned long address_bits;
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 3637dd937d..aa904e6a25 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -39,6 +39,11 @@
#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
void amd_setup_mtrrs(void);
+
+/* To distribute topmem MSRs to APs. */
+void setup_bsp_ramtop(void);
+uint64_t bsp_topmem(void);
+uint64_t bsp_topmem2(void);
#endif
#endif /* CPU_AMD_MTRR_H */
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 8cc9475c45..4b3859b20a 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -923,6 +923,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
#if CONFIG_GFXUMA
#error Northbridge does not set uma_memory_base or uma_memory_size.
#endif
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index af1d4f064c..6689e71f88 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -476,21 +476,9 @@ static void set_resources(device_t dev)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
+ uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk
- (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
/* refer to UMA Size Consideration in Family12h BKDG. */
/* Please reference MemNGetUmaSizeLN () */
/*
@@ -499,19 +487,17 @@ static void setup_uma_memory(void)
* >=1G 256M
* <1G 64M
*/
- sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size
- if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) {
+ sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size
+ if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) {
uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */
} else if (sys_mem >= 0x40000000) {
uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */
} else {
uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */
}
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -615,6 +601,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index a03939cde4..875dbbb744 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -524,24 +524,12 @@ static void domain_read_resources(device_t dev)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
+ uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk
- (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
/* refer to UMA Size Consideration in Family14h BKDG. */
- sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
- if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) {
+ sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
+ if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) {
uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */
}
else {
@@ -552,11 +540,9 @@ static void setup_uma_memory(void)
}
}
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -578,6 +564,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index d9a153b53b..96cfca2f8a 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -632,20 +632,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
+ uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
@@ -654,20 +643,18 @@ static void setup_uma_memory(void)
* >=1G 256M
* <1G 64M
*/
- sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
- if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
+ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
+ if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -686,6 +673,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index c63890df00..fb30277884 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -31,6 +31,7 @@
#include <cbmem.h>
#include <cpu/x86/lapic.h>
+#include <cpu/amd/mtrr.h>
#include <Porting.h>
#include <AGESA.h>
@@ -641,20 +642,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
+ uint32_t topmem = (uint32_t) bsp_topmem();
uint32_t sys_mem;
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk
- (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
/* refer to UMA Size Consideration in Family15h BKDG. */
/* Please reference MemNGetUmaSizeOR () */
/*
@@ -663,20 +653,18 @@ static void setup_uma_memory(void)
* >=1G 256M
* <1G 64M
*/
- sys_mem = msr.lo + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
- if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
+ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
+ if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
uma_memory_size = 512 << ONE_MB_SHIFT;
} else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
uma_memory_size = 256 << ONE_MB_SHIFT;
} else {
uma_memory_size = 64 << ONE_MB_SHIFT;
}
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -696,6 +684,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index aa15fdd6e5..865a3bc15f 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -851,22 +851,9 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
-
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk(BIOS_INFO,
- "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk(BIOS_INFO,
- "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
-
+ uint32_t topmem = (uint32_t) bsp_topmem();
/* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
+ switch (topmem) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x4000000; /* 64M recommended UMA */
break;
@@ -880,11 +867,9 @@ static void setup_uma_memory(void)
break;
}
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -903,6 +888,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if CONFIG_PCI_64BIT_PREF_MEM
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index b6e1a7d936..d94ee9abc9 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -826,21 +826,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
static void setup_uma_memory(void)
{
#if CONFIG_GFXUMA
- msr_t msr, msr2;
-
- /* TOP_MEM: the top of DRAM below 4G */
- msr = rdmsr(TOP_MEM);
- printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr.lo, msr.hi);
-
- /* TOP_MEM2: the top of DRAM above 4G */
- msr2 = rdmsr(TOP_MEM2);
- printk(BIOS_INFO, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
- __func__, msr2.lo, msr2.hi);
+ uint32_t topmem = (uint32_t) bsp_topmem();
#if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY
- switch (msr.lo) {
+ switch (topmem) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x2000000; /* 32M recommended UMA */
break;
@@ -859,7 +849,7 @@ static void setup_uma_memory(void)
}
#else
/* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
+ switch (topmem) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x4000000; /* 64M recommended UMA */
break;
@@ -874,11 +864,9 @@ static void setup_uma_memory(void)
}
#endif
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
-
- /* TODO: TOP_MEM2 */
#endif
}
@@ -896,6 +884,7 @@ static void amdk8_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
+ setup_bsp_ramtop();
setup_uma_memory();
#if 0
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 20:13:54 +0000