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-rw-r--r--src/cpu/amd/agesa/family12/fixme.c4
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c4
-rw-r--r--src/cpu/amd/agesa/family14/model_14_init.c8
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c4
-rw-r--r--src/cpu/amd/agesa/family15tn/model_15_init.c10
-rw-r--r--src/cpu/amd/agesa/family16kb/fixme.c4
-rw-r--r--src/cpu/amd/agesa/family16kb/model_16_init.c10
-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c4
-rw-r--r--src/cpu/amd/pi/00630F01/model_15_init.c8
-rw-r--r--src/cpu/amd/pi/00660F01/fixme.c4
-rw-r--r--src/cpu/amd/pi/00660F01/model_15_init.c8
-rw-r--r--src/cpu/amd/pi/00730F01/fixme.c4
-rw-r--r--src/cpu/amd/pi/00730F01/model_16_init.c8
-rw-r--r--src/drivers/amd/agesa/s3_mtrr.c20
14 files changed, 50 insertions, 50 deletions
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index 084cae8456..e97a819fda 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -98,7 +98,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 33e164354e..978c25ff6f 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -90,9 +90,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
MsrReg = 0;
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 3f0501e5cb..12f3ef1633 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -55,11 +55,11 @@ static void model_14_init(struct device *dev)
/* Set shadow WB, RdMEM, WrMEM */
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 847f75393f..7e493f9dda 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -76,7 +76,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index d188bcc84b..847eb6a52b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -54,12 +54,12 @@ static void model_15_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
- wrmsr (msrno, msr);
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
+ wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index 1f22307f1e..c761d6d22f 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -76,7 +76,7 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
}
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 286bcc377b..0c5e824587 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -52,12 +52,12 @@ static void model_16_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
msr.lo = msr.hi = 0;
- wrmsr (0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
- wrmsr (msrno, msr);
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
+ wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index 4feb1881cd..11cab62ba8 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -83,9 +83,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 503d5314ff..aa7afc2db8 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -54,11 +54,11 @@ static void model_15_init(struct device *dev)
* same as OntarioApMtrrSettingsList for APs
*/
msr.lo = msr.hi = 0;
- wrmsr(0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index 0bad4679ce..ee8728d34d 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -89,9 +89,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index 3f3a1fda44..a7822cfcfa 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -66,11 +66,11 @@ static void model_15_init(struct device *dev)
// BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0;
- wrmsr(0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 9f4c5289bb..4350572b9b 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -94,9 +94,9 @@ void amd_initmmio(void)
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
+ LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index f5121d1a4f..ecaa3ef274 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -51,11 +51,11 @@ static void model_16_init(struct device *dev)
* same as OntarioApMtrrSettingsList for APs
*/
msr.lo = msr.hi = 0;
- wrmsr(0x259, msr);
+ wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(0x250, msr);
- wrmsr(0x258, msr);
- for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr(MTRR_FIX_64K_00000, msr);
+ wrmsr(MTRR_FIX_16K_80000, msr);
+ for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index c039abefb6..531ad4565b 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -42,11 +42,11 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
wrmsr(SYSCFG_MSR, msr_data);
/* Fixed MTRRs */
- write_mtrr(&nvram_pos, 0x250);
- write_mtrr(&nvram_pos, 0x258);
- write_mtrr(&nvram_pos, 0x259);
+ write_mtrr(&nvram_pos, MTRR_FIX_64K_00000);
+ write_mtrr(&nvram_pos, MTRR_FIX_16K_80000);
+ write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000);
- for (i = 0x268; i < 0x270; i++)
+ for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++)
write_mtrr(&nvram_pos, i);
/* Disable access to AMD RdDram and WrDram extension bits */
@@ -55,7 +55,7 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
wrmsr(SYSCFG_MSR, msr_data);
/* Variable MTRRs */
- for (i = 0x200; i < 0x210; i++)
+ for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++)
write_mtrr(&nvram_pos, i);
/* SYSCFG_MSR */
@@ -89,21 +89,21 @@ void restore_mtrr(void)
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
- wrmsr(0x250, msr_data);
+ wrmsr(MTRR_FIX_64K_00000, msr_data);
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
- wrmsr(0x258, msr_data);
+ wrmsr(MTRR_FIX_16K_80000, msr_data);
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
msrPtr ++;
- wrmsr(0x259, msr_data);
+ wrmsr(MTRR_FIX_16K_A0000, msr_data);
- for (msr = 0x268; msr <= 0x26F; msr++) {
+ for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
@@ -117,7 +117,7 @@ void restore_mtrr(void)
wrmsr(SYSCFG_MSR, msr_data);
/* Restore the Variable MTRRs */
- for (msr = 0x200; msr <= 0x20F; msr++) {
+ for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) {
msr_data.lo = *msrPtr;
msrPtr ++;
msr_data.hi = *msrPtr;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 02:45:30 +0000