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-rw-r--r--src/soc/intel/baytrail/hda.c5
-rw-r--r--src/soc/intel/common/hda_verb.c13
2 files changed, 13 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index 010150faad..9e4140dcee 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -31,11 +31,6 @@
#include <baytrail/ramstage.h>
static const struct reg_script init_ops[] = {
- /* Set up VC0 and VC1. */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022),
- /* Enable VCi */
- REG_PCI_WRITE32(0x120, 0x81000022),
/* Enable no snoop traffic. */
REG_PCI_OR16(0x78, 1 << 11),
/* Configure HDMI codec connection. */
diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c
index bd61ceeca4..2523b41000 100644
--- a/src/soc/intel/common/hda_verb.c
+++ b/src/soc/intel/common/hda_verb.c
@@ -70,6 +70,19 @@ int hda_codec_detect(u8 *base)
/* Write back the value once reset bit is set. */
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
+ /* Clear the "State Change Status Register" STATESTS bits
+ * for each of the "SDIN Stat Change Status Flag"
+ */
+ write8(base + HDA_STATESTS_REG, 0xf);
+
+ /* Turn off the link and poll RESET# bit until it reads back as 0 */
+ if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
+ goto no_codec;
+
+ /* Turn on the link and poll RESET# bit until it reads back as 1 */
+ if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ goto no_codec;
+
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + HDA_STATESTS_REG);
reg8 &= 0x0f;