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-rw-r--r--src/drivers/usb/pci_ehci.c10
-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c4
-rw-r--r--src/soc/intel/broadwell/usb_debug.c8
-rw-r--r--src/southbridge/amd/agesa/hudson/enable_usbdebug.c3
-rw-r--r--src/southbridge/amd/pi/hudson/enable_usbdebug.c3
-rw-r--r--src/southbridge/amd/sb600/enable_usbdebug.c5
-rw-r--r--src/southbridge/amd/sb700/enable_usbdebug.c6
-rw-r--r--src/southbridge/amd/sb800/enable_usbdebug.c3
-rw-r--r--src/southbridge/intel/common/usb_debug.c6
-rw-r--r--src/southbridge/nvidia/ck804/enable_usbdebug.c5
-rw-r--r--src/southbridge/nvidia/mcp55/enable_usbdebug.c5
-rw-r--r--src/southbridge/sis/sis966/enable_usbdebug.c5
12 files changed, 8 insertions, 55 deletions
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index de291ee258..8b72f57a5a 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -47,12 +47,18 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */
- u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
- if (dbg_bar != EHCI_BAR_INDEX)
+ u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
+ if (ehci_bar != EHCI_BAR_INDEX)
return -1;
+ pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
+
+ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+
*base = CONFIG_EHCI_BAR;
*dbg_offset = (cap>>16) & 0x1ffc;
+
return 0;
}
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 675f4b7870..db1e4cf231 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -53,8 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY
- | PCI_COMMAND_MASTER);
}
diff --git a/src/soc/intel/broadwell/usb_debug.c b/src/soc/intel/broadwell/usb_debug.c
index 683b4cc522..b19462dc3e 100644
--- a/src/soc/intel/broadwell/usb_debug.c
+++ b/src/soc/intel/broadwell/usb_debug.c
@@ -41,12 +41,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- if (!dev)
- return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index fce7f5b33b..4a37e557b6 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index 787da6b676..cb6961ae40 100644
--- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 797f6d2836..8b19cc41de 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -35,9 +35,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 22f730f4ed..6d95b8ee4f 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -48,10 +48,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
}
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 3959ea8013..8ef3151f13 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */
outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA);
-
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index eeac6d92dc..e1cd6575d0 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -63,10 +63,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Bail out. No console to complain in. */
if (!dev)
return;
-
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 0f0e4cddbc..4ae4aa0052 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index dfeb351b67..679a71d7b3 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 477f724100..428af9429a 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -46,9 +46,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- /* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
- /* Enable access to the EHCI memory space registers. */
- pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 19:58:20 +0000