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-rw-r--r--src/cpu/via/car/cache_as_ram.inc2
-rw-r--r--src/cpu/x86/car/cache_as_ram.inc2
-rw-r--r--src/lib/debug.c78
-rw-r--r--src/mainboard/tyan/s2735/romstage.c2
-rw-r--r--src/mainboard/via/epia-m700/romstage.c2
-rw-r--r--src/mainboard/via/vt8454c/acpi_tables.c4
-rw-r--r--src/mainboard/via/vt8454c/debug.c108
-rw-r--r--src/mainboard/via/vt8454c/romstage.c7
-rw-r--r--src/northbridge/via/cx700/cx700_early_smbus.c6
-rw-r--r--src/northbridge/via/cx700/cx700_lpc.c8
-rw-r--r--src/northbridge/via/cx700/cx700_reset.c1
-rw-r--r--src/northbridge/via/cx700/raminit.c24
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c2
-rw-r--r--src/superio/via/vt1211/vt1211.c6
14 files changed, 94 insertions, 158 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 605e7f4aed..ba0fadfec5 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -163,7 +163,7 @@ testok: movb $0x40,%al
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %eax /* bist */
- call amd64_main
+ call stage1_main
/* We will not go back */
fixed_mtrr_msr:
diff --git a/src/cpu/x86/car/cache_as_ram.inc b/src/cpu/x86/car/cache_as_ram.inc
index cd37ac39ab..1b160ea20c 100644
--- a/src/cpu/x86/car/cache_as_ram.inc
+++ b/src/cpu/x86/car/cache_as_ram.inc
@@ -289,7 +289,7 @@ lout:
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %eax /* bist */
- call amd64_main
+ call stage1_main
/* We will not go back */
fixed_mtrr_msr:
diff --git a/src/lib/debug.c b/src/lib/debug.c
index ab7c1f8562..35d1f90bcb 100644
--- a/src/lib/debug.c
+++ b/src/lib/debug.c
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
static void print_debug_pci_dev(unsigned dev)
{
@@ -9,17 +29,16 @@ static void print_debug_pci_dev(unsigned dev)
print_debug_hex8((dev >> 8) & 7);
}
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
+ for (dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+ u32 id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
print_debug_pci_dev(dev);
@@ -32,8 +51,8 @@ static void dump_pci_device(unsigned dev)
int i;
print_debug_pci_dev(dev);
print_debug("\n");
-
- for(i = 0; i <= 255; i++) {
+
+ for (i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
@@ -48,19 +67,42 @@ static void dump_pci_device(unsigned dev)
}
}
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
{
device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
+ for (dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+ u32 id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0xffff)
+ || (((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
+
+
+static inline void dump_io_resources(unsigned port)
+{
+
+ int i;
+ udelay(2000);
+ print_debug_hex16(port);
+ print_debug(":\n");
+ for (i = 0; i < 256; i++) {
+ u8 val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = inb(port);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\n");
+ }
+ port++;
+ }
+}
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index b9a566ef11..22a94c68fd 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -65,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/x86/car/copy_and_run.c"
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 316c0be8c1..91ddfee82e 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -394,7 +394,7 @@ void EmbedComInit(void)
}
/* cache_as_ram.inc jumps to here. */
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
{
unsigned cpu_reset = 0;
u16 boot_mode;
diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c
index dbd53f3fa6..b065c1fa5f 100644
--- a/src/mainboard/via/vt8454c/acpi_tables.c
+++ b/src/mainboard/via/vt8454c/acpi_tables.c
@@ -52,7 +52,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
-void acpi_create_via_hpet(acpi_hpet_t * hpet)
+static void acpi_create_via_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfe800000ULL
acpi_header_t *header = &(hpet->header);
@@ -182,7 +182,7 @@ unsigned long write_acpi_tables(unsigned long start)
dsdt = (acpi_header_t *) current;
current += AmlCode.length;
memcpy((void *) dsdt, &AmlCode,AmlCode.length);
-#if DONT_TRUST_IASL
+#ifdef DONT_TRUST_IASL
dsdt->checksum = 0; // don't trust intel iasl compiler to get this right
dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
#endif
diff --git a/src/mainboard/via/vt8454c/debug.c b/src/mainboard/via/vt8454c/debug.c
deleted file mode 100644
index 3212495f71..0000000000
--- a/src/mainboard/via/vt8454c/debug.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
- device_t dev;
- for (dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
- u32 id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
- || (((id >> 16) & 0xffff) == 0xffff)
- || (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- print_debug_pci_dev(dev);
- print_debug("\n");
- }
-}
-
-static void dump_pci_device(unsigned dev)
-{
- int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
-
- for (i = 0; i <= 255; i++) {
- unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
- }
-}
-
-static void dump_pci_devices(void)
-{
- device_t dev;
- for (dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
- u32 id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)
- || (((id >> 16) & 0xffff) == 0xffff)
- || (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
-}
-
-
-static void dump_io_resources(unsigned port)
-{
-
- int i;
- udelay(2000);
- print_debug_hex16(port);
- print_debug(":\n");
- for (i = 0; i < 256; i++) {
- u8 val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
- val = inb(port);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
- port++;
- }
-}
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index 0680fe1b2a..b133c6ad85 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -30,7 +30,6 @@
#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cx700/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#define DEACTIVATE_CAR 1
@@ -38,9 +37,8 @@
#include "cpu/x86/car/copy_and_run.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/via/cx700/cx700_early_smbus.c"
-#include "debug.c"
+#include "lib/debug.c"
#include "northbridge/via/cx700/cx700_early_serial.c"
#include "northbridge/via/cx700/raminit.c"
@@ -126,7 +124,8 @@ static void main(unsigned long bist)
copy_and_run(0);
}
-void amd64_main(unsigned long bist) {
+void stage1_main(unsigned long bist)
+{
main(bist);
}
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index 361b5e9bca..b1d6344f6d 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -57,6 +57,7 @@
#endif
/* Internal functions */
+#if CONFIG_DEBUG_SMBUS
static void smbus_print_error(unsigned char host_status_register, int loops)
{
/* Check if there actually was an error */
@@ -87,6 +88,7 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
print_err("Host Busy\n");
}
}
+#endif
static void smbus_wait_until_ready(void)
{
@@ -127,7 +129,7 @@ static void set_ics_data(unsigned char dev, int data, char len)
inb(SMBHSTCTL);
/* fill blocktransfer array */
- if (dev = 0xd2) {
+ if (dev == 0xd2) {
//char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
outb(0x0d, SMBBLKDAT);
outb(0x00, SMBBLKDAT);
@@ -231,7 +233,7 @@ static void enable_smbus(void)
}
/* Debugging Function */
-#ifdef CONFIG_DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
static void dump_spd_data(const struct mem_controller *ctrl)
{
int dimm, offset, regs;
diff --git a/src/northbridge/via/cx700/cx700_lpc.c b/src/northbridge/via/cx700/cx700_lpc.c
index d6495aba61..02beb86283 100644
--- a/src/northbridge/via/cx700/cx700_lpc.c
+++ b/src/northbridge/via/cx700/cx700_lpc.c
@@ -84,7 +84,7 @@ static void pci_routing_fixup(struct device *dev)
* can't figure out how to do !!!!
*/
-void setup_pm(device_t dev)
+static void setup_pm(device_t dev)
{
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
@@ -236,7 +236,7 @@ static void cx700_set_lpc_registers(struct device *dev)
}
-void cx700_read_resources(device_t dev)
+static void cx700_read_resources(device_t dev)
{
struct resource *res;
@@ -258,7 +258,7 @@ void cx700_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-void cx700_set_resources(device_t dev)
+static void cx700_set_resources(device_t dev)
{
struct resource *resource;
resource = find_resource(dev, 1);
@@ -266,7 +266,7 @@ void cx700_set_resources(device_t dev)
pci_dev_set_resources(dev);
}
-void cx700_enable_resources(device_t dev)
+static void cx700_enable_resources(device_t dev)
{
/* Enable SuperIO decoding */
pci_dev_enable_resources(dev);
diff --git a/src/northbridge/via/cx700/cx700_reset.c b/src/northbridge/via/cx700/cx700_reset.c
index 80e09d7fab..83439881f6 100644
--- a/src/northbridge/via/cx700/cx700_reset.c
+++ b/src/northbridge/via/cx700/cx700_reset.c
@@ -18,6 +18,7 @@
*/
#include <arch/io.h>
+#include <reset.h>
void hard_reset(void)
{
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index d28b8e37c4..d68ad3b2c2 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -103,15 +103,15 @@
} while ( 0 )
#define REGISTERPRESET(bus,dev,fun,bdfspec) \
- { u8 i, reg; \
- for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
+ { u8 j, reg; \
+ for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \
printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
- printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
+ printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \
printk(BIOS_DEBUG, "\n"); \
- reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
- reg &= (bdfspec)[i].mask; \
- reg |= (bdfspec)[i].val; \
- pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \
+ reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg); \
+ reg &= (bdfspec)[j].mask; \
+ reg |= (bdfspec)[j].val; \
+ pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg, reg); \
} \
}
@@ -1436,23 +1436,23 @@ static void sdram_enable(const struct mem_controller *ctrl)
{ 0x67, ~0x03, 0x01},
{ 0x5b, ~0x01, 0x00},
{ 0x8d, ~0x02, 0x02},
- { 0x97, ~0x80, 0x00},
+ { 0x97, 0x7f, 0x00},
{ 0xd2, ~0x18, 0x00},
{ 0xe2, ~0x36, 0x06},
- { 0xe4, ~0x80, 0x00},
+ { 0xe4, 0x7f, 0x00},
{ 0xe5, 0x00, 0x40},
{ 0xe6, 0x00, 0x20},
- { 0xe7, ~0xd0, 0xc0},
+ { 0xe7, 0x2f, 0xc0},
{ 0xec, ~0x08, 0x00}
}, b0d17f7[] = {
- { 0x4e, ~0x80, 0x80},
+ { 0x4e, 0x7f, 0x80},
{ 0x4f, ~(1 << 6), 1 << 6 }, /* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */
{ 0x74, ~0x00, 0x04}, /* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */
{ 0x7c, ~0x00, 0x02}, /* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */
{ 0xe6, 0x0, 0x04} // MSI post
}, b0d19f0[] = { /* P2PE */
{ 0x42, ~0x08, 0x08}, // Disable HD Audio,
- { 0x40, ~0xc0, 0x80} // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
+ { 0x40, 0x3f, 0x80} // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
}, b0d0f2[] = {
{ 0x50, ~0x40, 0x88},
{ 0x51, 0x80, 0x7b},
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 22c0fbd40f..a9f22ac0f1 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -300,7 +300,7 @@ void EmbedComInit()
/* cache_as_ram.inc jump to here
*/
-void amd64_main(unsigned long bist)
+void stage1_main(unsigned long bist)
{
unsigned cpu_reset = 0;
u16 boot_mode;
diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c
index 06b4f57596..1b98ae666e 100644
--- a/src/superio/via/vt1211/vt1211.c
+++ b/src/superio/via/vt1211/vt1211.c
@@ -117,7 +117,7 @@ static void vt1211_init(struct device *dev)
}
}
-void vt1211_pnp_enable_resources(device_t dev)
+static void vt1211_pnp_enable_resources(device_t dev)
{
printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev));
pnp_enter_ext_func_mode(dev);
@@ -125,7 +125,7 @@ void vt1211_pnp_enable_resources(device_t dev)
pnp_exit_ext_func_mode(dev);
}
-void vt1211_pnp_set_resources(struct device *dev)
+static void vt1211_pnp_set_resources(struct device *dev)
{
int i;
struct resource *resource;
@@ -178,7 +178,7 @@ void vt1211_pnp_set_resources(struct device *dev)
pnp_exit_ext_func_mode(dev);
}
-void vt1211_pnp_enable(device_t dev)
+static void vt1211_pnp_enable(device_t dev)
{
if (!dev->enabled) {
pnp_enter_ext_func_mode(dev);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 11:23:05 +0000