3 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index cc1bfae95c..62cbd50fc2 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
+ * Copyright 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -94,6 +94,10 @@ static void setup_pinmux(void)
 	// EC in RW.
 	gpio_input_pullup(GPIO(U4));
 
+	// route PU4/5 to GMI to remove conflict w/PWM1/2.
+	pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR);        //s/b GMI
+	pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR);        //s/b GMI
+
 	// SOC and TPM reset GPIO, active low.
 	gpio_output(GPIO(I5), 1);
 
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 48d3842aa2..62cbd50fc2 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -94,6 +94,10 @@ static void setup_pinmux(void)
 	// EC in RW.
 	gpio_input_pullup(GPIO(U4));
 
+	// route PU4/5 to GMI to remove conflict w/PWM1/2.
+	pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR);        //s/b GMI
+	pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR);        //s/b GMI
+
 	// SOC and TPM reset GPIO, active low.
 	gpio_output(GPIO(I5), 1);
 
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 48d3842aa2..62cbd50fc2 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -94,6 +94,10 @@ static void setup_pinmux(void)
 	// EC in RW.
 	gpio_input_pullup(GPIO(U4));
 
+	// route PU4/5 to GMI to remove conflict w/PWM1/2.
+	pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR);        //s/b GMI
+	pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR);        //s/b GMI
+
 	// SOC and TPM reset GPIO, active low.
 	gpio_output(GPIO(I5), 1);