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-rw-r--r--src/cpu/amd/pi/Makefile.inc3
-rw-r--r--src/cpu/amd/pi/cache_as_ram.inc170
-rw-r--r--src/cpu/amd/pi/romstage.c48
-rw-r--r--src/mainboard/amd/bettong/romstage.c15
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c19
-rw-r--r--src/mainboard/amd/lamar/romstage.c16
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c16
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c16
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c16
9 files changed, 76 insertions, 243 deletions
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index ecbc386fb6..3fef7e8580 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -19,8 +19,9 @@ subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
ramstage-$(CONFIG_SPI_FLASH) += spi.c
-cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
+romstage-y += romstage.c
romstage-y += ../agesa/heapmanager.c
ramstage-y += ../agesa/heapmanager.c
ramstage-y += amd_late_init.c
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
deleted file mode 100644
index 55480070c9..0000000000
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/******************************************************************************
- * AMD Generic Encapsulated Software Architecture
- *
- * $Workfile:: cache_as_ram.inc
- *
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
- *
- ******************************************************************************
- */
-
-#include "gcccar.inc"
-#include <cpu/x86/cache.h>
-
-/*
- * XMM map:
- * xmm0: BIST
- * xmm1: backup ebx -- cpu_init_detected
- */
-
-.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
-
-cache_as_ram_setup:
-
- post_code(0xa0)
-
- /* enable SSE2 128bit instructions */
- /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
- movl %cr4, %eax
- orl $(3 << 9), %eax
- movl %eax, %cr4
-
- /* Get the cpu_init_detected */
- mov $1, %eax
- cpuid
- shr $24, %ebx
-
- /* Save the BIST result */
- cvtsi2sd %ebp, %xmm0
-
- /* for normal part %ebx already contain cpu_init_detected from fallback call */
-
- /* Save the cpu_init_detected */
- cvtsi2sd %ebx, %xmm1
-
- post_code(0xa1)
-
- AMD_ENABLE_STACK
-
- /* Align the stack. */
- and $0xFFFFFFF0, %esp
-
-#ifdef __x86_64__
- /* switch to 64 bit long mode */
- mov %esi, %ecx
- add $0, %ecx # core number
- xor %eax, %eax
- lea (0x1000+0x23)(%ecx), %edi
- mov %edi, (%ecx)
- mov %eax, 4(%ecx)
-
- lea 0x1000(%ecx), %edi
- movl $0x000000e3, 0x00(%edi)
- movl %eax, 0x04(%edi)
- movl $0x400000e3, 0x08(%edi)
- movl %eax, 0x0c(%edi)
- movl $0x800000e3, 0x10(%edi)
- movl %eax, 0x14(%edi)
- movl $0xc00000e3, 0x18(%edi)
- movl %eax, 0x1c(%edi)
-
- # load ROM based identity mapped page tables
- mov %ecx, %eax
- mov %eax, %cr3
-
- # enable PAE
- mov %cr4, %eax
- bts $5, %eax
- mov %eax, %cr4
-
- # enable long mode
- mov $0xC0000080, %ecx
- rdmsr
- bts $8, %eax
- wrmsr
-
- # enable paging
- mov %cr0, %eax
- bts $31, %eax
- mov %eax, %cr0
-
- # use call far to switch to 64-bit code segment
- ljmp $0x18, $1f
-1:
- /* Pass the cpu_init_detected */
- cvtsd2si %xmm1, %esi
-
- /* Pass the BIST result */
- cvtsd2si %xmm0, %edi
-
-
- .code64
- call cache_as_ram_main
- .code32
-
-#else
-
- /* Restore the BIST result */
- cvtsd2si %xmm0, %edx
-
- /* Restore the cpu_init_detected */
- cvtsd2si %xmm1, %ebx
-
- /* Must maintain 16-byte stack alignment here. */
- pushl $0x0
- pushl $0x0
- pushl %ebx /* init detected */
- pushl %edx /* bist */
- call cache_as_ram_main
-#endif
-
- /* Should never see this postcode */
- post_code(0xaf)
-stop:
- jmp stop
-
-disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
- /* Disable cache */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- AMD_DISABLE_STACK
-
- /* enable cache */
- movl %cr0, %eax
- andl $0x9fffffff, %eax
- movl %eax, %cr0
- xorl %eax, %eax
-
- /* Restore the return stack */
- wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
-
-cache_as_ram_setup_out:
-#ifdef __x86_64__
-.code64
-#endif
diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c
new file mode 100644
index 0000000000..393cbd4aeb
--- /dev/null
+++ b/src/cpu/amd/pi/romstage.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Kyösti Mälkki
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <cpu/amd/car.h>
+#include <cpu/x86/mtrr.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+void asmlinkage early_all_cores(void)
+{
+ amd_initmmio();
+}
+
+void * asmlinkage romstage_main(unsigned long bist)
+{
+ uintptr_t stack_top = CACHE_TMP_RAMTOP;
+ u8 initial_apic_id = cpuid_ebx(1) >> 24;
+
+ /* Only BSP returns from here. */
+ cache_as_ram_main(bist, initial_apic_id);
+
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ return (void*)stack_top;
+}
+
+void asmlinkage romstage_after_car(void)
+{
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+
+ agesa_postcar(NULL);
+
+ run_ramstage();
+}
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 29cd8a7284..eefae85337 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -20,6 +20,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +29,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -62,18 +60,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+
+void agesa_postcar(struct sysinfo *cb)
+{
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 0ba1c1dfea..4da974796b 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -32,11 +33,7 @@
#include <southbridge/amd/pi/hudson/hudson.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
+{ u32 val;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@@ -78,19 +75,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 5530a25e84..bbd5ad0528 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -40,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -89,16 +87,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index c98ae25bc0..ff2c4c411d 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -35,9 +36,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -88,20 +86,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index d8342c917f..576a3eefbb 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -39,9 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". This following register setting has been
@@ -82,20 +80,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index c95adb6555..1ccf7c4e36 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -52,8 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xD2, 0xcd6);
outb(0x00, 0xcd7);
- amd_initmmio();
-
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
@@ -85,27 +84,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+}
+void agesa_postcar(struct sysinfo *cb)
+{
//PspMboxBiosCmdDramInfo();
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
init_tpm(false);
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
-
- post_code(0x50);
- copy_and_run();
-
- post_code(0x54); /* Should never see this post code. */
}
-
static void early_lpc_init(void)
{
u32 setting = 0x0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 01:36:38 +0000