diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/quartet/auto.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_early_smbus.c | 32 |
2 files changed, 35 insertions, 2 deletions
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c index 31a653d982..23951738c6 100644 --- a/src/mainboard/amd/quartet/auto.c +++ b/src/mainboard/amd/quartet/auto.c @@ -99,9 +99,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) unsigned hub = device >> 8; device &= 0xff; - // smbus_write_byte(SMBUS_HUB, hub); + smbus_write_byte(SMBUS_HUB, 0x01, 1<<hub); + smbus_write_byte(SMBUS_HUB, 0x03, 0); + return smbus_read_byte(device, address); - } /* no specific code here. this should go away completely */ diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index e67d414933..e0aaa05ff4 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -106,3 +106,35 @@ static int smbus_read_byte(unsigned device, unsigned address) } return byte; } + +static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ +#if 0 + if (smbus_wait_until_ready() < 0) { + return; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), + SMBUS_IO_BASE + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR); + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data write */ /* FIXME */ + outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL); + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); + + /* clear the data word...*/ + outw(val, SMBUS_IO_BASE + SMBHSTDAT); + + /* start the command */ + outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); +#endif + return; +} |