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-rw-r--r--src/southbridge/amd/amd8111/ide.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/bootblock.c2
-rw-r--r--src/southbridge/amd/cimx/sb800/fan.c24
-rw-r--r--src/southbridge/amd/cimx/sb900/bootblock.c4
-rw-r--r--src/southbridge/amd/rs780/gfx.c2
-rw-r--r--src/southbridge/ricoh/rl5c476/rl5c476.c2
-rw-r--r--src/southbridge/sis/sis966/ide.c2
-rw-r--r--src/southbridge/sis/sis966/nic.c6
-rw-r--r--src/southbridge/via/vt8237r/early_smbus.c2
-rw-r--r--src/southbridge/via/vt8237r/lpc.c4
11 files changed, 27 insertions, 27 deletions
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index a7eee35659..fec424d36b 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -33,7 +33,7 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word);
- byte = 0x20 ; // Latency: 64-->32
+ byte = 0x20; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
word = 0x0f;
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 2f67a36106..e10bb05ca9 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -29,7 +29,7 @@ static void sb700_enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/
dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ //dword |= (1<<6) | (1<<29) | (1<<30);
/*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword);
@@ -42,7 +42,7 @@ static void sb700_enable_rom(void)
* BIT21: Port Enable for Port 0x80
*/
dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+ dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 89e56b6505..008a19b11e 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -28,7 +28,7 @@ static void enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/
dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ //dword |= (1<<6) | (1<<29) | (1<<30);
/* Turn on all of LPC IO Port decode enable */
dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword);
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index e37fc3d94c..5925330f11 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];
/* EC LDN9 function 83 zone 0 - Temperature Thresholds */
@@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;
sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];
/*EC LDN9 function 85 zone 0 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
}
@@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];
/* EC LDN9 function 83 zone 1 - Temperature Thresholds */
@@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;
sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];
/* EC LDN9 function 85 zone 1 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
}
@@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];
/* EC LDN9 function 83 zone 2 */
@@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;
sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];
/* EC LDN9 function 85 zone 2 */
sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
}
@@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];
/* EC LDN9 function 83 zone 3 */
@@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;
sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];
/* EC LDN9 function 85 zone 3 */
sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT ; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
}
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index 50d3087641..a06946352c 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -28,7 +28,7 @@ static void sb900_enable_rom(void)
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/
dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ //dword |= (1<<6) | (1<<29) | (1<<30);
/*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword);
@@ -41,7 +41,7 @@ static void sb900_enable_rom(void)
* BIT21: Port Enable for Port 0x80
*/
dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+ dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index c2b3d3a8c2..52bc071d4c 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -302,7 +302,7 @@ static void poweron_ddi_lanes(device_t nb_dev)
ddi_pads = ~(nbpcie_ind_read_index(nb_dev, 0x65)); /* save original setting */
gfx_cfg = nbmisc_read_index(nb_dev, 0x74);
- for (i = 0; i < 3 ; i++) {
+ for (i = 0; i < 3; i++) {
if (gfx_cfg & GFX_CONFIG_DDI) {
ddi_pads |= (3 << (i * 2));
}
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 8284ec810e..78561cc15b 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -184,7 +184,7 @@ static void rl5c476_set_resources(device_t dev)
if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
if ( !(resource->flags & IORESOURCE_STORED) ){
- resource->flags |= IORESOURCE_STORED ;
+ resource->flags |= IORESOURCE_STORED;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;
}
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index 56862270cc..6c7c7fe568 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -133,7 +133,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
pci_write_config16(dev, 0x50, word);
- byte = 0x20 ; // Latency: 64-->32
+ byte = 0x20; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index a167848b26..448514b000 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -73,7 +73,7 @@ static void readApcMacAddr(void)
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
printk(BIOS_DEBUG, "MAC addr in APC = ");
- for (i = 0x9 ; i <=0xe ; i++) {
+ for (i = 0x9; i <=0xe; i++) {
printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
}
printk(BIOS_DEBUG, "\n");
@@ -97,7 +97,7 @@ static void set_apc(struct device *dev)
outl(0x80001048,0xcf8);
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
- for (i = 0 ; i <3; i++) {
+ for (i = 0; i <3; i++) {
addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
@@ -139,7 +139,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
mdelay(10);
- for (i=0 ; i <= LoopNum; i++) {
+ for (i=0; i <= LoopNum; i++) {
ulValue=read32(base + 0x3c);
if (!(ulValue & 0x0080)) //BIT_7
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index 23f5928e34..96a5c1b49d 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -347,7 +347,7 @@ int acpi_get_sleep_type(void)
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
printk(BIOS_DEBUG, "%02x", tmp);
- return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+ return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
}
#if defined(__GNUC__)
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index dd3bcae3fd..9d91749379 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -51,7 +51,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin)
{
static unsigned char Irqs[4];
int i;
- for (i = 0 ; i < 4 ; i++)
+ for (i = 0; i < 4; i++)
Irqs[i] = pciIrqs[ pin[i] - 'A' ];
return Irqs;
@@ -253,7 +253,7 @@ static void setup_pm(device_t dev)
int acpi_get_sleep_type(void)
{
u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
- return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+ return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
}
static void vt8237r_init(struct device *dev)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 15:38:28 +0000