diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/solo/Config.lb | 463 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/auto.c | 34 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/chip.h | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/mainboard.c | 33 |
4 files changed, 306 insertions, 229 deletions
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb index 12c59fdb38..3fe6ed6b5d 100644 --- a/src/mainboard/amd/solo/Config.lb +++ b/src/mainboard/amd/solo/Config.lb @@ -1,186 +1,179 @@ -# -### -### Build code to export a CMOS option table -### -default HAVE_OPTION_TABLE=1 -option HAVE_MP_TABLE=0 -#### -#### Build options -#### -# -### -### Location of the DIMM EEPROMS on the SMBUS -### This is fixed into a narrow range by the DIMM package standard. -### -option SMBUS_MEM_DEVICE_START=(0xa << 3) -option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1) -option SMBUS_MEM_DEVICE_INC=1 -default CONFIG_CONSOLE_VGA=0 -default CONFIG_CONSOLE_LOGBUF=0 -default CONFIG_CONSOLE_SROM=0 -default CONFIG_SMP=0 -default CONFIG_UDELAY_TSC=0 -# -### -### Customize our winbond superio chip for this motherboard -### -option CONFIG_CONSOLE_SERIAL8250=0 -# -### -### Build code for the fallback boot -### +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses MAINBOARD +uses ARCH +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_STREAM_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE + +### +### Build options +### + +## +## Build code for the fallback boot +## option HAVE_FALLBACK_BOOT=1 -# -### -### Build code to reset the motherboard from linuxBIOS -### -## option HAVE_HARD_RESET=1 -# -### -### Build code to export a programmable irq routing table -### + +## +## Build code to reset the motherboard from linuxBIOS +## +option HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## option HAVE_PIRQ_TABLE=1 option IRQ_SLOT_COUNT=7 -# -### -### Build code to export an x86 MP table -### Useful for specifying IRQ routing values -### -##option HAVE_MP_TABLE=1 -# -### -### Build code for SMP support -### Only worry about 2 micro processors -### -##option CONFIG_SMP=1 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +option HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +option HAVE_OPTION_TABLE=1 + +## +## AMD Solo is a 1cpu board +## +option CONFIG_SMP=0 option CONFIG_MAX_CPUS=1 -# -### -### Build code to setup a generic IOAPIC -### + +## +## Build code to setup a generic IOAPIC +## option CONFIG_IOAPIC=1 -# -### -### MEMORY_HOLE instructs earlymtrr.inc to -### enable caching from 0-640KB and to disable -### caching from 640KB-1MB using fixed MTRRs -### -### Enabling this option breaks SMP because secondary -### CPU identification depends on only variable MTRRs -### being enabled. -### -option MEMORY_HOLE=0 -# -### -### Clean up the motherboard id strings -### -option MAINBOARD_PART_NUMBER="Solo7" + +## +## Clean up the motherboard id strings +## +option MAINBOARD_PART_NUMBER="SOLO7" option MAINBOARD_VENDOR="AMD" -# -### -### Figure out which type of linuxBIOS image to build -### If we aren't a fallback image we must be a normal image -### This is useful for optional includes -### -default USE_FALLBACK_IMAGE=0 -# -#### -#### LinuxBIOS layout values -#### -# -### ROM_SIZE is the size of boot ROM that this board will use. -option ROM_SIZE=262144 -# -### ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. -option ROM_IMAGE_SIZE=65535 -# -### -### Use a small 8K stack -### + +### +### LinuxBIOS layout values +### + +## ROM_SIZE is the size of boot ROM that this board will use. +option ROM_SIZE = 262144 + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +option ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## option STACK_SIZE=0x2000 -# -### -### Use a small 8K heap -### -option HEAP_SIZE=0x2000 -# -### -### Only use the option table in a normal image -### -option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE -# -### -### Compute the location and size of where this firmware image -### (linuxBIOS plus bootloader) will live in the boot rom chip. -### -default FALLBACK_SIZE=65536 -if USE_FALLBACK_IMAGE - option ROM_SECTION_SIZE = FALLBACK_SIZE - option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) + +## +## Use a small 16K heap +## +option HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + option ROM_SECTION_SIZE = FALLBACK_SIZE + option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else - option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - option ROM_SECTION_OFFSET= 0 + option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + option ROM_SECTION_OFFSET = 0 end -# -### -### Compute the start location and size size of -### The linuxBIOS bootloader. -### -option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) option CONFIG_ROM_STREAM = 1 -# -### -### Compute where this copy of linuxBIOS will start in the boot rom -### -option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE) -# -### -### Compute a range of ROM that can cached to speed up linuxBIOS, -### execution speed. -### -##expr XIP_ROM_SIZE = 65536 -##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE -##option XIP_ROM_SIZE=65536 -##option XIP_ROM_BASE=0xffff0000 -# -## XIP_ROM_SIZE && XIP_ROM_BASE values that work. -##option XIP_ROM_SIZE=0x8000 -##option XIP_ROM_BASE=0xffff8000 -# -### -### Set all of the defaults for an x86 architecture -### -# -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +option XIP_ROM_SIZE=65536 +option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end +#cpu k8 end + +## +## Build the objects we have code for in this directory. +## + +#object mainboard.o driver mainboard.o -object static_devices.o +#object static_devices.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -# -arch i386 end -cpu k8 end -# -option DEBUG=1 -default USE_FALLBACK_IMAGE=1 -option A=(1+2) -option B=0xa -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### +object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E" +end + +makerule ./failover.inc + depends "./failover.E ./romcc" + action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c" + action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" +end +makerule ./auto.inc + depends "./auto.E ./romcc" + action "./romcc -mcpu=k8 -O ./auto.E > auto.inc" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### + +## +## Build our reset vector (This is where linuxBIOS is entered) +## if USE_FALLBACK_IMAGE mainboardinit cpu/i386/reset16.inc ldscript /cpu/i386/reset16.lds @@ -188,74 +181,92 @@ else mainboardinit cpu/i386/reset32.inc ldscript /cpu/i386/reset32.lds end -# -#### Should this be in the northbridge code? -#mainboardinit archi386/lib/cpu_reset.inc -# -### -### Include an id string (For safe flashing) -### + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -# -#### -#### This is the early phase of linuxBIOS startup -#### Things are delicate and we test to see if we should -#### failover to another image. -#### -option MAX_REBOOT_CNT=2 -if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end -# -### -### Setup our mtrrs -### + +## +## Setup our mtrrs +## mainboardinit cpu/k8/earlymtrr.inc -# -# -#### -#### O.k. We aren't just an intermediary anymore! -#### -# + ### -### When debugging disable the watchdog timer +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. ### -##option MAXIMUM_CONSOLE_LOGLEVEL=7 -#default MAXIMUM_CONSOLE_LOGLEVEL=7 -# -### -### Setup the serial port -### -#mainboardinit superiowinbond/w83627hf/setup_serial.inc -mainboardinit pc80/serial.inc -mainboardinit arch/i386/lib/console.inc -if USE_FALLBACK_IMAGE mainboardinit archi386/lib/noop_failover.inc end -# +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + ### -### Romcc output +### O.k. We aren't just an intermediary anymore! ### -#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit .failover.inc -makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" -makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" + +## +## Setup RAM +## +mainboardinit cpu/k8/enable_mmx_sse.inc mainboardinit ./auto.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 -end -southbridge amd/amd8111 +mainboardinit cpu/k8/disable_mmx_sse.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +northbridge amd/amdk8 "mc0" + pci 0:18.0 + pci 0:18.0 + pci 0:18.0 + pci 0:18.1 + pci 0:18.2 + pci 0:18.3 + southbridge amd/amd8111 "amd8111" + pci 0:0.0 + pci 0:1.0 + pci 0:1.1 + pci 0:1.2 + pci 0:1.3 + pci 0:1.5 + pci 0:1.6 + superio NSC/pc87360 + pnp 1:2e.0 + pnp 1:2e.1 + pnp 1:2e.2 + pnp 1:2e.3 + pnp 1:2e.4 + pnp 1:2e.5 + pnp 1:2e.6 + pnp 1:2e.7 + pnp 1:2e.8 + pnp 1:2e.9 + pnp 1:2e.a + register "com1" = "{1, 0, 0x3f8, 4}" + register "lpt" = "{1}" + end + end + southbridge amd/amd8151 "amd8151" + pci 0:0.0 + pci 0:1.0 + end end -#mainboardinit archi386/smp/secondary.inc -superio NSC/pc87360 - register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1" + +cpu k8 "cpu0" + register "up" = "{ .chip = &amd8111, .ht_width=16, .ht_speed=600 }" end -dir /pc80 -##dir /src/superio/winbond/w83627hf -cpu p5 end -cpu p6 end -cpu k7 end -cpu k8 end + +## +## Include the old serial code for those few places that still need it. +## +mainboardinit pc80/serial.inc +mainboardinit arch/i386/lib/console.inc + diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c index 895d97ea14..27b476c19c 100644 --- a/src/mainboard/amd/solo/auto.c +++ b/src/mainboard/amd/solo/auto.c @@ -1,6 +1,4 @@ #define ASSEMBLY 1 -#define MAXIMUM_CONSOLE_LOGLEVEL 9 -#define DEFAULT_CONSOLE_LOGLEVEL 9 #include <stdint.h> #include <device/pci_def.h> @@ -20,12 +18,21 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#define SIO_BASE 0x2e + static void memreset_setup(void) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ } static void memreset(int controllers, const struct mem_controller *ctrl) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) @@ -87,6 +94,26 @@ static void stop_this_cpu(void) } } +#define PC87360_FDC 0x00 +#define PC87360_PP 0x01 +#define PC87360_SP2 0x02 +#define PC87360_SP1 0x03 +#define PC87360_SWC 0x04 +#define PC87360_KBCM 0x05 +#define PC87360_KBCK 0x06 +#define PC87360_GPIO 0x07 +#define PC87360_ACB 0x08 +#define PC87360_FSCM 0x09 +#define PC87360_WDT 0x0A + +/* FIXME: Do we really need this on Solo boards? */ +static void pc87360_enable_serial(void) +{ + pnp_set_logical_device(SIO_BASE, PC87360_SP1); + pnp_set_enable(SIO_BASE, 1); + pnp_set_iobase0(SIO_BASE, 0x3f8); +} + static void main(void) { /* @@ -111,11 +138,14 @@ static void main(void) enable_lapic(); init_timer(); + /* Solo boards only have 1 CPU, this check is not needed!? */ if (!boot_cpu()) { notify_bsp_ap_is_stopped(); stop_this_cpu(); } + pc87360_enable_serial(); + uart_init(); console_init(); setup_default_resource_map(); diff --git a/src/mainboard/amd/solo/chip.h b/src/mainboard/amd/solo/chip.h new file mode 100644 index 0000000000..e25cfac762 --- /dev/null +++ b/src/mainboard/amd/solo/chip.h @@ -0,0 +1,5 @@ +struct chip_control mainboard_amd_solo_control; + +struct mainboard_amd_solo_config { + int nothing; +}; diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c index 75a77d6adb..a4c45341ae 100644 --- a/src/mainboard/amd/solo/mainboard.c +++ b/src/mainboard/amd/solo/mainboard.c @@ -1,11 +1,42 @@ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <arch/io.h> +#include <device/chip.h> +#include "../../../northbridge/amd/amdk8/northbridge.h" +#include "chip.h" + unsigned long initial_apicid[CONFIG_MAX_CPUS] = { - 0 + 0, +}; + +static struct device_operations mainboard_operations = { + .read_resources = root_dev_read_resources, + .set_resources = root_dev_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = amdk8_scan_root_bus, + .enable = 0, +}; + +static void enumerate(struct chip *chip) +{ + struct chip *child; + dev_root.ops = &mainboard_operations; + chip->dev = &dev_root; + chip->bus = 0; + for(child = chip->children; child; child = child->next) { + child->bus = &dev_root.link[0]; + } +} +struct chip_control mainboard_amd_solo_control = { + .enumerate = enumerate, + .name = "AMD Solo7 mainboard ", }; + |