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-rw-r--r--src/southbridge/intel/fsp_rangeley/gpio.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 2a2061cb1a..0a287c4dc4 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -62,7 +62,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* GPIO PAD Settings */
/* CFIO Core Well Set 1 */
- if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
+ if ((gpio->core.cfio_init != NULL) && (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
@@ -76,7 +76,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
}
/* CFIO SUS Well Set 1 */
- if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
+ if ((gpio->sus.cfio_init != NULL) && (gpio->sus.cfio_entrynum != 0)) {
write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))