diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 20 |
3 files changed, 11 insertions, 18 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 25df4d15ce..b13d6861bd 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y + select BACKUP_DEFAULT_SMM_REGION select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 7c9beed6d8..dc6012bced 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -33,6 +33,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include <cpu/x86/smm.h> #include <delay.h> #include <pc80/mc146818rtc.h> #include <northbridge/intel/haswell/haswell.h> @@ -753,6 +754,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) int max_cpus; int num_aps; const void *microcode_patch; + void *smm_save_area; /* Perform any necessary BSP initialization before APs are brought up. * This call also allows the BSP to prepare for any secondary effects @@ -761,6 +763,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) microcode_patch = intel_microcode_find(); + /* Save default SMM area before relocation occurs. */ + smm_save_area = backup_default_smm_area(); + /* This needs to be called after the mtrr setup so the BSP mtrrs * can be mirrored by the APs. */ if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { @@ -782,6 +787,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); + /* Restore the default SMM region. */ + restore_default_smm_area(smm_save_area); + /* Enable ROM caching if option was selected. */ x86_mtrr_enable_rom_caching(); } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8d57c03b16..010cc07104 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -305,10 +305,7 @@ static void mc_add_dram_resources(device_t dev) /* * These are the host memory ranges that should be added: - * - 0 -> SMM_DEFAULT_BASE : cacheable - * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : - * cacheable and reserved - * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable + * - 0 -> 0xa0000: cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved @@ -338,21 +335,8 @@ static void mc_add_dram_resources(device_t dev) */ index = 0; - /* 0 - > SMM_DEFAULT_BASE */ + /* 0 - > 0xa0000 */ base_k = 0; - size_k = SMM_DEFAULT_BASE >> 10; - ram_resource(dev, index++, base_k, size_k); - - /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ - resource = new_resource(dev, index++); - resource->base = SMM_DEFAULT_BASE; - resource->size = SMM_DEFAULT_SIZE; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_CACHEABLE | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ - base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); |