diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 138 |
2 files changed, 65 insertions, 74 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 2637cf8482..6f6e153ca6 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -97,6 +97,7 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; + case PCH_DEVFN_GSPI3: return "SPI3"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f54ab4b448..9a35e73252 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -39,42 +39,62 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_DPTF 0x04 +#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) + +#define SA_DEV_SLOT_TBT 0x07 +#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) +#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) +#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) +#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) +#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) +#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) +#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) +#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) /* PCH Devices */ -#define PCH_DEV_SLOT_THERMAL 0x12 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) -#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) -#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) -#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) -#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) - -#define PCH_DEV_SLOT_ISH 0x13 +#define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) + +#define PCH_DEV_SLOT_SIO1 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) +#define PCH_DEV_UART3 _PCH_DEVFN(SIO1, 0) + +#define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) +#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) + +#define PCH_DEV_SLOT_SIO2 0x13 +#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_CNViWIFI _PCH_DEVFN(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) +#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) - -#define PCH_DEV_SLOT_SIO1 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) +#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) +#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) + +#define PCH_DEV_SLOT_SIO3 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) #define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) @@ -94,17 +114,13 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) -#define PCH_DEV_SLOT_SIO2 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) - -#define PCH_DEV_SLOT_STORAGE 0x1A -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#define PCH_DEV_SLOT_SIO4 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -129,46 +145,20 @@ #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) -#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) -#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) -#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) -#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) -#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) -#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) -#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) - -#define PCH_DEV_SLOT_PCIE_2 0x1b -#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) -#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) -#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) -#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) -#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) -#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) -#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) -#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) -#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) -#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) -#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) -#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) -#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) -#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) -#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) -#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) - -#define PCH_DEV_SLOT_SIO3 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) + +#define PCH_DEV_SLOT_SIO5 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) +#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) #define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI @@ -180,7 +170,7 @@ #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) #define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) -#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI #define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) |