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-rw-r--r--src/mainboard/intel/saddlebrook/Kconfig1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb120
-rw-r--r--src/mainboard/intel/saddlebrook/ramstage.c2
-rw-r--r--src/mainboard/intel/saddlebrook/romstage.c30
4 files changed, 69 insertions, 84 deletions
diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig
index 934c15affd..3fb694a800 100644
--- a/src/mainboard/intel/saddlebrook/Kconfig
+++ b/src/mainboard/intel/saddlebrook/Kconfig
@@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
select USE_INTEL_FSP_MP_INIT
+ select MAINBOARD_USES_FSP2_0
config IRQ_SLOT_COUNT
int
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 3322bf8e42..385a4be19f 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -61,82 +61,70 @@ chip soc/intel/skylake
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # VR Settings Configuration for 5 Domains
- #+----------------+-------+-------+-------------+-------------+-------+
- #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
- #+----------------+-------+-------+-------------+-------------+-------+
- #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
- #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
- #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
- #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
- #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 34A | 35A | 35A |
- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
- #+----------------+-------+-------+-------------+-------------+-------+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x10, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x1C, \
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0 \
- }"
- register "domain_vr_config[VR_RING]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0, \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C ,\
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C, \
- .voltage_limit = 0x5F0 \
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
}"
# Enable x1 slot
diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c
index 42477e6ef3..ed37681822 100644
--- a/src/mainboard/intel/saddlebrook/ramstage.c
+++ b/src/mainboard/intel/saddlebrook/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c
index 0ed6730b5c..8e280de638 100644
--- a/src/mainboard/intel/saddlebrook/romstage.c
+++ b/src/mainboard/intel/saddlebrook/romstage.c
@@ -24,10 +24,10 @@
#include <spd_bin.h>
-void mainboard_memory_init_params(
- struct romstage_params *params,
- MEMORY_INIT_UPD *memory_params)
+void mainboard_memory_init_params(FSPM_UPD *mupd)
{
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
struct spd_block blk = {
.addr_map = { 0x50, 0x52, },
};
@@ -36,26 +36,22 @@ void mainboard_memory_init_params(
dump_spd_info(&blk);
printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
- memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
- memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
- printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
- memory_params->MemorySpdPtr00);
- printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
- memory_params->MemorySpdPtr10);
+ mem_cfg->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", mem_cfg->MemorySpdPtr00);
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", mem_cfg->MemorySpdPtr10);
/*
* Configure the DQ/DQS settings if required. In general the settings
* should be set in the FSP flash image and should not need to be
* changed.
*/
- mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0,
- &memory_params->DqByteMapCh1);
- mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0,
- &memory_params->DqsMapCpu2DramCh1);
- mainboard_fill_rcomp_res_data(&memory_params->RcompResistor);
- mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget);
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
/* update spd length*/
- memory_params->MemorySpdDataLen = blk.len;
- memory_params->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->DqPinsInterleaved = TRUE;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 21:37:39 +0000