summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_206ax/chip.h2
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h1
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c26
3 files changed, 29 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
index 48e0c89c21..96b4c5d9a9 100644
--- a/src/cpu/intel/model_206ax/chip.h
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -34,4 +34,6 @@ struct cpu_intel_model_206ax_config {
int c1_acpower; /* ACPI C1 on AC Power */
int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */
+
+ int tcc_offset; /* TCC Activation Offset */
};
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index cdcc233ee6..a7ca04a690 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -34,6 +34,7 @@
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 70a655a6f0..2ad8012edf 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -37,6 +37,7 @@
#include <pc80/mc146818rtc.h>
#include <usbdebug.h>
#include "model_206ax.h"
+#include "chip.h"
/*
* List of suported C-states in this processor
@@ -312,6 +313,28 @@ static void configure_c_states(void)
wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
}
+static void configure_thermal_target(void)
+{
+ struct cpu_intel_model_206ax_config *conf;
+ device_t lapic;
+ msr_t msr;
+
+ /* Find pointer to CPU configuration */
+ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+ if (!lapic || !lapic->chip_info)
+ return;
+ conf = lapic->chip_info;
+
+ /* Set TCC activaiton offset if supported */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (conf->tcc_offset & 0xf) << 24;
+ wrmsr(MSR_TEMPERATURE_TARGET, msr);
+ }
+}
+
static void configure_misc(void)
{
msr_t msr;
@@ -454,6 +477,9 @@ static void model_206ax_init(device_t cpu)
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
+ /* Thermal throttle activation offset */
+ configure_thermal_target();
+
/* Enable Direct Cache Access */
configure_dca_cap();