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-rw-r--r--src/soc/intel/broadwell/include/soc/pch.h2
-rw-r--r--src/soc/intel/broadwell/include/soc/xhci.h2
-rw-r--r--src/soc/intel/broadwell/pch.c6
-rw-r--r--src/soc/intel/broadwell/xhci.c8
4 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h
index 690af9f985..19ba2e0b64 100644
--- a/src/soc/intel/broadwell/include/soc/pch.h
+++ b/src/soc/intel/broadwell/include/soc/pch.h
@@ -43,6 +43,6 @@ int pch_is_wpt(void);
int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id);
void pch_log_state(void);
-void pch_disable_devfn(device_t dev);
+void pch_disable_devfn(struct device *dev);
#endif
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index cf1b13526a..33e4c2dd06 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -51,7 +51,7 @@
#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
#ifdef __SMM__
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
#endif
#endif
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index a8b25cf650..c5df1adc08 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -77,7 +77,7 @@ u32 pch_read_soft_strap(int id)
#ifndef __PRE_RAM__
/* Put device in D3Hot Power State */
-static void pch_enable_d3hot(device_t dev)
+static void pch_enable_d3hot(struct device *dev)
{
u32 reg32 = pci_read_config32(dev, PCH_PCS);
reg32 |= PCH_PCS_PS_D3HOT;
@@ -92,7 +92,7 @@ static void rcba_function_disable(u32 reg, u32 bit)
}
/* Set bit in Function Disable register to hide this device */
-void pch_disable_devfn(device_t dev)
+void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCH_DEVFN_ADSP: /* Audio DSP */
@@ -183,7 +183,7 @@ void pch_disable_devfn(device_t dev)
}
}
-void broadwell_pch_enable_dev(device_t dev)
+void broadwell_pch_enable_dev(struct device *dev)
{
u32 reg32;
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 75a63cfca3..8b4c7b1b5e 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -25,7 +25,7 @@
#include <soc/cpu.h>
#ifdef __SMM__
-static u8 *usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(pci_devfn_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -36,7 +36,7 @@ static u8 *usb_xhci_mem_base(device_t dev)
return (u8 *)(mem_base & ~0xf);
}
-static int usb_xhci_port_count_usb3(device_t dev)
+static int usb_xhci_port_count_usb3(pci_devfn_t dev)
{
/* PCH-LP has 4 SS ports */
return 4;
@@ -69,7 +69,7 @@ static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(pci_devfn_t dev, int all)
{
u32 status, port_disabled;
int timeout, port;
@@ -140,7 +140,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
}
/* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;