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-rw-r--r--src/cpu/amd/mtrr/amd_earlymtrr.c6
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c15
-rw-r--r--src/mainboard/asus/m2v-mx_se/Kconfig1
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c11
-rw-r--r--src/mainboard/via/pc2500e/mptable.c1
-rw-r--r--src/northbridge/amd/amdk8/debug.c10
-rw-r--r--src/northbridge/amd/amdk8/raminit_f.c4
-rw-r--r--src/northbridge/amd/amdk8/raminit_f_dqs.c4
-rw-r--r--src/northbridge/via/cn700/cn700.h3
-rw-r--r--src/northbridge/via/cn700/northbridge.c4
-rw-r--r--src/northbridge/via/cn700/vga.c4
-rw-r--r--src/northbridge/via/cn700/vgabios.c29
-rw-r--r--src/southbridge/via/k8t890/k8t890.h4
-rw-r--r--src/southbridge/via/k8t890/k8t890_ctrl.c2
-rw-r--r--src/southbridge/via/k8t890/k8t890_early_car.c1
-rw-r--r--src/southbridge/via/vt8237r/vt8237_ctrl.c6
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.c6
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.h5
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_early_smbus.c5
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_ide.c6
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c3
21 files changed, 59 insertions, 71 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c
index 6ade525110..81b4a80a84 100644
--- a/src/cpu/amd/mtrr/amd_earlymtrr.c
+++ b/src/cpu/amd/mtrr/amd_earlymtrr.c
@@ -42,12 +42,6 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
wrmsr(TOP_MEM, msr);
#if defined(CONFIG_XIP_ROM_SIZE)
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-extern unsigned long AUTO_XIP_ROM_BASE;
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 150091e7a8..af9d56871a 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -26,6 +26,15 @@
# error "CONFIG_RAMTOP must be a power of 2"
#endif
+#if defined(CONFIG_XIP_ROM_SIZE)
+# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+ extern unsigned long AUTO_XIP_ROM_BASE;
+# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+# else
+# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+# endif
+#endif
+
static void disable_var_mtrr(unsigned reg)
{
/* The invalid bit is kept in the mask so we simply
@@ -100,12 +109,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
}
#if defined(CONFIG_XIP_ROM_SIZE)
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-extern unsigned long AUTO_XIP_ROM_BASE;
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
index 2aa7b5676f..a1f2ce6045 100644
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ b/src/mainboard/asus/m2v-mx_se/Kconfig
@@ -29,7 +29,6 @@ config BOARD_ASUS_M2V_MX_SE
select SUPERIO_ITE_IT8712F
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
- select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 5b542a2985..4183ce9b5a 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -116,12 +116,6 @@ static void ldtstop_sb(void)
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-#warning No hard_reset implemented for this board!
-void hard_reset(void)
-{
- print_info("NO HARD RESET. FIX ME!\n");
-}
-
void soft_reset(void)
{
uint8_t tmp;
@@ -164,7 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- msr_t msr;
static const uint16_t spd_addr[] = {
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
@@ -176,9 +169,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- char *p;
- u8 reg;
+ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
sio_init();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index e3f1fc15ea..7a0237f202 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -40,7 +40,6 @@ static void *smp_write_config_table(void *v)
struct mp_config_table *mc;
int bus_num;
- int i;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index ff2f347af1..97ca25577c 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -20,7 +20,7 @@ static void print_debug_pci_dev(unsigned dev)
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
}
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@@ -63,7 +63,7 @@ static void dump_pci_device(unsigned dev)
#if CONFIG_K8_REV_F_SUPPORT == 1
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
-static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
+static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
print_debug_pci_dev(dev);
@@ -109,7 +109,7 @@ static void dump_pci_devices(void)
}
}
-static void dump_pci_devices_on_bus(unsigned busn)
+static inline void dump_pci_devices_on_bus(unsigned busn)
{
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
@@ -208,7 +208,7 @@ static void dump_smbus_registers(void)
}
#endif
-static void dump_io_resources(unsigned port)
+static inline void dump_io_resources(unsigned port)
{
int i;
@@ -228,7 +228,7 @@ static void dump_io_resources(unsigned port)
}
}
-static void dump_mem(unsigned start, unsigned end)
+static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index c38d1595ae..e34187154c 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1690,7 +1690,7 @@ static unsigned convert_to_linear(unsigned value)
static const uint8_t latency_indicies[] = { 25, 23, 9 };
-int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
+static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time)
{
int new_cycle_time, new_latency;
int index;
@@ -1938,7 +1938,7 @@ static unsigned convert_to_1_4(unsigned value)
return valuex;
}
-int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
+static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
{
int value;
int value2;
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 4e402e6d7a..3372474ac5 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -125,7 +125,7 @@ static inline void write_cr4(unsigned long cr4)
}
-static inline void enable_sse2()
+static inline void enable_sse2(void)
{
unsigned long cr4;
cr4 = read_cr4();
@@ -133,7 +133,7 @@ static inline void enable_sse2()
write_cr4(cr4);
}
-static inline void disable_sse2()
+static inline void disable_sse2(void)
{
unsigned long cr4;
cr4 = read_cr4();
diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h
index df139cef35..8ffe44c8d9 100644
--- a/src/northbridge/via/cn700/cn700.h
+++ b/src/northbridge/via/cn700/cn700.h
@@ -19,7 +19,8 @@
*/
#if !defined (__PRE_RAM__)
-static void cn700_noop()
+// HACK
+static inline void cn700_noop(device_t dev)
{
}
#endif
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index ad8c42d841..445ecf2780 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -202,7 +202,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static const struct device_operations pci_domain_ops = {
+static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
@@ -219,7 +219,7 @@ static void cpu_bus_noop(device_t dev)
{
}
-static const struct device_operations cpu_bus_ops = {
+static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 283f23dd16..789dbfb480 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -52,7 +52,7 @@ static void vga_init(device_t dev)
* Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
* This is for compatibility with the VGA ROM's BIOS callbacks.
*/
- memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
+ memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
printk(BIOS_DEBUG, "Initializing VGA\n");
@@ -98,7 +98,7 @@ static void vga_init(device_t dev)
outb(reg8, SR_DATA);
/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
- memset(0xf0000, 0, 0x10000);
+ memset((void *)0xf0000, 0, 0x10000);
}
static const struct device_operations vga_operations = {
diff --git a/src/northbridge/via/cn700/vgabios.c b/src/northbridge/via/cn700/vgabios.c
index c9a6404f99..83ca814eeb 100644
--- a/src/northbridge/via/cn700/vgabios.c
+++ b/src/northbridge/via/cn700/vgabios.c
@@ -4,7 +4,7 @@
#include <device/pci_ops.h>
#undef __KERNEL__
#include <arch/io.h>
-//#include <printk.h>
+#include <stddef.h>
#include <string.h>
#include "vgachip.h"
#include <cbfs.h>
@@ -176,6 +176,7 @@ static void real_mode_switch_call_vga(unsigned long devfn)
/* put the stack at the end of page zero.
* that way we can easily share it between real and protected,
* since the 16-bit ESP at segment 0 will work for any case.
+ */
/* Setup a stack */
" mov $0x0, %ax \n"
" mov %ax, %ss \n"
@@ -271,6 +272,7 @@ void vga_enable_console()
/* put the stack at the end of page zero.
* that way we can easily share it between real and protected,
* since the 16-bit ESP at segment 0 will work for any case.
+ */
/* Setup a stack */
" mov $0x0, %ax \n"
" mov %ax, %ss \n"
@@ -336,7 +338,7 @@ void do_vgabios(void)
{
device_t dev;
unsigned long busdevfn;
- unsigned int rom = 0;
+ unsigned char *rom;
unsigned char *buf;
unsigned int size = 64*1024;
int i;
@@ -357,9 +359,9 @@ void do_vgabios(void)
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
- rom = cbfs_load_optionrom(dev->vendor, dev->device, 0);
- pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
- printk(BIOS_DEBUG, "rom base, size: %x\n", rom);
+ rom = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
+ pci_write_config32(dev, PCI_ROM_ADDRESS, (u32)rom | 1);
+ printk(BIOS_DEBUG, "rom base: %p\n", rom);
buf = (unsigned char *) rom;
if ((buf[0] == 0x55) && (buf[1] == 0xaa)) {
@@ -635,7 +637,7 @@ void setup_realmode_idt(void)
// and get it that way. But that's really disgusting.
for (i = 0; i < 256; i++) {
idts[i].cs = 0;
- codeptr = (char*) 4096 + i * codesize;
+ codeptr = (unsigned char*) 4096 + i * codesize;
idts[i].offset = (unsigned) codeptr;
memcpy(codeptr, &idthandle, codesize);
intbyte = codeptr + 3;
@@ -648,7 +650,7 @@ void setup_realmode_idt(void)
// int10.
// calling convention here is the same as INTs, we can reuse
// the int entry code.
- codeptr = (char*) 0xff065;
+ codeptr = (unsigned char*) 0xff065;
memcpy(codeptr, &idthandle, codesize);
intbyte = codeptr + 3;
*intbyte = 0x42; /* int42 is the relocated int10 */
@@ -657,7 +659,7 @@ void setup_realmode_idt(void)
TF bit is set upon call to real mode */
idts[1].cs = 0;
idts[1].offset = 16384;
- memcpy(16384, &debughandle, &end_debughandle - &debughandle);
+ memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle);
}
@@ -687,16 +689,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
{
- unsigned long edi = *pedi;
- unsigned long esi = *pesi;
- unsigned long ebp = *pebp;
- unsigned long esp = *pesp;
- unsigned long ebx = *pebx;
- unsigned long edx = *pedx;
- unsigned long ecx = *pecx;
- unsigned long eax = *peax;
- unsigned long flags = *pflags;
- unsigned short func = (unsigned short) eax;
+ unsigned short func = (unsigned short) (*peax);
int retval = 0;
unsigned short devid, vendorid, devfn;
short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index ba078f5e22..139daf91c2 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -40,8 +40,12 @@
#include <device/device.h>
+#if 0
extern void writeback(struct device *dev, u16 where, u8 what);
extern void dump_south(device_t dev);
+#endif
+#include <southbridge/via/vt8237r/vt8237r.h>
+
int k8m890_host_fb_size_get(void);
//void k8m890_host_fb_direct_set(uint32_t fb_address);
diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c
index ed11534945..ad17fe624d 100644
--- a/src/southbridge/via/k8t890/k8t890_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_ctrl.c
@@ -29,7 +29,7 @@
static void vt8237r_cfg(struct device *dev, struct device *devsb)
{
- u8 regm, regm2, regm3;
+ u8 regm, regm3;
device_t devfun3;
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index a0a269bb94..a7bb9102c4 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -59,6 +59,7 @@ u8 k8t890_early_setup_ht(void)
pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
/* check if connected non coherent, initcomplete (find the SB on K8 side) */
+ ldtnr = 0;
if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
ldtnr = 0;
} else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) {
diff --git a/src/southbridge/via/vt8237r/vt8237_ctrl.c b/src/southbridge/via/vt8237r/vt8237_ctrl.c
index 45af37624e..08c9c54754 100644
--- a/src/southbridge/via/vt8237r/vt8237_ctrl.c
+++ b/src/southbridge/via/vt8237r/vt8237_ctrl.c
@@ -22,12 +22,13 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
+#include "vt8237r.h"
/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */
static void vt8237_cfg(struct device *dev)
{
- u8 regm, regm2, regm3;
+ u8 regm, regm3;
device_t devfun3;
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
@@ -69,6 +70,7 @@ static void vt8237_cfg(struct device *dev)
regm = pci_read_config8(devfun3, 0x83);
pci_write_config8(dev, 0x63, regm);
+ // FIXME is this really supposed to be regm3?
regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */
pci_write_config8(dev, 0x64, regm);
@@ -167,8 +169,6 @@ static void ctrl_enable(struct device *dev)
pci_write_config8(dev, 0x4f, 0x43);
}
-extern void dump_south(device_t dev);
-
static void ctrl_init(struct device *dev)
{
/*
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 2b5d34bccc..be24bb5dc2 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -21,6 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "vt8237r.h"
#include "chip.h"
/*
@@ -28,11 +29,6 @@
* VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
*/
-void hard_reset(void)
-{
- printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n");
-}
-
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7
void writeback(struct device *dev, u16 where, u8 what)
{
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index 780876ce38..4e2484511e 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -103,4 +103,9 @@ __attribute__ ((packed))
#endif
;
+#ifndef __PRE_RAM__
+void writeback(struct device *dev, u16 where, u8 what);
+void dump_south(device_t dev);
+#endif
+
#endif
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index 533cbe0c88..4dd3678097 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -61,8 +61,9 @@ static void smbus_wait_until_ready(void)
PRINT_DEBUG("Waiting until SMBus ready\n");
- loops = 0;
/* Yes, this is a mess, but it's the easiest way to do it. */
+ /* XXX not so messy, but an explanation of the hack would have been better */
+ loops = 0;
while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
++loops;
@@ -464,6 +465,8 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom)
pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */
/* Yes, this is a mess, but it's the easiest way to do it. */
+ /* XXX not so messy, but an explanation of the hack would have been better */
+ loops = 0;
while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0)
&& (loops < LAN_TIMEOUT)) {
++loops;
diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c
index 0b4dccc2f0..ecbcfffc8c 100644
--- a/src/southbridge/via/vt8237r/vt8237r_ide.c
+++ b/src/southbridge/via/vt8237r/vt8237r_ide.c
@@ -35,10 +35,8 @@ static void ide_init(struct device *dev)
struct southbridge_via_vt8237r_config *sb =
(struct southbridge_via_vt8237r_config *)dev->chip_info;
- u8 enables, reg8;
+ u8 enables;
u32 cablesel;
- device_t lpc_dev;
- int i, j;
printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
sb->ide0_enable ? "enabled" : "disabled");
@@ -98,6 +96,8 @@ static void ide_init(struct device *dev)
pci_write_config32(dev, IDE_UDMA, cablesel);
#if CONFIG_EPIA_VT8237R_INIT
+ device_t lpc_dev;
+
/* Set PATA Output Drive Strength */
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 4e09823a69..f47c8c8dff 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -34,7 +34,6 @@
#include "vt8237r.h"
#include "chip.h"
-extern void dump_south(device_t dev);
static void southbridge_init_common(struct device *dev);
#if CONFIG_EPIA_VT8237R_INIT
@@ -248,7 +247,7 @@ static void setup_pm(device_t dev)
static void vt8237r_init(struct device *dev)
{
- u8 enables, reg8;
+ u8 enables;
#if CONFIG_EPIA_VT8237R_INIT
printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 03:48:46 +0000