diff options
Diffstat (limited to 'src')
20 files changed, 40 insertions, 40 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index d5f11dcc53..be8aa69264 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -34,7 +34,7 @@ /* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namesace. + * polluting the namespace. */ #define PM_MMIO_BASE 0xfed80300 diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 129a6151a9..836966e293 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -126,7 +126,7 @@ static void hudson_lpc_set_resources(struct device *dev) /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ static void hudson_lpc_enable_childrens_resources(device_t dev) diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index e762d0bb96..d1b661b103 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -65,7 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { - /* A GEVENT SMI occured */ + /* A GEVENT SMI occurred */ if (mainboard_smi_gpi) mainboard_smi_gpi(status & gevent_mask); } diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 35631bc7c1..9c7048271c 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -30,7 +30,7 @@ #include <device/pci_ehci.h> #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ -#include "Platform.h" /* Platfrom Specific Definitions */ +#include "Platform.h" /* Platform Specific Definitions */ #include "sb_cimx.h" #include "sb700_cfg.h" /* sb700 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 5d05762f55..75a3fb97da 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -89,7 +89,7 @@ void lpc_set_resources(struct device *dev) /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ void lpc_enable_childrens_resources(device_t dev) @@ -131,13 +131,13 @@ void lpc_enable_childrens_resources(device_t dev) case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c index a79695b9f5..c5f48beb5b 100644 --- a/src/southbridge/amd/cimx/sb700/smbus.c +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -201,7 +201,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) tmp |= val; /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); @@ -224,7 +224,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) tmp |= val; //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index b26d429bd3..59d89b019d 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -73,7 +73,7 @@ typedef union _PCI_ADDR { //------------------------------------------------------------------------------------------------------------------------// /** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable @@ -91,7 +91,7 @@ typedef union _PCI_ADDR { * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11) * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9f10dc5c7d..9ddcf8f314 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -71,7 +71,7 @@ unsigned long get_top_of_ram(void) /** * @brief South Bridge CIMx configuration * - * should be called before exeucte CIMx function. + * should be called before executing CIMx functions. * this function will be called in romstage and ramstage. */ void sb800_cimx_config(AMDSBCFG *sb_config) diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648edfb8..24dc8e0f02 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -58,7 +58,7 @@ void sb_Poweron_Init(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbPowerOnInit(&sb_early_cfg); } diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index bd3eb3f950..9442edccfb 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -125,7 +125,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->century = 0; /* 0x7f to make rtc alarm work */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 4f4ce150d6..eeefe24b4c 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -222,7 +222,7 @@ if (sb_chip->imc_fan_zone3_enabled) { } /* - * EC LDN9 funtion 89 - Set HWM TEMPIN Temperature Calculation Parameters + * EC LDN9 function 89 - Set HWM TEMPIN Temperature Calculation Parameters * This function provides the critical parameters of the HWM TempIn * sensors, IMC would not perform temperature measurement using those * sensors until the parameters are provided. @@ -232,7 +232,7 @@ if (sb_chip->imc_tempin0_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0; - /* EC LDN9 funtion 89 TEMPIN channel 0 */ + /* EC LDN9 function 89 TEMPIN channel 0 */ sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff); @@ -250,7 +250,7 @@ if (sb_chip->imc_tempin1_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1; - /* EC LDN9 funtion 89 TEMPIN channel 1 */ + /* EC LDN9 function 89 TEMPIN channel 1 */ sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01; sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff); @@ -268,7 +268,7 @@ if (sb_chip->imc_tempin2_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2; - /* EC LDN9 funtion 89 TEMPIN channel 2 */ + /* EC LDN9 function 89 TEMPIN channel 2 */ sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02; sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff); @@ -286,7 +286,7 @@ if (sb_chip->imc_tempin3_enabled) { sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3; - /* EC LDN9 funtion 89 TEMPIN channel 3 */ + /* EC LDN9 function 89 TEMPIN channel 3 */ sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03; sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff); diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cbb3797636..9c4047fd83 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -32,7 +32,7 @@ #include <arch/acpi.h> #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platfrom Specific Definitions */ +#include "SBPLATFORM.h" /* Platform Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 519e3c1175..ea2ebdca42 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -77,7 +77,7 @@ void lpc_set_resources(struct device *dev) /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ void lpc_enable_childrens_resources(device_t dev) @@ -119,13 +119,13 @@ void lpc_enable_childrens_resources(device_t dev) case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 277ff21cb1..bfe99c0776 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -205,7 +205,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) tmp |= val; /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); @@ -228,7 +228,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) tmp |= val; //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 6371bcd69e..67c33e8f85 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -70,7 +70,7 @@ typedef union _PCI_ADDR { //------------------------------------------------------------------------------------------------------------------------// /** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable @@ -88,7 +88,7 @@ typedef union _PCI_ADDR { * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11) * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index c596a372e3..5a8b2252bb 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -26,7 +26,7 @@ /** * @brief South Bridge CIMx configuration * - * should be called before exeucte CIMx function. + * should be called before execute CIMx function. * this function will be called in romstage and ramstage. */ void sb900_cimx_config(AMDSBCFG *sb_config) @@ -274,7 +274,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config) sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option - sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option + sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internal Option sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 6e4e44e169..b6b4ce1e17 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -74,7 +74,7 @@ void sb_poweron_init(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbPowerOnInit(&sb_early_cfg); printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); } @@ -93,7 +93,7 @@ void sb_before_pci_init(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbBeforePciInit(&sb_early_cfg); printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); } @@ -109,7 +109,7 @@ void sb_After_Pci_Init(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbAfterPciInit(&sb_early_cfg); printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); #endif @@ -125,7 +125,7 @@ void sb_Mid_Post_Init(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbMidPostInit(&sb_early_cfg); printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); } @@ -142,7 +142,7 @@ void sb_Late_Post(void) //AmdSbDispatcher(&sb_early_cfg); //TODO //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() take minitues to find the image. + // VerifyImage() will fail, LocateImage() take minutes to find the image. sbLatePost(&sb_early_cfg); //Set ACPI SCI IRQ to 0x9. diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 00e9a27c1c..6f6a5010bb 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -29,7 +29,7 @@ #include <device/pci_ehci.h> #include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ -#include "SbPlatform.h" /* Platfrom Specific Definitions */ +#include "SbPlatform.h" /* Platform Specific Definitions */ #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index ce1be11da7..e9b782fa95 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -74,7 +74,7 @@ void lpc_set_resources(struct device *dev) /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ void lpc_enable_childrens_resources(device_t dev) @@ -116,13 +116,13 @@ void lpc_enable_childrens_resources(device_t dev) case 0x2f8: /* COM2 */ reg |= (1 << 7); break; - case 0x378: /* Parallal 1 */ + case 0x378: /* Parallel 1 */ reg |= (1 << 0); break; case 0x3f0: /* FD0 */ reg |= (1 << 26); break; - case 0x220: /* Aduio 0 */ + case 0x220: /* Audio 0 */ reg |= (1 << 8); break; case 0x300: /* Midi 0 */ diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 1dbbe5abb1..01b6af983f 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -205,7 +205,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) tmp |= val; /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n"); @@ -228,7 +228,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) tmp |= val; //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n"); |