diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 26 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/cpu.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 1 |
3 files changed, 29 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 1fdaf69241..ccd1deaeff 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -166,6 +166,27 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +/* + * The emulated ACPI timer allows replacing of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TMR, msr); +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -188,6 +209,9 @@ void soc_core_init(struct device *cpu) /* Configure Intel Speed Shift */ configure_isst(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ + enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index dfc7183910..1e3e2b4cb1 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -37,6 +37,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 63b92013a3..09f0fce1a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -36,6 +36,7 @@ #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) |