diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/glados/devicetree.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2c6d99736f..40fe2b1d4f 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -20,17 +20,17 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" - register "PortUsb20Enable[0]" = "1" /* Type-C Port 1 */ - register "PortUsb20Enable[1]" = "1" /* Type-C Port 2 */ - register "PortUsb20Enable[2]" = "1" /* Bluetooth */ - register "PortUsb20Enable[4]" = "1" /* Type-A Port 1 */ - register "PortUsb20Enable[6]" = "1" /* Camera */ - register "PortUsb20Enable[8]" = "1" /* Type-A Port 2 */ + register "PortUsb20Enable[0]" = "1" # Type-C Port 1 + register "PortUsb20Enable[1]" = "1" # Type-C Port 2 + register "PortUsb20Enable[2]" = "1" # Bluetooth + register "PortUsb20Enable[4]" = "1" # Type-A Port 1 + register "PortUsb20Enable[6]" = "1" # Camera + register "PortUsb20Enable[8]" = "1" # Type-A Port 2 - register "PortUsb30Enable[0]" = "1" /* Type-C Port 1 */ - register "PortUsb30Enable[1]" = "1" /* Type-C Port 2 */ - register "PortUsb30Enable[2]" = "1" /* Type-A Port 1 */ - register "PortUsb30Enable[3]" = "1" /* Type-A Port 2 */ + register "PortUsb30Enable[0]" = "1" # Type-C Port 1 + register "PortUsb30Enable[1]" = "1" # Type-C Port 2 + register "PortUsb30Enable[2]" = "1" # Type-A Port 1 + register "PortUsb30Enable[3]" = "1" # Type-A Port 2 # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" |