diff options
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | 107 |
1 files changed, 68 insertions, 39 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index e81131db85..9bc1a409c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -269,7 +269,12 @@ typedef struct { /** Offset 0x015C - Reserved **/ - UINT8 Reserved4[40]; + UINT8 Reserved4[4]; + +/** Offset 0x0160 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; /** Offset 0x0184 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) @@ -277,9 +282,33 @@ typedef struct { **/ UINT8 VtdDisable; -/** Offset 0x0185 - Reserved +/** Offset 0x0185 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIgdEnable; + +/** Offset 0x0186 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x0187 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; + +/** Offset 0x0188 - Vtd Programming for ITbt + 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar + programming disabled) + $EN_DIS **/ - UINT8 Reserved5[4]; + UINT8 VtdItbtEnable; /** Offset 0x0189 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -297,7 +326,7 @@ typedef struct { /** Offset 0x018B - Reserved **/ - UINT8 Reserved6; + UINT8 Reserved5; /** Offset 0x018C - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile @@ -308,7 +337,7 @@ typedef struct { /** Offset 0x018D - Reserved **/ - UINT8 Reserved7[3]; + UINT8 Reserved6[3]; /** Offset 0x0190 - SA GV System Agent dynamic frequency support and when enabled memory will be training @@ -319,7 +348,7 @@ typedef struct { /** Offset 0x0191 - Reserved **/ - UINT8 Reserved8[2]; + UINT8 Reserved7[2]; /** Offset 0x0193 - Rank Margin Tool Enable/disable Rank Margin Tool. @@ -329,7 +358,7 @@ typedef struct { /** Offset 0x0194 - Reserved **/ - UINT8 Reserved9[10]; + UINT8 Reserved8[10]; /** Offset 0x019E - Memory Reference Clock 100MHz, 133MHz. @@ -339,7 +368,7 @@ typedef struct { /** Offset 0x019F - Reserved **/ - UINT8 Reserved10[22]; + UINT8 Reserved9[22]; /** Offset 0x01B5 - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller @@ -355,17 +384,17 @@ typedef struct { /** Offset 0x01B7 - Reserved **/ - UINT8 Reserved11[166]; + UINT8 Reserved10[166]; /** Offset 0x025D - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. $EN_DIS **/ - UINT8 ImguClkOutEn[5]; + UINT8 ImguClkOutEn[6]; -/** Offset 0x0262 - Reserved +/** Offset 0x0263 - Reserved **/ - UINT8 Reserved12[7]; + UINT8 Reserved11[6]; /** Offset 0x0269 - RpClockReqMsgEnable **/ @@ -377,7 +406,7 @@ typedef struct { /** Offset 0x026E - Reserved **/ - UINT8 Reserved13[3]; + UINT8 Reserved12[3]; /** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -477,7 +506,7 @@ typedef struct { /** Offset 0x0281 - Reserved **/ - UINT8 Reserved14[126]; + UINT8 Reserved13[126]; /** Offset 0x02FF - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane @@ -486,7 +515,7 @@ typedef struct { /** Offset 0x0307 - Reserved **/ - UINT8 Reserved15[22]; + UINT8 Reserved14[22]; /** Offset 0x031D - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM @@ -498,7 +527,7 @@ typedef struct { /** Offset 0x031E - Reserved **/ - UINT8 Reserved16[5]; + UINT8 Reserved15[5]; /** Offset 0x0323 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> @@ -508,7 +537,7 @@ typedef struct { /** Offset 0x0324 - Reserved **/ - UINT8 Reserved17; + UINT8 Reserved16; /** Offset 0x0325 - CPU ratio value CPU ratio value. Valid Range 0 to 63 @@ -517,7 +546,7 @@ typedef struct { /** Offset 0x0326 - Reserved **/ - UINT8 Reserved18[2]; + UINT8 Reserved17[2]; /** Offset 0x0328 - Processor Early Power On Configuration FCLK setting <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- @@ -528,7 +557,7 @@ typedef struct { /** Offset 0x0329 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x032A - Enable or Disable VMX Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. @@ -538,7 +567,7 @@ typedef struct { /** Offset 0x032B - Reserved **/ - UINT8 Reserved20[31]; + UINT8 Reserved19[31]; /** Offset 0x034A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -552,7 +581,7 @@ typedef struct { /** Offset 0x034C - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved20[4]; /** Offset 0x0350 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -566,7 +595,7 @@ typedef struct { /** Offset 0x0358 - Reserved **/ - UINT8 Reserved22[8]; + UINT8 Reserved21[8]; /** Offset 0x0360 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -580,7 +609,7 @@ typedef struct { /** Offset 0x0368 - Reserved **/ - UINT8 Reserved23[522]; + UINT8 Reserved22[522]; /** Offset 0x0572 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -589,7 +618,7 @@ typedef struct { /** Offset 0x0573 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved23[4]; /** Offset 0x0577 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -604,7 +633,7 @@ typedef struct { /** Offset 0x0597 - Reserved **/ - UINT8 Reserved25[5]; + UINT8 Reserved24[5]; /** Offset 0x059C - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -627,7 +656,7 @@ typedef struct { /** Offset 0x05A2 - Reserved **/ - UINT8 Reserved26[14]; + UINT8 Reserved25[14]; /** Offset 0x05B0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -637,7 +666,7 @@ typedef struct { /** Offset 0x05B1 - Reserved **/ - UINT8 Reserved27[4]; + UINT8 Reserved26[4]; /** Offset 0x05B5 - MRC Safe Config Enables/Disable MRC Safe Config @@ -683,7 +712,7 @@ typedef struct { /** Offset 0x05BC - Reserved **/ - UINT8 Reserved28[4]; + UINT8 Reserved27[4]; /** Offset 0x05C0 - Early Command Training Enables/Disable Early Command Training @@ -693,7 +722,7 @@ typedef struct { /** Offset 0x05C1 - Reserved **/ - UINT8 Reserved29[109]; + UINT8 Reserved28[109]; /** Offset 0x062E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -703,7 +732,7 @@ typedef struct { /** Offset 0x0630 - Reserved **/ - UINT8 Reserved30[62]; + UINT8 Reserved29[62]; /** Offset 0x066E - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -716,7 +745,7 @@ typedef struct { /** Offset 0x066F - Reserved **/ - UINT8 Reserved31[2]; + UINT8 Reserved30[2]; /** Offset 0x0671 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -726,7 +755,7 @@ typedef struct { /** Offset 0x0672 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved31[2]; /** Offset 0x0674 - TCSS USB Port Enable Bitmap for per port enabling @@ -735,7 +764,7 @@ typedef struct { /** Offset 0x0675 - Reserved **/ - UINT8 Reserved33[80]; + UINT8 Reserved32[80]; /** Offset 0x06C5 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -746,7 +775,7 @@ typedef struct { /** Offset 0x06C6 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x06C8 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -756,7 +785,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved35[122]; + UINT8 Reserved34[122]; /** Offset 0x0743 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -766,7 +795,7 @@ typedef struct { /** Offset 0x0744 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved35[3]; /** Offset 0x0747 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -775,7 +804,7 @@ typedef struct { /** Offset 0x0749 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -795,7 +824,7 @@ typedef struct { /** Offset 0x075D - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x0760 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -832,7 +861,7 @@ typedef struct { /** Offset 0x0775 - Reserved **/ - UINT8 Reserved39[355]; + UINT8 Reserved38[355]; } FSP_M_CONFIG; /** Fsp M UPD Configuration |