diff options
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | 11 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h | 36 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | 6 |
3 files changed, 38 insertions, 15 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index dded50d383..876c9d264c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -917,10 +917,9 @@ typedef struct { **/ UINT8 CoreVoltageMode; -/** Offset 0x0207 - Minimum clr turbo ratio override - Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83 +/** Offset 0x0207 **/ - UINT8 RingMinOcRatio; + UINT8 UnusedUpdSpace6; /** Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the @@ -1075,7 +1074,7 @@ typedef struct { /** Offset 0x0227 **/ - UINT8 UnusedUpdSpace6; + UINT8 UnusedUpdSpace7; /** Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 @@ -1853,7 +1852,7 @@ typedef struct { /** Offset 0x04C7 **/ - UINT8 UnusedUpdSpace7; + UINT8 UnusedUpdSpace8; /** Offset 0x04C8 - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (224= Def) @@ -2481,7 +2480,7 @@ typedef struct { /** Offset 0x0579 **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace9; /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 2a2412d8ff..17b9f92b4e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -975,46 +975,52 @@ typedef struct { PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>. **/ - UINT16 McivrRfiFrequencyAdjust; + UINT8 McivrRfiFrequencyAdjust; -/** Offset 0x0310 - FIVR RFI Frequency +/** Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0: Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; 0-1535 (Up to 153.5MHz) for 19MHz clock. **/ UINT16 FivrRfiFrequency; -/** Offset 0x0312 - McIVR RFI Spread Spectrum +/** Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%. **/ UINT8 McivrSpreadSpectrum; -/** Offset 0x0313 - FIVR RFI Spread Spectrum +/** Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>; Range: 0.0% to 10.0% (0-100). **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x0314 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain +/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True $EN_DIS **/ UINT8 FastPkgCRampDisableFivr; -/** Offset 0x0315 - Slew Rate configuration for Deep Package C States for VR FIVR domain +/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 **/ UINT8 SlowSlewRateForFivr; -/** Offset 0x0316 - CpuBistData +/** Offset 0x0315 - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; +/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues. + Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox + command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. +**/ + UINT8 IslVrCmd; + /** Offset 0x031A - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS @@ -2935,11 +2941,23 @@ typedef struct { **/ UINT8 CpuWakeUpTimer; -/** Offset 0x08A3 - ReservedCpuPostMemTest +/** Offset 0x08A3 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x08A4 - Minimum Ring ratio limit override + Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x08A5 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[23]; + UINT8 ReservedCpuPostMemTest[21]; /** Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 24f0883588..665e5a090a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -142,9 +142,15 @@ typedef struct { #ifndef MRC_DDR_TYPE_LPDDR3 #define MRC_DDR_TYPE_LPDDR3 2 #endif +#ifndef CPU_CFL//CNL +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#else//CFL #ifndef MRC_DDR_TYPE_UNKNOWN #define MRC_DDR_TYPE_UNKNOWN 3 #endif +#endif//CPU_CFL-endif #define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported |