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-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h4
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h11
2 files changed, 11 insertions, 4 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index f3aa4c85c6..5d9e0c235d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -539,7 +539,7 @@ typedef struct {
UINT8 PegDisableSpreadSpectrumClocking;
/** Offset 0x0235 - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[4];
@@ -554,7 +554,7 @@ typedef struct {
UINT8 DmiGen3EndPointHint[4];
/** Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
+ Range: 0-15, 3 is default for each bundle, must be specified based upon platform design
**/
UINT8 DmiGen3RxCtlePeaking[2];
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index f4f4badf47..0209245151 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -451,9 +451,16 @@ typedef struct {
**/
UINT8 AmtSolEnabled;
-/** Offset 0x015D
+/** Offset 0x015D - Configure CLKSRC Number
+ Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid
+ clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for
+ port1, byte1 for port2, and so on.
**/
- UINT8 UnusedUpdSpace6[163];
+ UINT8 PcieRpClkSrcNumber[24];
+
+/** Offset 0x0175
+**/
+ UINT8 UnusedUpdSpace6[139];
/** Offset 0x0200 - Subsystem Vendor ID for SA devices
Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086