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path: root/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
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Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
index 35cc43bcbb..909ba36708 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -1304,9 +1304,14 @@ typedef struct {
**/
UINT8 IsTPMPresence;
-/** Offset 0x0389 - Reserved
+/** Offset 0x0389 - ConfigTdpLevel
+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/
- UINT8 Reserved17[6];
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x038A - Reserved
+**/
+ UINT8 Reserved17[5];
/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.