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Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h | 637 |
1 files changed, 637 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h new file mode 100644 index 0000000000..cce959cb15 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -0,0 +1,637 @@ +/** @file + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Reserved +**/ + UINT8 Reserved0[8]; + +/** Offset 0x0048 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x004A - Reserved +**/ + UINT8 Reserved1[2]; + +/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr00; + +/** Offset 0x0050 - Reserved +**/ + UINT8 Reserved2[4]; + +/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x0058 - Reserved +**/ + UINT8 Reserved3[4]; + +/** Offset 0x005C - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0068 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x007C - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x0084 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x008A - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x0094 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x0095 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, + 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x0096 - Reserved +**/ + UINT8 Reserved4[6]; + +/** Offset 0x009C - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x00A0 - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x00A4 - Reserved +**/ + UINT8 Reserved5[6]; + +/** Offset 0x00AA - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x00AB - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[4]; + +/** Offset 0x00AF - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe. + 0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled + (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x00B0 - Reserved +**/ + UINT8 Reserved6[2]; + +/** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate + Enable ModPHY Pwoer Gate when DCI is enabled + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x00B3 - Reserved +**/ + UINT8 Reserved7; + +/** Offset 0x00B4 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x00B5 - Reserved +**/ + UINT8 Reserved8[47]; + +/** Offset 0x00E4 - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x00E5 - Reserved +**/ + UINT8 Reserved9[3]; + +/** Offset 0x00E8 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x00E9 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x00EA - Reserved +**/ + UINT8 Reserved10; + +/** Offset 0x00EB - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x00EC - Reserved +**/ + UINT8 Reserved11[2]; + +/** Offset 0x00EE - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x00EF - Reserved +**/ + UINT8 Reserved12[5]; + +/** Offset 0x00F4 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00F5 - Reserved +**/ + UINT8 Reserved13[24]; + +/** Offset 0x010D - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x010E - Reserved +**/ + UINT8 Reserved14[26]; + +/** Offset 0x0128 - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x0129 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x012A - Reserved +**/ + UINT8 Reserved15[98]; + +/** Offset 0x018C - Program GPIOs for LFP on DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x018D - Reserved +**/ + UINT8 Reserved16[2]; + +/** Offset 0x018F - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0190 - Enable or disable HPD of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0191 - Reserved +**/ + UINT8 Reserved17[5]; + +/** Offset 0x0196 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0197 - Enable or disable DDC of DDI port C + 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x0198 - Reserved +**/ + UINT8 Reserved18[165]; + +/** Offset 0x023D - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x023E - Reserved +**/ + UINT8 Reserved19[7]; + +/** Offset 0x0245 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x0246 - Reserved +**/ + UINT8 Reserved20[4]; + +/** Offset 0x024A - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x024B - Reserved +**/ + UINT8 Reserved21[31]; + +/** Offset 0x026A - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x026B - Reserved +**/ + UINT8 Reserved22[5]; + +/** Offset 0x0270 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x0274 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x0278 - Reserved +**/ + UINT8 Reserved23[543]; + +/** Offset 0x0497 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x04A7 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x04B7 - Reserved +**/ + UINT8 Reserved24[5]; + +/** Offset 0x04BC - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x04C0 - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x04C1 - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x04C2 - Reserved +**/ + UINT8 Reserved25[22]; + +/** Offset 0x04D8 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x04D9 - Reserved +**/ + UINT8 Reserved26[2]; + +/** Offset 0x04DB - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x04DC - Reserved +**/ + UINT8 Reserved27[7]; + +/** Offset 0x04E3 - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x04E4 - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x04E5 - Reserved +**/ + UINT8 Reserved28; + +/** Offset 0x04E6 - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x04E7 - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x04E8 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x04E9 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x04EA - Reserved +**/ + UINT8 Reserved29[3]; + +/** Offset 0x04ED - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x04EE - Reserved +**/ + UINT8 Reserved30[3]; + +/** Offset 0x04F1 - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x04F2 - Reserved +**/ + UINT8 Reserved31[6]; + +/** Offset 0x04F8 - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x04F9 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x04FA - Reserved +**/ + UINT8 Reserved32[60]; + +/** Offset 0x0536 - RAPL PL 1 WindowX + Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindX; + +/** Offset 0x0537 - RAPL PL 1 WindowY + Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindY; + +/** Offset 0x0538 - Reserved +**/ + UINT8 Reserved33[2]; + +/** Offset 0x053A - RAPL PL 1 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim1Pwr; + +/** Offset 0x053C - Reserved +**/ + UINT8 Reserved34[68]; + +/** Offset 0x0580 - LpDdrDqDqsReTraining + Enables/Disable LpDdrDqDqsReTraining + $EN_DIS +**/ + UINT8 LpDdrDqDqsReTraining; + +/** Offset 0x0581 - Reserved +**/ + UINT8 Reserved35[172]; + +/** Offset 0x062D - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHdaEnable; + +/** Offset 0x062E - Reserved +**/ + UINT8 Reserved36[3]; + +/** Offset 0x0631 - Enable HD Audio DMIC_N Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. +**/ + UINT8 PchHdaAudioLinkDmicEnable[2]; + +/** Offset 0x0633 - Reserved +**/ + UINT8 Reserved37[17]; + +/** Offset 0x0644 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0645 - Reserved +**/ + UINT8 Reserved38[11]; + +/** Offset 0x0650 - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 +**/ + UINT8 PchHdaAudioLinkSspEnable[6]; + +/** Offset 0x0656 - Enable HD Audio SoundWire#N Link + Enable/disable HD Audio SNDW#N link. Muxed with HDA. +**/ + UINT8 PchHdaAudioLinkSndwEnable[4]; + +/** Offset 0x065A - Reserved +**/ + UINT8 Reserved39[7]; + +/** Offset 0x0661 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x0662 - Reserved +**/ + UINT8 Reserved40[22]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0678 +**/ + UINT8 UnusedUpdSpace19[6]; + +/** Offset 0x067E +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif |