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path: root/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
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Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h23
1 files changed, 13 insertions, 10 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 14e235f320..8dcac42bd3 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -155,6 +155,7 @@ typedef struct {
uint8_t PcieSegment;
UINT64_STRUCT SegMmcfgBase;
uint16_t stackPresentBitmap;
+ uint16_t CxlPresentBitmap;
uint16_t M2PciePresentBitmap;
uint8_t TotM3Kti;
uint8_t TotCha;
@@ -199,20 +200,23 @@ typedef struct _STACK_RES {
uint8_t Personality; // see STACK_TYPE for details
uint8_t BusBase;
uint8_t BusLimit;
- uint16_t PciResourceIoBase;
- uint16_t PciResourceIoLimit;
- uint32_t IoApicBase;
- uint32_t IoApicLimit;
+ uint16_t IoBase; // Base of IO configured for this stack
+ uint16_t IoLimit; // Limit of IO configured for this stack
+ uint32_t IoApicBase; // Base of IO configured for this stack
+ uint32_t IoApicLimit; // Limit of IO configured for this stack
uint32_t Mmio32Base;
uint32_t Mmio32Limit;
uint64_t Mmio64Base;
uint64_t Mmio64Limit;
+ uint8_t PciResourceBusBase; // Base of Bus resource available for PCI devices
+ uint8_t PciResourceBusLimit; // Limit of Bus resource available for PCI devices
+ uint16_t PciResourceIoBase; // Base of IO resource available for PCI devices
+ uint16_t PciResourceIoLimit; // Limit of IO resource available for PCI devices
uint32_t PciResourceMem32Base;
uint32_t PciResourceMem32Limit;
uint64_t PciResourceMem64Base;
uint64_t PciResourceMem64Limit;
uint32_t VtdBarAddress;
- uint32_t Slt2HfiBarAddress; // KNH Only
} STACK_RES;
typedef struct {
@@ -224,10 +228,10 @@ typedef struct {
uint16_t PciResourceIoLimit;
uint32_t IoApicBase;
uint32_t IoApicLimit;
- uint32_t PciResourceMem32Base;
- uint32_t PciResourceMem32Limit;
- uint64_t PciResourceMem64Base;
- uint64_t PciResourceMem64Limit;
+ uint32_t Mmio32Base;
+ uint32_t Mmio32Limit;
+ uint64_t Mmio64Base;
+ uint64_t Mmio64Limit;
STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
uint32_t RcBaseAddress;
IIO_DMI_PCIE_INFO PcieInfo;
@@ -275,7 +279,6 @@ typedef struct {
uint8_t DmiVc1;
uint8_t DmiVcm;
uint32_t CpuPCPSInfo;
- uint8_t MctpEn;
uint8_t cpuSubType;
uint8_t SystemRasType;
uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC