diff options
Diffstat (limited to 'src/vendorcode/google/chromeos')
| -rw-r--r-- | src/vendorcode/google/chromeos/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/acpi.c | 43 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/acpi/chromeos.asl | 6 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/chromeos.h | 72 |
4 files changed, 122 insertions, 0 deletions
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index dffbcd5b23..c94d6abd7d 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += chromeos.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c new file mode 100644 index 0000000000..6605809023 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include "chromeos.h" + +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) +{ + size_t i; + + acpigen_write_scope("\\"); + acpigen_write_name("OIPG"); + + acpigen_write_package(num); + for (i = 0; i < num; i++) { + acpigen_write_package(4); + acpigen_write_integer(gpios[i].type); + acpigen_write_integer(gpios[i].polarity); + acpigen_write_integer(gpios[i].gpio_num); + acpigen_write_string(gpios[i].device); + acpigen_pop_len(); + } + acpigen_pop_len(); + + acpigen_pop_len(); +} + +void chromeos_dsdt_generator(struct device *dev) +{ + mainboard_chromeos_acpi_generate(); +} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 7d62f4a728..44d9d155e3 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -15,6 +15,11 @@ #include <vboot/vbnv_layout.h> +#if IS_ENABLED(CONFIG_CHROMEOS) + +/* GPIO package generated at run time. */ +External (OIPG) + Device (CRHW) { Name(_HID, EISAID("GGL0001")) @@ -107,3 +112,4 @@ Device (CRHW) } #include "ramoops.asl" +#endif diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0a93ccd307..fd845bfae1 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -19,6 +19,7 @@ #include <stddef.h> #include <stdint.h> #include <bootmode.h> +#include <device/device.h> #include <rules.h> #include <vboot/misc.h> #include <vboot/vboot_common.h> @@ -53,4 +54,75 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} void cbmem_add_vpd_calibration_data(void); +/* + * Create the OIPG package containing the Chrome OS gpios described by + * the chromeos_gpio array. + */ +struct cros_gpio; +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); + +/* + * Common helper function and delcarations for mainboards to use to generate + * ACPI-specific Chrome OS needs. + */ +void mainboard_chromeos_acpi_generate(void); +#if IS_ENABLED(CONFIG_CHROMEOS) +void chromeos_dsdt_generator(struct device *dev); +#else +#define chromeos_dsdt_generator DEVICE_NOOP +#endif + +enum { + CROS_GPIO_REC = 1, /* Recovery */ + CROS_GPIO_DEV = 2, /* Developer */ + CROS_GPIO_WP = 3, /* Write Protect */ + + CROS_GPIO_ACTIVE_LOW = 0, + CROS_GPIO_ACTIVE_HIGH = 1, + + CROS_GPIO_VIRTUAL = -1, +}; + +struct cros_gpio { + int type; + int polarity; + int gpio_num; + const char *device; +}; + +#define CROS_GPIO_INITIALIZER(typ, pol, num, dev) \ + { \ + .type = (typ), \ + .polarity = (pol), \ + .gpio_num = (num), \ + .device = (dev), \ + } + +#define CROS_GPIO_REC_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_REC, pol, num, dev) + +#define CROS_GPIO_REC_AL(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_REC_AH(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_DEV_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_DEV, pol, num, dev) + +#define CROS_GPIO_DEV_AL(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_DEV_AH(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev) + +#define CROS_GPIO_WP_AL(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_WP_AH(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + #endif /* __CHROMEOS_H__ */ |