diff options
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/OEM.h | 8 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBPOR.c | 11 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBTYPE.h | 5 |
3 files changed, 23 insertions, 1 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h index 9abea30dbb..b38acba524 100644 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ b/src/vendorcode/amd/cimx/sb800/OEM.h @@ -87,6 +87,14 @@ #endif /** + * SIO_HWM_BASE_ADDRESS - Super IO HWM base address + * + */ +#ifndef SIO_HWM_BASE_ADDRESS + #define SIO_HWM_BASE_ADDRESS 0x290 +#endif + +/** * SPI_BASE_ADDRESS - SPI controller (ROM) base address * */ diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index 33d09d622e..daf13c719c 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -144,6 +144,7 @@ sbPowerOnInit ( UINT8 cimSataMode; UINT8 cimSpiFastReadEnable; UINT8 cimSpiFastReadSpeed; + UINT8 cimSioHwmPortEnable; UINT8 SataPortNum; cimNbSbGen2 = pConfig->NbSbGen2; @@ -155,12 +156,14 @@ sbPowerOnInit ( cimSpiFastReadEnable = cimSpiFastReadEnableDefault; } cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; + cimSioHwmPortEnable = pConfig->SioHwmPortEnable; #if SB_CIMx_PARAMETER == 0 cimNbSbGen2 = cimNbSbGen2Default; cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); cimSpiFastReadEnable = cimSpiFastReadEnableDefault; cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; + cimSioHwmPortEnable = cimSioHwmPortEnableDefault; #endif // SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct @@ -200,6 +203,12 @@ sbPowerOnInit ( // Set Build option into SB WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + if (cimSioHwmPortEnable) { + // Use Wide IO Port 1 to provide access to the superio HWM registers. + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes + } RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); // Enabled SMBUS0/SMBUS1 (ASF) Base Address @@ -354,4 +363,4 @@ sbPowerOnInit ( // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); -}
\ No newline at end of file +} diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index ea3e6f6c42..b8278cf5ec 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -156,6 +156,10 @@ typedef struct _BUILDPARAM { * @par * SIO PME BASE Address */ + unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress + * @par + * SIO HWM BASE Address + */ unsigned int WatchDogTimerBase; /**< WatchDogTimerBase * @par * Watch Dog Timer Address @@ -911,6 +915,7 @@ typedef struct _AMDSBCFG { unsigned int MTC1e:1; //29 /** MiscDummy - Reserved */ unsigned int MiscDummy:2; //31:30 + unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC //DebugOptions //offset 4 bytes (146-149) /** PcibAutoClkCtrlLow - Debug function Reserved */ |