diff options
Diffstat (limited to 'src/vendorcode/amd')
| -rwxr-xr-x | src/vendorcode/amd/agesa/f10/gcccar.inc | 2 | ||||
| -rwxr-xr-x | src/vendorcode/amd/agesa/f12/gcccar.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/gcccar.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/gcccar.inc | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index a24c0b7abe..70988b89b8 100755 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -989,7 +989,7 @@ fam15_enable_stack_hook_exit: mov $CU_CFG3, %ecx # MSR:C001_102B _RDMSR - bts $(COMBINE_CR0_CD - 32), %eax # Set CombineCr0Cd bit + bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit _WRMSR fam15_disable_stack_hook_exit: diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 63f3ea9d12..e7f2ec7bd7 100755 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -983,7 +983,7 @@ fam15_enable_stack_hook_exit: mov $CU_CFG3, %ecx # MSR:C001_102B _RDMSR - bts $(COMBINE_CR0_CD - 32), %eax # Set CombineCr0Cd bit + bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit _WRMSR fam15_disable_stack_hook_exit: diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index d81b6afe70..fc1b1adaa4 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -997,7 +997,7 @@ fam15_enable_stack_hook_exit: mov $CU_CFG3, %ecx # MSR:C001_102B _RDMSR - bts $(COMBINE_CR0_CD - 32), %eax # Set CombineCr0Cd bit + bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit _WRMSR fam15_disable_stack_hook_exit: diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 423d404469..3627da6df3 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1004,7 +1004,7 @@ fam15_enable_stack_hook_exit: mov $CU_CFG3, %ecx # MSR:C001_102B _RDMSR - bts $(COMBINE_CR0_CD - 32), %eax # Set CombineCr0Cd bit + bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit _WRMSR fam15_disable_stack_hook_exit: |