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-rw-r--r--src/vendorcode/amd/fsp/phoenix/platform_descriptors.h49
1 files changed, 45 insertions, 4 deletions
diff --git a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
index cd6b835162..a6133c1d17 100644
--- a/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
@@ -88,29 +88,70 @@ enum dxio_port_param_type {
PP_CLOCK_PM,
PP_CHANNELTYPE,
PP_TURN_OFF_UNUSED_LANES,
- PP_APIC_GROUPMAP,
- PP_APIC_SWIZZLE,
- PP_APIC_BRIDGEINT,
PP_MASTER_PLL,
PP_SLOT_NUM,
PP_PHY_PARAM,
PP_ESM,
PP_CCIX,
+ PP_CXL,
PP_GEN3_DS_TX_PRESET,
PP_GEN3_DS_RX_PRESET_HINT,
PP_GEN3_US_TX_PRESET,
PP_GEN3_US_RX_PRESET_HINT,
PP_GEN4_DS_TX_PRESET,
PP_GEN4_US_TX_PRESET,
+ PP_GEN5_DS_TX_PRESET,
+ PP_GEN5_US_TX_PRESET,
PP_GEN3_FIXED_PRESET,
PP_GEN4_FIXED_PRESET,
+ PP_GEN5_FIXED_PRESET,
+ PP_GEN3_PRESET_MASK,
+ PP_GEN4_PRESET_MASK,
+ PP_GEN5_PRESET_MASK,
PP_PSPP_DC,
PP_PSPP_AC,
PP_GEN2_DEEMPHASIS,
PP_INVERT_POLARITY,
PP_TARGET_LINK_SPEED,
PP_GEN4_DLF_CAP_DISABLE,
- PP_GEN4_DLF_EXCHG_DISABLE
+ PP_GEN4_DLF_EXCHG_DISABLE,
+ PP_I2C_EXPANDER_ADDRESS,
+ PP_I2C_EXPANDER_TYPE,
+ PP_I2C_CLEAR_ALL_INTS,
+ PP_UBM_SWITCH0_ADDR,
+ PP_UBM_SWITCH0_SELECT,
+ PP_UBM_SWITCH0_TYPE,
+ PP_UBM_SWITCH1_ADDR,
+ PP_UBM_SWITCH1_SELECT,
+ PP_UBM_SWITCH1_TYPE,
+ PP_UBM_HFC_INDEX,
+ PP_UBM_DFC_INDEX,
+ PP_DFC_EVENT,
+ PP_GPIOx_I2C_RESET,
+ PP_GPIOx_BP_TYPE,
+ PP_START_LANE,
+ PP_OCP_PRESENT_START,
+ PP_OCP_DEF_VALID,
+ PP_OCP_DEF_PRSNTB_PRIMARY,
+ PP_OCP_DEF_PRSNTB_SECONDARY,
+ PP_OCP_BIF_PRIMARY,
+ PP_OCP_BIF_SECONDARY,
+ PP_OCP_NUM_HOSTS,
+ PP_OCP_NUM_SOCKETS,
+ PP_OCP_FORM_FACTOR,
+ PP_ALWAYS_EXPOSE,
+ PP_SRIS_ENABLED,
+ PP_SRIS_SKIP_INTERVAL,
+ PP_SRIS_LOWER_OS_GEN_SUP,
+ PP_SRIS_LOWER_OS_RCV_SUP,
+ PP_SRIS_AUTODETECT_MODE,
+ PP_SRIS_SKP_INTERVAL_SEL,
+ PP_SRIS_AUTODETECT_FACTOR,
+ PP_LEGACY_SWITCH0_ADDR,
+ PP_LEGACY_SWITCH0_SELECT,
+ PP_NPEM_ENABLE,
+ PP_NPEM_CAPABILITES,
+ PP_BMC_LOCATION,
};
/* DDI Aux channel */