diff options
Diffstat (limited to 'src/vendorcode/amd/fsp')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index e51cbef143..66c8ab81b4 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -51,21 +51,21 @@ typedef struct __packed { /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; /** Offset 0x03EA**/ uint16_t stt_error_coeff; /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; - /** Offset 0x03EE**/ uint8_t stapm_control; - /** Offset 0x03EF**/ uint8_t stapm_boost; - /** Offset 0x03F0**/ uint8_t smartshift_enable; - /** Offset 0x03F1**/ uint32_t apu_only_sppt_limit; - /** Offset 0x03F5**/ uint32_t sustained_power_limit; - /** Offset 0x03F9**/ uint32_t fast_ppt_limit; - /** Offset 0x03FD**/ uint32_t slow_ppt_limit; - /** Offset 0x0401**/ uint8_t system_configuration; - /** Offset 0x0402**/ uint8_t cppc_ctrl; - /** Offset 0x0403**/ uint8_t cppc_perf_limit_max_range; - /** Offset 0x0404**/ uint8_t cppc_perf_limit_min_range; - /** Offset 0x0405**/ uint8_t cppc_epp_max_range; - /** Offset 0x0406**/ uint8_t cppc_epp_min_range; - /** Offset 0x0407**/ uint8_t cppc_preferred_cores; - /** Offset 0x0408**/ uint8_t smu_soc_tuning_reserved[20]; + /** Offset 0x03EE**/ uint8_t smartshift_enable; + /** Offset 0x03EF**/ uint32_t apu_only_sppt_limit; + /** Offset 0x03F3**/ uint32_t sustained_power_limit; + /** Offset 0x03F7**/ uint32_t fast_ppt_limit; + /** Offset 0x03FB**/ uint32_t slow_ppt_limit; + /** Offset 0x03FF**/ uint8_t system_configuration; + /** Offset 0x0400**/ uint8_t cppc_ctrl; + /** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range; + /** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range; + /** Offset 0x0403**/ uint8_t cppc_epp_max_range; + /** Offset 0x0404**/ uint8_t cppc_epp_min_range; + /** Offset 0x0405**/ uint8_t cppc_preferred_cores; + /** Offset 0x0406**/ uint8_t stapm_boost; + /** Offset 0x0407**/ uint32_t stapm_time_constant; + /** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17]; /** Offset 0x041C**/ uint8_t iommu_support; /** Offset 0x041D**/ uint8_t pspp_policy; /** Offset 0x041E**/ uint8_t enable_nb_azalia; |