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-rw-r--r--src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h2
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c12
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h2
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h2
5 files changed, 11 insertions, 9 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
index 0ff75856f6..1944b32168 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
- IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
+ IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
index d11ee6d56a..444ef2cf99 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c
@@ -248,9 +248,10 @@ PStateGatherMain (
//Calculate next node buffer address
//
PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
- PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
- PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+ MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
+ PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
+ PStateStrucPtr->SizeOfBytes += (MaxState + 1) * sizeof (S_PSTATE_VALUES);
+ PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
//
//Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
@@ -266,9 +267,10 @@ PStateGatherMain (
//
//Calculate next node buffer address
//
- PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+ MaxState = PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue;
+ PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (MaxState + 1) * sizeof (S_PSTATE_VALUES));
PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
- PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+ PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + PStateBufferPtr->PStateLevelingSizeOfBytes);
}
}
}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
index 81af4912cb..59b02d5980 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.h
@@ -79,7 +79,7 @@ typedef struct {
IN OUT UINT8 HtcPstateLimit; ///< Htc limit
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
- IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
+ IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
index b75ea3e250..95768d2563 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
- IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
+ IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
index 9ccacb4491..a01845e57f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h
@@ -78,7 +78,7 @@ typedef struct {
IN OUT UINT8 HtcCapable; ///< Htc capable
IN OUT UINT8 LocalApicId; ///< Local Apic Id
IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states
- IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
+ IN OUT S_PSTATE_VALUES PStateStruct[]; ///< P state struc
} S_PSTATE;
/// P-state structure for each node