diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc')
15 files changed, 69 insertions, 68 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c index ab06fe196f..176fd73069 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c @@ -97,7 +97,7 @@ AMD_WHEA_INIT_DATA F16WheaInitData = { 0x00, // AmdMcbClrStatusOnInit 0x02, // AmdMcbStatusDataFormat 0x00, // AmdMcbConfWriteEn - (sizeof (F16HestBankInitData) / sizeof (F16HestBankInitData[0])), // HestBankNum + ARRAY_SIZE(F16HestBankInitData), // HestBankNum &F16HestBankInitData[0] // Pointer to Initial data of HEST Bank }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c index 57ca222710..9f90a1376c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c @@ -183,7 +183,8 @@ ProgramFchEnvHwAcpiPciReg ( // //Early post initialization of pci config space // - ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]), sizeof (FchYangtzeInitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchYangtzeInitEnvHwAcpiPciTable[0]), + ARRAY_SIZE(FchYangtzeInitEnvHwAcpiPciTable), StdHeader); if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c index db46136bc0..d012d06e13 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c @@ -86,7 +86,7 @@ STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = { { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13}, }; -#define NUM_OF_DEVICE_FOR_APICIRQ sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK) +#define NUM_OF_DEVICE_FOR_APICIRQ ARRAY_SIZE(FchInternalDeviceIrqForApicMode) /** * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS. diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c index 0ae09932cf..7cf6a818d7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c @@ -202,7 +202,7 @@ FchProgramSataPhy ( PhyTablePtr = &SataPhyTable[0]; - for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) { RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); ++PhyTablePtr; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c index e2f37bbc25..289acd2b00 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c @@ -82,7 +82,8 @@ FchInitEnvLpcProgram ( LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; - ProgramPciByteTable ((REG8_MASK*) (&FchInitYangtzeEnvLpcPciTable[0]), sizeof (FchInitYangtzeEnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ((REG8_MASK*) (&FchInitYangtzeEnvLpcPciTable[0]), + ARRAY_SIZE(FchInitYangtzeEnvLpcPciTable), StdHeader); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 0); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c index ab71bb9d49..6411e04e38 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c @@ -125,7 +125,8 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), sizeof (FchInitYangtzeResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); + ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), + ARRAY_SIZE(FchInitYangtzeResetLpcPciTable), StdHeader); if ( LocalCfgPtr->Spi.LpcClk0 ) { RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0 + 1, AccessWidth8, 0xDF, 0x20, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 23501227eb..3d3a097e63 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -253,7 +253,7 @@ GfxIntegratedExtConnectorInfo ( ) { UINTN Index; - for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) { if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { return &ConnectorInfoTable[Index]; } @@ -331,7 +331,7 @@ GfxIntegratedExtDisplayDeviceInfo ( UINT8 Index; UINT8 LastIndex; LastIndex = 0xff; - for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) { if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { LastIndex = Index; if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c index 4e83c44359..3cc3fad253 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c @@ -889,13 +889,11 @@ GfxPwrPlayBuildVceStateTable ( UsedStateBitmap = 0; // build used state for (Index = 0; - Index < (sizeof (PpWorkspace->PpF1s->VceFlags) / - sizeof (PpWorkspace->PpF1s->VceFlags[0])) ; + Index < ARRAY_SIZE(PpWorkspace->PpF1s->VceFlags); Index++) { UsedStateBitmap |= PpWorkspace->PpF1s->VceFlags[Index]; for (VceStateIndex = 0; - VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / - sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((PpWorkspace->PpF1s->VceFlags[Index] & (1 << VceStateIndex)) != 0) { v4 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld33[PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld16[Index]], @@ -919,7 +917,7 @@ GfxPwrPlayBuildVceStateTable ( } //build unused states for (VceStateIndex = 0; - VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) { if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c index 41b7b176f2..e0dae34ea4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c @@ -708,157 +708,157 @@ F1_TABLE_ENTRY_KB F1RegisterTableKB [] = { { 0x4, 0xC0104007, - sizeof (D0F0xBC_xC0104007_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104007_TABLE), D0F0xBC_xC0104007_TABLE }, { 0x4, 0xC0104008, - sizeof (D0F0xBC_xC0104008_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104008_TABLE), D0F0xBC_xC0104008_TABLE }, { 0x4, 0xC010400c, - sizeof (D0F0xBC_xC010400C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010400C_TABLE), D0F0xBC_xC010400C_TABLE }, { 0x4, 0xC010407c, - sizeof (D0F0xBC_xC010407C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010407C_TABLE), D0F0xBC_xC010407C_TABLE }, { 0x4, 0xC0104080, - sizeof (D0F0xBC_xC0104080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104080_TABLE), D0F0xBC_xC0104080_TABLE }, { 0x4, 0xC0104083, - sizeof (D0F0xBC_xC0104083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104083_TABLE), D0F0xBC_xC0104083_TABLE }, { 0x4, 0xC0104084, - sizeof (D0F0xBC_xC0104084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104084_TABLE), D0F0xBC_xC0104084_TABLE }, { 0x4, 0xC0104088, - sizeof (D0F0xBC_xC0104088_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0104088_TABLE), D0F0xBC_xC0104088_TABLE }, { 0x4, 0xC01040a8, - sizeof (D0F0xBC_xC01040A8_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC01040A8_TABLE), D0F0xBC_xC01040A8_TABLE }, { 0x4, 0xC01040ac, - sizeof (D0F0xBC_xC01040AC_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC01040AC_TABLE), D0F0xBC_xC01040AC_TABLE }, { 0x4, 0xC0107044, - sizeof (D0F0xBC_xC0107044_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107044_TABLE), D0F0xBC_xC0107044_TABLE }, { 0x4, 0xC0107064, - sizeof (D0F0xBC_xC0107064_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107064_TABLE), D0F0xBC_xC0107064_TABLE }, { 0x4, 0xC0107067, - sizeof (D0F0xBC_xC0107067_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107067_TABLE), D0F0xBC_xC0107067_TABLE }, { 0x4, 0xC0107068, - sizeof (D0F0xBC_xC0107068_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107068_TABLE), D0F0xBC_xC0107068_TABLE }, { 0x4, 0xC010706b, - sizeof (D0F0xBC_xC010706B_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706B_TABLE), D0F0xBC_xC010706B_TABLE }, { 0x4, 0xC010706c, - sizeof (D0F0xBC_xC010706C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706C_TABLE), D0F0xBC_xC010706C_TABLE }, { 0x4, 0xC010706f, - sizeof (D0F0xBC_xC010706F_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010706F_TABLE), D0F0xBC_xC010706F_TABLE }, { 0x4, 0xC0107070, - sizeof (D0F0xBC_xC0107070_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107070_TABLE), D0F0xBC_xC0107070_TABLE }, { 0x4, 0xC0107073, - sizeof (D0F0xBC_xC0107073_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107073_TABLE), D0F0xBC_xC0107073_TABLE }, { 0x4, 0xC0107074, - sizeof (D0F0xBC_xC0107074_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107074_TABLE), D0F0xBC_xC0107074_TABLE }, { 0x4, 0xC0107077, - sizeof (D0F0xBC_xC0107077_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107077_TABLE), D0F0xBC_xC0107077_TABLE }, { 0x4, 0xC0107078, - sizeof (D0F0xBC_xC0107078_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107078_TABLE), D0F0xBC_xC0107078_TABLE }, { 0x4, 0xC010707c, - sizeof (D0F0xBC_xC010707C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC010707C_TABLE), D0F0xBC_xC010707C_TABLE }, { 0x4, 0xC0107080, - sizeof (D0F0xBC_xC0107080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107080_TABLE), D0F0xBC_xC0107080_TABLE }, { 0x4, 0xC0107083, - sizeof (D0F0xBC_xC0107083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107083_TABLE), D0F0xBC_xC0107083_TABLE }, { 0x4, 0xC0107084, - sizeof (D0F0xBC_xC0107084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D0F0xBC_xC0107084_TABLE), D0F0xBC_xC0107084_TABLE } }; @@ -867,67 +867,67 @@ F1_TABLE_ENTRY_KB PPRegisterTableKB [] = { { D18F3x64_TYPE, D18F3x64_ADDRESS, - sizeof (D18F3x64_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F3x64_TABLE), D18F3x64_TABLE }, { 0x4, 0xC0500000, - sizeof (GnbFuseTableKB565_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(GnbFuseTableKB565_TABLE), GnbFuseTableKB565_TABLE }, { D18F2x90_dct0_TYPE, D18F2x90_dct0_ADDRESS, - sizeof (D18F2x90_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2x90_dct0_TABLE), D18F2x90_dct0_TABLE }, { D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, - sizeof (D18F2x94_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2x94_dct0_TABLE), D18F2x94_dct0_TABLE }, { D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, - sizeof (D18F2xA8_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F2xA8_dct0_TABLE), D18F2xA8_dct0_TABLE }, { D18F5x160_TYPE, D18F5x160_ADDRESS, - sizeof (D18F5x160_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x160_TABLE), D18F5x160_TABLE }, { D18F5x164_TYPE, D18F5x164_ADDRESS, - sizeof (D18F5x164_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x164_TABLE), D18F5x164_TABLE }, { D18F5x168_TYPE, D18F5x168_ADDRESS, - sizeof (D18F5x168_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x168_TABLE), D18F5x168_TABLE }, { D18F5x16C_TYPE, D18F5x16C_ADDRESS, - sizeof (D18F5x16C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + ARRAY_SIZE(D18F5x16C_TABLE), D18F5x16C_TABLE } }; F1_TABLE_KB F1TableKB = { - sizeof (F1RegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + ARRAY_SIZE(F1RegisterTableKB), F1RegisterTableKB }; F1_TABLE_KB PPTableKB = { - sizeof (PPRegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + ARRAY_SIZE(PPRegisterTableKB), PPRegisterTableKB }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c index bc87ddef3d..4e774a83b6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c @@ -351,7 +351,7 @@ PcieCheckPortPciDeviceMappingKB ( if (DevFunc == 0) { return TRUE; } - for (Index = 0; Index < (sizeof (DefaultPortDevMap) / sizeof (DefaultPortDevMap[0])); Index++) { + for (Index = 0; Index < ARRAY_SIZE(DefaultPortDevMap); Index++) { if (DefaultPortDevMap[Index] == DevFunc) { return TRUE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c index 10f882808a..d99fbe77cc 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c @@ -95,8 +95,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB = { &PcieInitEarlyTable[0], - sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(PcieInitEarlyTable) + }; STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { { @@ -146,8 +146,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB = { &CoreInitTable[0], - sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) -}; + ARRAY_SIZE(CoreInitTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { @@ -197,8 +197,8 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB = { &PortInitEarlyTable[0], - sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitEarlyTable) + }; STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { @@ -221,5 +221,5 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB = { &PortInitMidTable[0], - sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) -}; + ARRAY_SIZE(PortInitMidTable) + }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c index 64e7cb36fc..8c25a8b098 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -139,7 +139,7 @@ PcieAspmBlackListFeature ( GnbLibPciRead (LinkAspm->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); GnbLibPciRead (LinkAspm->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); LinkAspm->BlackList = FALSE; - for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(AspmBrDeviceTable); i = i + 3) { VendorId = AspmBrDeviceTable[i]; DeviceId = AspmBrDeviceTable[i + 1]; if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { @@ -157,7 +157,7 @@ PcieAspmBlackListFeature ( GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); DeviceId = UpstreamDeviceId >> 16; - for (i = 0; i < (sizeof (Aspm168cL0sEnabled) / sizeof (UINT16)); i++) { + for (i = 0; i < ARRAY_SIZE(Aspm168cL0sEnabled); i++) { if (DeviceId == Aspm168cL0sEnabled[i]) { LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL0sL1; LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm & AspmL1; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c index edf877264b..a74fe043b7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c @@ -289,7 +289,7 @@ PciePayloadBlackListFeature ( UINT32 VendorId; GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); - for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { + for (i = 0; i < ARRAY_SIZE(PayloadBlacklistDeviceTable); i = i + 3) { VendorId = PayloadBlacklistDeviceTable[i]; DeviceId = PayloadBlacklistDeviceTable[i + 1]; if (VendorId == (UINT16)TargetDeviceId) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c index 6ca3859b8e..95a464ae82 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c @@ -242,7 +242,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = { 0, - (sizeof (S3PciPreSelfRefDescriptorKB) / sizeof (PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3PciPreSelfRefDescriptorKB), S3PciPreSelfRefDescriptorKB, PciSpecialCaseFuncKB }; @@ -414,7 +414,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefKB = { 0, - (sizeof (S3CPciPreSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPreSelfDescriptorKB), S3CPciPreSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -608,7 +608,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefKB = { 0, - (sizeof (S3CPciPostSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPostSelfDescriptorKB), S3CPciPostSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -638,7 +638,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = { CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefKB = { 0, - (sizeof (S3MSRPreSelfRefDescriptorKB) / sizeof (MSR_REG_DESCRIPTOR)), + ARRAY_SIZE(S3MSRPreSelfRefDescriptorKB), S3MSRPreSelfRefDescriptorKB, MsrSpecialCaseFuncKB }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c index 113386e20b..f632337a3b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c @@ -207,12 +207,12 @@ MemConstructTechBlock3 ( // // Initialize the SPD pointers for each Dimm // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) { ChannelPtr->DimmSpdPtr[i] = NULL; } for (i = 0 ; i < DimmSlots; i++) { ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) { if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); |