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path: root/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
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Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c')
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
index df810d0df1..f8b70b877a 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c
@@ -234,7 +234,7 @@ MemNCmnGetSetFieldKB (
if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) {
IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n",
NBPtr->PciAddr.Address.Device, NBPtr->Dct,
- (Address >> 12) & 0xF, Address & 0xFFF, Value);
+ (Address >> 12) & 0x7, Address & 0xFFF, Value);
}
} else if (Type == DCT_PHY_ACCESS) {
if (IsPhyDirectAccess && (NumOfInstances > 1)) {
@@ -265,7 +265,7 @@ MemNCmnGetSetFieldKB (
if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) {
IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n",
NBPtr->PciAddr.Address.Device, NBPtr->Dct,
- (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
+ (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field);
}
} else if (Type == DCT_PHY_ACCESS) {
ASSERT (!NBPtr->IsSupported[ScrubberEn]); // Phy CSR write is not allowed after scrubber is enabled