diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB')
3 files changed, 644 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c new file mode 100644 index 0000000000..fddf8eb403 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c @@ -0,0 +1,308 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Option Specific Routines for common F16 + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + */ +/***************************************************************************** + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "IdsLib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF16PowerMgmt.h" +#include "F16KbPowerMgmt.h" +#include "IdsF16KbAllService.h" +#include "IdsF16KbNvDef.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbRegistersKB.h" +#include "GnbPcie.h" +#include "GnbHandleLib.h" +#include "GnbRegisterAccKB.h" +#include "IdsRegAcc.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE + +/** + * IDS F16 Backend Function for HTC Controls + * + * This function is used to override HTC control Parameter. + * + * @param[in,out] DataPtr The Pointer of HTC register. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubHTCControlF16Kb ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + HTC_REGISTER *PHtcReg; + IDS_STATUS NvValue; + + PHtcReg = (HTC_REGISTER *) DataPtr; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_EN, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvThermalHTCEnDisabled: + PHtcReg->HtcEn = 0; + break; + case IdsNvThermalHTCEnEnabled: + PHtcReg->HtcEn = 1; + break; + case IdsNvThermalHTCEnAuto: + break; + default: + ASSERT (FALSE); + break; + } + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_OVERRIDE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvThermalHTCOverrideDisabled: + break; + case IdsNvThermalHTCOverrideEnabled: + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_PSTATE_LIMIT, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHtcPstateLimitMin) && (NvValue <= IdsNvThermalHtcPstateLimitMax)); + PHtcReg->HtcPstateLimit = NvValue; + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_TEMP_HYS, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHTCTempHysMin) && (NvValue <= IdsNvThermalHTCTempHysMax)); + PHtcReg->HtcHystLmt = NvValue; + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_ACT_TEMP, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHTCActTempMin) && (NvValue <= IdsNvThermalHTCActTempMax)); + PHtcReg->HtcTmpLmt = NvValue; + } + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Memory Mapping + * + * This function is used to override the following setting. + * EnableBankIntlv, ChannelIntlvMode, EnableNodeIntlv, MemHole, + * EnablePowerDown, PowerDownMode, EnableBurstLen32, BankSwizzle, + * UserTimingMode, MemClockValue, EnableParity, DqsTrainCtl, AllMemClks, + * and EnableClkHZAltVidC3. + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubMemoryMappingF16Kb ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + MEM_PARAMETER_STRUCT *RefPtr; + IDS_STATUS NvValue; + MEM_DATA_STRUCT * memdataptr; + + PostParamsPtr = (AMD_POST_PARAMS *)DataPtr; + memdataptr = PostParamsPtr->MemConfig.MemData; + RefPtr = memdataptr->ParameterListPtr; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_BANK_INTERLEAVE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvMemMappingBankInterleaveDisabled: + RefPtr->EnableBankIntlv = FALSE; + break; + case IdsNvMemMappingBankInterleaveAuto: + RefPtr->EnableBankIntlv = TRUE; + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for override GNB platform config + * + * @param[in,out] DataPtr The Pointer of BOOLEAN. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubGnbPlatformCfgF16Kb ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + GFX_PLATFORM_CONFIG *PGfx; + IDS_STATUS NvValue; + + PGfx = (GFX_PLATFORM_CONFIG*) DataPtr; + //NB Azalia + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_GNBHDAUDIOEN, IdsNvPtr, StdHeader) { + switch (NvValue) { + //Auto + case IdsNvGnbGfxNbAzaliaAuto: + break; + //Disabled + case IdsNvGnbGfxNbAzaliaDisabled: + PGfx->GnbHdAudio = 0; + break; + //Enabled + case IdsNvGnbGfxNbAzaliaEnabled: + PGfx->GnbHdAudio = 1; + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} +/** + * IDS Family specific Function for programming GMMX register + * + * @param[in,out] DataPtr The Pointer of BOOLEAN. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * + **/ +STATIC IDS_STATUS +IdsRegSetGmmxF16Kb ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IdsRegAcc132_STRUCT *PIdsRegGmmx; + UINT32 Value; + GNB_HANDLE *GnbHandle; + + PIdsRegGmmx = (IdsRegAcc132_STRUCT *) DataPtr; + GnbHandle = GnbGetHandle (StdHeader); + + GnbRegisterReadKB ( + GnbHandle, + 0x12, + PIdsRegGmmx->Offset, + &Value, + 0, + StdHeader); + + IdsLibDataMaskSet32 (&Value, PIdsRegGmmx->AndMask, PIdsRegGmmx->OrMask); + + GnbRegisterWriteKB ( + GnbHandle, + 0x12, + PIdsRegGmmx->Offset, + &Value, + 0, + StdHeader); + + return IDS_SUCCESS; +} + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF16Kb = +{ + IDS_FEAT_HTC_CTRL, + IDS_ALL_CORES, + IDS_HTC_CTRL, + AMD_FAMILY_16_KB, + IdsSubHTCControlF16Kb +}; + + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF16Kb = +{ + IDS_FEAT_MEMORY_MAPPING, + IDS_ALL_CORES, + IDS_INIT_POST_BEFORE, + AMD_FAMILY_16_KB, + IdsSubMemoryMappingF16Kb +}; + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF16Kb = +{ + IDS_FEAT_GNB_PLATFORMCFG, + IDS_ALL_CORES, + IDS_GNB_PLATFORMCFG_OVERRIDE, + AMD_FAMILY_16_KB, + IdsSubGnbPlatformCfgF16Kb +}; + +// For register access +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF16Kb = + MAKE_IDS_FAMILY_FEAT_ALL_CORES ( + dummy210, + AMD_FAMILY_16_KB, + IdsRegSetGmmxF16Kb + ); + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h new file mode 100644 index 0000000000..3288143832 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h @@ -0,0 +1,49 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA IDS Translation + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _IDS_F16_KB_ALLSERVICE_H_ +#define _IDS_F16_KB_ALLSERVICE_H_ +#ifdef __IDS_EXTENDED__ + #include IDS_EXT_INCLUDE_F16_KB (IdsIntF16KbAllService) +#endif + +#endif //_IDS_F16_KB_ALLSERVICE_H_ + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h new file mode 100644 index 0000000000..c08bdb3ce3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h @@ -0,0 +1,287 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IDS NV definition for F16Kb + * + * Auto generated from CBS XML file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS F16Kb + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + +#ifndef _IDSF16KBNVDEF_H_ +#define _IDSF16KBNVDEF_H_ +///HTC Enable +///Enable or disable Hardware Thermal Control. D18F3x64[0] +typedef enum { + IdsNvThermalHTCEnDisabled = 0,///<Disabled + IdsNvThermalHTCEnEnabled = 1,///<Enabled + IdsNvThermalHTCEnAuto = 3,///<Auto +} IdsNvThermalHTCEn; + +///HTC Override +///Enable or disable Thermal Control Override +typedef enum { + IdsNvThermalHTCOverrideDisabled = 0,///<Disabled + IdsNvThermalHTCOverrideEnabled = 1,///<Enabled +} IdsNvThermalHTCOverride; + +///HTC P-state limit select +///Specifies the P-state limit of all cores when in the P-state based HTC-active state +#define IdsNvThermalHtcPstateLimitMin 0 +#define IdsNvThermalHtcPstateLimitMax 7 + +///HTC Temperature Hysteresis +///Sets the temperature hysteresis for HTC. D18F3x64[27:24] +#define IdsNvThermalHTCTempHysMin 0 +#define IdsNvThermalHTCTempHysMax 0xF + +///HTC Activation Temp +///Sets the HTC temperature limit. D18F3x64[22:16] +#define IdsNvThermalHTCActTempMin 0 +#define IdsNvThermalHTCActTempMax 0x7F + +///Bank Interleave +///Interleave memory blocks across the DRAM chip selects for node 0. +typedef enum { + IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled + IdsNvMemMappingBankInterleaveAuto = 1,///<Auto +} IdsNvMemMappingBankInterleave; + +///DRAM Channel Interleave +///Interleave between two DCTs when they are in unganged mode. +typedef enum { + IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6 + IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12 + IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6] + IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9] + IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8 + IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9 + IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled + IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto +} IdsNvMemMappingChlInterleave; + +///ECC Symbol Size +///ECC symbol size and code selection. D18F3x180[25] +typedef enum { + IdsNvEccSymbolSizex4 = 0,///<x4 + IdsNvEccSymbolSizex8 = 1,///<x8 + IdsNvEccSymbolSizeAuto = 3,///<Auto +} IdsNvEccSymbolSize; + +///DRAM prefetches triggered from CPU requests +///Enable or disable DRAM prefetches Prefetch triggered by CPU requests. +typedef enum { + IdsNvPrefetchPrefCpuDis0 = 0,///<0 + IdsNvPrefetchPrefCpuDis1 = 1,///<1 + IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto +} IdsNvPrefetchPrefCpuDis; + +///HW prefetch training on SW Prefetches +///Enable or disable Hardware Prefetch training on Software Prefetches +typedef enum { + IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0 + IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1 + IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto +} IdsNvPrefetchDisHWPFforSWPF; + +///Hardware Prefetches +///Enable or disable Hardware Prefetches. +typedef enum { + IdsNvPrefetchDisHWPF0 = 0,///<0 + IdsNvPrefetchDisHWPF1 = 1,///<1 + IdsNvPrefetchDisHWPFAuto = 3,///<Auto +} IdsNvPrefetchDisHWPF; + +///UMI Gen2 +///Enable or disable UMI link Gen2 +typedef enum { + IdsNvFchGppUmiGen2Disabled = 0,///<Disabled + IdsNvFchGppUmiGen2Enabled = 1,///<Enabled +} IdsNvFchGppUmiGen2; + +///SATA Controller +///Disable or enable OnChip SATA controller +typedef enum { + IdsNvFchSataEnableDisabled = 0,///<Disabled + IdsNvFchSataEnableEnabled = 1,///<Enabled +} IdsNvFchSataEnable; + +///SATA Mode +///Select OnChip SATA Type +typedef enum { + IdsNvFchSataClassNative_IDE = 0,///<Native IDE + IdsNvFchSataClassRAID = 1,///<RAID + IdsNvFchSataClassAHCI = 3,///<AHCI + IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE + IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI + IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804 + IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804 +} IdsNvFchSataClass; + +///OnChip IDE +///Select OnChip IDE controller mode +typedef enum { + IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE + IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE +} IdsNvFchSataIdeMode; + +///IDE Controller +///Disable or enable OnChip IDE controller +typedef enum { + IdsNvFchSataIdeEnableDisabled = 0,///<Disabled + IdsNvFchSataIdeEnableEnabled = 1,///<Enabled +} IdsNvFchSataIdeEnable; + +///XHC Switch (Bus 0 Dev 16 Fn 0/1) +///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1) +typedef enum { + IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled + IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled +} IdsNvFchUsbXhciSwitch; + +///USB1(Bus 0 Dev 18 Fn 0/2) +///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci1Enable; + +///USB2 (Bus 0 Dev 19 Fn 0/2) +///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci2Enable; + +///USB3 (Bus 0 Dev 22 Fn 0/2) +///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci3Enable; + +///USB4 (Bus 0 Dev 20 Fn 5) +///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5) +typedef enum { + IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci4Enable; + +///Hardware Monitor Enable +///Master switch to enable or disable hardware monitor function +typedef enum { + IdsNvFchHwmEnableDisabled = 0,///<Disabled + IdsNvFchHwmEnableEnabled = 1,///<Enabled +} IdsNvFchHwmEnable; + +///In-Chip IR +///Enable or disable the In-Chip IR +typedef enum { + IdsNvFchIrConfigDisabled = 0,///<Disabled + IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only + IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only + IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1 +} IdsNvFchIrConfig; + +///SD Configuration Mode +///Select SD Mode +typedef enum { + IdsNvFchSdConfigDisabled = 0,///<Disabled + IdsNvFchSdConfigADMA = 1,///<ADMA + IdsNvFchSdConfigDMA = 2,///<DMA + IdsNvFchSdConfigPIO = 3,///<PIO +} IdsNvFchSdConfig; + +///Azalia Device +///Select disable or enable Azalia Device +typedef enum { + IdsNvFchAzaliaControlAuto = 0,///<Auto + IdsNvFchAzaliaControlDisabled = 1,///<Disabled + IdsNvFchAzaliaControlEnabled = 2,///<Enabled + IdsNvFchAzaliaControlReserved = 3,///<Reserved +} IdsNvFchAzaliaControl; + +///Integrated Graphics Controller +///Enable Integrate Graphics controller +typedef enum { + IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto + IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled + IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces +} IdsNvGnbGfxiGPU_CONTROL; + +///UMA Frame buffer Size +///Set UMA FB size +typedef enum { + IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto + IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M + IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M + IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M + IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M + IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M + IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M + IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G + IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G + IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G +} IdsNvGnbGfxUmaFrameBufferSize; + +///NB Azalia +///Enable Integrate HD Audio controller +typedef enum { + IdsNvGnbGfxNbAzaliaDisabled = 0,///<Disabled + IdsNvGnbGfxNbAzaliaEnabled = 1,///<Enabled + IdsNvGnbGfxNbAzaliaAuto = 0xf,///<Auto +} IdsNvGnbGfxNbAzalia; + +///PSPP Policy +///PCIe speed power policy +typedef enum { + IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled + IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance + IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High + IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low + IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving + IdsNvGnbPciePsppPolicyAuto = 5,///<Auto +} IdsNvGnbPciePsppPolicy; + +///IOMMU +/// +typedef enum { + IdsNvGnbNbIOMMUDisabled = 0,///<Disabled + IdsNvGnbNbIOMMUEnabled = 1,///<Enabled +} IdsNvGnbNbIOMMU; + +#endif // _IDSF16KBNVDEF_H_ + |