diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/GNB')
174 files changed, 82525 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h new file mode 100644 index 0000000000..100ae03036 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87645 $ @e \$Date: 2013-02-06 13:08:17 -0600 (Wed, 06 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNB_H_ +#define _GNB_H_ + +#include "Ids.h" + +#pragma pack (push, 1) + +#define GNB_DEADLOOP() \ +{ \ + VOLATILE BOOLEAN k; \ + k = TRUE; \ + while (k) { \ + } \ +} +#ifdef IDSOPT_TRACING_ENABLED + #if (IDSOPT_TRACING_ENABLED == TRUE) + #define GNB_TRACE_ENABLE + #endif +#endif + + +#ifndef GNB_DEBUG_CODE + #ifdef GNB_TRACE_ENABLE + #define GNB_DEBUG_CODE(Code) Code + #else + #define GNB_DEBUG_CODE(Code) + #endif +#endif + +#ifndef MIN + #define MIN(x, y) (((x) > (y))? (y):(x)) +#endif + +#ifndef MAX + #define MAX(x, y) (((x) > (y))? (x):(y)) +#endif + +#define OFF 0 + +#define PVOID UINT32 + +#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a)) + +#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader) + +#define AGESA_STATUS_UPDATE(Current, Aggregated) \ +if (Current > Aggregated) { \ + Aggregated = Current; \ +} + +#ifndef offsetof + #define offsetof(s, m) (UINTN)&(((s *)0)->m) +#endif + + +//Table properties + +#define TABLE_PROPERTY_DEFAULT 0x00000000ul +#define TABLE_PROPERTY_IGFX_DISABLED 0x00000001ul +#define TABLE_PROPERTY_IOMMU_DISABLED 0x00000002ul +#define TABLE_PROPERTY_LCLK_DEEP_SLEEP 0x00000004ul +#define TABLE_PROPERTY_BAPM 0x00000100ul +#define TABLE_PROPERTY_NBDPM 0x00000800ul +#define TABLE_PROPERTY_LOADLINE_ENABLE 0x00001000ul +#define TABLE_PROPERTY_LHTC 0x00010000ul +#define TABLE_PROPERTY_SVI2 0x00020000ul + +//Register access flags Flags +#define GNB_REG_ACC_FLAG_S3SAVE 0x00000001ul + +// Gnb PCIe Master PLL +#define GNB_PCIE_MASTERPLL_A 0xA +#define GNB_PCIE_MASTERPLL_B 0xB +#define GNB_PCIE_MASTERPLL_C 0xC +#define GNB_PCIE_MASTERPLL_D 0xD + +/// LCLK DPM enable control +typedef enum { + LclkDpmDisabled, ///<LCLK DPM disabled + LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method +} LCLK_DPM_MODE; + + + + +/// Topology information +typedef struct { + BOOLEAN PhantomFunction; ///< PCIe topology have device with phantom function + BOOLEAN PcieToPciexBridge; ///< PCIe topology have device with Pcieto Pcix bridge +} GNB_TOPOLOGY_INFO; + + +/// GNB installable services +typedef enum { + GnbPcieFamConfigService, ///< PCIe config service + GnbPcieFamInitService, ///< PCIe Init service + GnbPcieFamDebugService, ///< PCIe Debug service + GnbRegisterAccessService, ///< GNB register access service + GnbIommuService, ///< GNB IOMMU config service + GnbUraService, ///< GNB Ura service + GfxFamService, ///< GFX Family service + GnbPcieMaxPayloadService, ///< GNB MaxPayload service + GnbFamTsService ///< GNB TimeStamp service +} GNB_SERVICE_ID; + +/// GNB service entry +typedef struct _GNB_SERVICE { + GNB_SERVICE_ID ServiceId; ///< Service ID + UINT64 Family; ///< CPU family + VOID *ServiceProtocol; ///< Service protocol + struct _GNB_SERVICE *NextService; ///< Pointer to next service +} GNB_SERVICE; + +/// GNB SMU Firmware Pointers +typedef struct _GNB_FW_PTRS { + VOID *FirmwareType1; ///< Pointer to Type 1 SMU Firmware + VOID *FirmwareType2; ///< Poitner to Type 2 SMU Firmware +} GNB_FW_PTRS; + + +#define GNB_STRINGIZE(x) #x +#define GNB_SERVICE_DEFINITIONS(x) GNB_STRINGIZE (Services/x/x.h) +#define GNB_MODULE_DEFINITIONS(x) GNB_STRINGIZE (Modules/x/x.h) +#define GNB_MODULE_INSTALL(x) GNB_STRINGIZE (Modules/x/x##Install.h) +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h new file mode 100644 index 0000000000..add550924b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h @@ -0,0 +1,99 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84159 $ @e \$Date: 2012-12-12 20:20:16 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#ifndef _GNBF1TABLE_H_ +#define _GNBF1TABLE_H_ + +#pragma pack (push, 1) + +#define PP_F1_MAX_NUM_DPM_STATE 5 +#define PP_F1_MAX_NUM_SW_STATE 6 + +typedef struct { + UINT8 PPlayTableRev; ///< PP table revision + UINT8 PP_FUSE_ARRAY_V2_fld1[5]; + UINT8 PP_FUSE_ARRAY_V2_fld2[5]; + UINT8 PP_FUSE_ARRAY_V2_fld3; + UINT8 PP_FUSE_ARRAY_V2_fld4[6]; + UINT8 PP_FUSE_ARRAY_V2_fld5[5]; + UINT8 excel841_fld6[5]; ///< DispClk DID + UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID + UINT8 MainPllId; ///< Main PLL Id from fuses + UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 GpuBoostCap; ///< GPU boost cap + UINT32 PP_FUSE_ARRAY_V2_fld11; + UINT32 PP_FUSE_ARRAY_V2_fld12; + BOOLEAN PP_FUSE_ARRAY_V2_fld13; + UINT8 VceFlags[5]; ///< VCE Flags + UINT8 VceMclk; ///< MCLK for VCE + UINT8 PP_FUSE_ARRAY_V2_fld16[4]; + UINT8 EclkDid[5]; ///< Eclk DID + UINT8 HtcEn; ///< HTC Enabled + UINT8 HtcTmpLmt; ///< HTC Temperature Limit + UINT8 PP_FUSE_ARRAY_V2_fld20; + UINT8 PP_FUSE_ARRAY_V2_fld21; + UINT8 DisDllShutdownSR[4]; ///< DRAM Configuration Low [per DCT] + UINT8 MemClkFreq[4]; ///< DRAM Configuration High [per DCT] + UINT8 MemPhyPllPdMode[4]; ///< DRAM Controller Miscellaneous 2 [per DCT] + UINT8 M1MemClkFreq[4]; ///< Memory PState Control and Status [per DCT] + UINT8 PP_FUSE_ARRAY_V2_fld26[4]; + UINT8 PP_FUSE_ARRAY_V2_fld27[4]; + UINT8 PP_FUSE_ARRAY_V2_fld28[4]; + UINT8 PP_FUSE_ARRAY_V2_fld29[4]; + UINT8 PP_FUSE_ARRAY_V2_fld30[4]; + UINT8 PP_FUSE_ARRAY_V2_fld31[4]; + UINT8 PP_FUSE_ARRAY_V2_fld32[5]; + UINT8 PP_FUSE_ARRAY_V2_fld33[5]; + UINT8 PP_FUSE_ARRAY_V2_fld34[5]; + UINT8 PP_FUSE_ARRAY_V2_fld35[5]; + UINT8 PP_FUSE_ARRAY_V2_fld36; + UINT8 PP_FUSE_ARRAY_V2_fld37; + UINT8 PP_FUSE_ARRAY_V2_fld38; +} PP_F1_ARRAY_V2; + +#pragma pack (pop) + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h new file mode 100644 index 0000000000..94510c32b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBFAMSERVICES_H_ +#define _GNBFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" + +typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader +); + +/// Register Read/Write protocol +typedef struct { + F_GNB_REGISTER_ACCESS *Read; ///< Read Register + F_GNB_REGISTER_ACCESS *Write; ///< Write Register +} GNB_REGISTER_SERVICE; + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_GNBFMCREATEIVRSENTRY ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef BOOLEAN F_GNBFMCHECKIOMMUPRESENT ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GNB IOMMU services +typedef struct { + F_GNBFMCHECKIOMMUPRESENT *GnbFmCheckIommuPresent; ///< GnbFmCheckIommuPresent + F_GNBFMCREATEIVRSENTRY *GnbFmCreateIvrsEntry; ///< GnbFmCreateIvrsEntry +} GNB_FAM_IOMMU_SERVICES; + + +typedef UINT8 (F_PCIE_MAXPAYLOAD_SETTING) ( + IN PCIe_ENGINE_CONFIG *Engine +); + +/// MaxPayload service protocol +typedef struct { + F_PCIE_MAXPAYLOAD_SETTING *SetMaxPayload; ///< Write Register +} PCIE_MAXPAYLOAD_SERVICE; + + + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT32 F_GNBTIMESTAMP ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GNB Timestamp services +typedef struct { + F_GNBTIMESTAMP *GnbFmTimeStamp; ///< GnbFmTimeStamp +} GNB_FAM_TS_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h new file mode 100644 index 0000000000..d5c571bb3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h @@ -0,0 +1,348 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86709 $ @e \$Date: 2013-01-24 17:39:09 -0600 (Thu, 24 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFX_H_ +#define _GNBGFX_H_ + +#define DEVICE_DFP 0x1 +#define DEVICE_CRT 0x2 +#define DEVICE_LCD 0x3 + + +#define CONNECTOR_DISPLAYPORT_ENUM 0x3013 +#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 +#define CONNECTOR_VGA_ENUM 0x3005 +#define CONNECTOR_LVDS_ENUM 0x300E +#define CONNECTOR_eDP_ENUM 0x3014 +#define CONNECTOR_LVDS_eDP_ENUM 0x3016 +//DP to VGA: +#define ENCODER_DP2VGA_ENUM_ID1 0x2123 +//DP to LVDS: +#define ENCODER_DP2LVDS_ENUM_ID2 0x2223 +#define ENCODER_ALMOND_ENUM_ID1 0x2122 +#define ENCODER_NOT_PRESENT 0x0000 + +// no eDP->LVDS translator chip +#define eDP_TO_LVDS_RX_DISABLE 0x00 +// common eDP->LVDS translator chip without AMD SW init +#define eDP_TO_LVDS_COMMON_ID 0x01 +// Third party translator which requires AMD SW init +#define eDP_TO_LVDS_SWINIT_ID 0x02 + + +#define ATOM_DEVICE_CRT1_SUPPORT 0x0001 +#define ATOM_DEVICE_DFP1_SUPPORT 0x0008 +#define ATOM_DEVICE_DFP6_SUPPORT 0x0040 +#define ATOM_DEVICE_DFP2_SUPPORT 0x0080 +#define ATOM_DEVICE_DFP3_SUPPORT 0x0200 +#define ATOM_DEVICE_DFP4_SUPPORT 0x0400 +#define ATOM_DEVICE_DFP5_SUPPORT 0x0800 +#define ATOM_DEVICE_LCD1_SUPPORT 0x0002 + +/// Graphics card information structure +typedef struct { + UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information + UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information + UINT32 PciGfxCardBitmap; ///< All PCI graphics card information +} GFX_CARD_CARD_INFO; + +typedef enum { + iGpuVgaAdapter, ///< Configure iGPU as VGA adapter + iGpuVgaNonAdapter ///< Configure iGPU as non VGA adapter +} GFX_IGPU_VGA_MODE; + +/// UMA Steering Mode +typedef enum { + UMA_STEERING_ENUM0, + SystemTrafficOnion, ///< System traffic to onion + Onion, ///< Onion + UMA_STEERING_ENUM3, +} UMA_STEERING; + +/// User Options +typedef enum { + OptionDisabled, ///< Disabled + OptionEnabled ///< Enabled +} CONTROL_OPTION; + +/// GFX enable Policy +typedef enum { + GmcPowerGatingDisabled, ///< Disable Power gating + GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode + GmcPowerGatingWithStutter ///< GMC Power gating with Stutter mode +} GMC_POWER_GATING; + +/// Internal GFX mode +typedef enum { + GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode + GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1 +} GFX_CONTROLLER_MODE; + +/// Graphics Platform Configuration +typedef struct { + PVOID StdHeader; ///< Standard Header + PCI_ADDR GfxPciAddress; ///< Graphics PCI Address + UMA_INFO UmaInfo; ///< UMA Information + UINT64 GmmBase; ///< GMM Base + UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), + ///< essentially it enables function 1 of graphics device. + ///< @li 0 = HD Audio disable + ///< @li 1 = HD Audio enable + UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is + ///< characteristic specific to display panel which used by platform design. + ///< @li 0 = ABM support disabled + ///< @li 1 = ABM support enabled + UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. + UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. + ///< If equal to 0 backlight not controlled by iGPU. + UINT32 AmdPlatformType; ///< Platform type + UMA_STEERING UmaSteering; ///< UMA Steering + GFX_IGPU_VGA_MODE iGpuVgaMode; ///< iGPU VGA mode + BOOLEAN GmcClockGating; ///< Clock gating + BOOLEAN GmcLockRegisters; ///< GmcLock Registers + BOOLEAN GfxFusedOff; ///< Record if GFX is fused off. + GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating. + UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID + GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode + UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % + UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + UINT8 LvdsPowerOnSeqDigonToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToDigon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing. + UINT16 LvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported. + UINT32 LcdBitDepthControlValue; ///< The LCD bit depth control settings. + UINT8 Lvds24bbpPanelMode; ///< The LVDS 24 BBP mode. + LVDS_MISC_CONTROL LvdsMiscControl; ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; ///< Discrete GFX card info + UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % + BOOLEAN GnbRemoteDisplaySupport; ///< Wireless Display Enable + UINT8 LVDSVoltAdjust; ///< when ucLVDSMisc[5]=1, then this value will be programmed to register LVDS_CTRL_4 to adjust LVDS output voltage + DISPLAY_MISC_CONTROL DisplayMiscControl; ///< The Display misc control + DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType; ///< To indicate fixed voltage swing value + UINT8 MinAllowedBLLevel; ///< Minimum allowed LCD backlight level +} GFX_PLATFORM_CONFIG; + + +typedef UINT32 ULONG; +typedef UINT16 USHORT; +typedef UINT8 UCHAR; + +/// Driver interface header structure +typedef struct _ATOM_COMMON_TABLE_HEADER { + USHORT usStructureSize; ///< Structure size + UCHAR ucTableFormatRevision; ///< Format revision number + UCHAR ucTableContentRevision; ///< Contents revision number +} ATOM_COMMON_TABLE_HEADER; + +/// Link ping mapping for DP/eDP/LVDS +typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING { + UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DP_CONN_CHANNEL_MAPPING; + +/// Link ping mapping for DVI/HDMI +typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING { + UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DVI_CONN_CHANNEL_MAPPING; + + +/// External Display Path +typedef struct _EXT_DISPLAY_PATH { + USHORT usDeviceTag; ///< A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; ///< 16bit device ACPI id. + USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions + UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT + UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT + USHORT usExtEncoderObjId; ///< external encoder object id + union { ///< Lane mapping + UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + } ChannelMapping; + UCHAR ucChPNInvert; ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted + USHORT usCaps; ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1 + USHORT usReserved; ///< Reserved +} EXT_DISPLAY_PATH; + +/// External Display Connection Information +typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header + UCHAR ucGuid [16]; ///< Guid + EXT_DISPLAY_PATH sPath[7]; ///< External Display Path + UCHAR ucChecksum; ///< Checksum + UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID + UCHAR ucRemoteDisplayConfig; ///< Bit0=1:Enable Wireless Display through APU VCE HW function + UCHAR uceDPToLVDSRxId; ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Third party translator which require AMD SW init + UCHAR ucFixDPVoltageSwing; ///< The value match DPCD register DPx_LANE_SET defined in DP spec + UCHAR Reserved [3]; ///< Reserved +} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +/// DispClk to VID relation table +typedef struct _ATOM_CLK_VOLT_CAPABILITY { + ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz +} ATOM_CLK_VOLT_CAPABILITY; + +typedef struct _GnbGfx275_STRUCT { + ULONG GnbGfx275_STRUCT_fld0; + USHORT GnbGfx275_STRUCT_fld1; + USHORT GnbGfx275_STRUCT_fld2; +} GnbGfx275_STRUCT; + +/// TDP Configuration Bitfields +typedef struct _ATOM_TDP_CONFIG_BITS { + UINT32 uCTDP_Enable:2; ///< = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) + UINT32 uCTDP_Value:14; ///< Override value in tens of milli watts + UINT32 uTDP_Value:14; ///< Original TDP value in tens of milli watts + UINT32 uReserved:2; ///< Reserved +} ATOM_TDP_CONFIG_BITS; + +/// TDP Configuration Union +typedef union _ATOM_TDP_CONFIG { + ATOM_TDP_CONFIG_BITS TDP_config; ///< Field-wise access + ULONG TDP_config_all; ///< Access to all +} ATOM_TDP_CONFIG; + + +/// IntegrateSystemInfoTable is used for Kaveri & Kabini APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< + ULONG ulBootUpEngineClock; ///< + ULONG field2; ///< + ULONG ulBootUpUMAClock; ///< + ATOM_CLK_VOLT_CAPABILITY ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld4[4]; ///< + ULONG ulBootUpReqDisplayVector; ///< + ULONG ulVBIOSMisc; ///< + ULONG ulGPUCapInfo; ///< + ULONG ulReserved1; ///< + USHORT usRequestedPWMFreqInHz; ///< + UCHAR ucHtcTmpLmt; ///< + UCHAR ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11; ///< + ULONG ulReserved2; ///< + ULONG ulSystemConfig; ///< + ULONG ulCPUCapInfo; ///< + ULONG ulReserved3; ///< + USHORT usReserved1; ///< + USHORT usExtDispConnInfoOffset; ///< + USHORT usPanelRefreshRateRange; ///< + UCHAR ucMemoryType; ///< + UCHAR ucUMAChannelNumber; ///< + UCHAR strVBIOSMsg[40]; ///< + ULONG ulReserved[20]; ///< + GnbGfx275_STRUCT ATOM_INTEGRATED_SYSTEM_INFO_V1_8[5]; ///< + ULONG ulGMCRestoreResetTime; ///< + ULONG ulReserved4; ///< + ULONG ulIdleNClk; ///< + ULONG ulDDR_DLL_PowerUpTime; ///< + ULONG ulDDR_PLL_PowerUpTime; ///< + USHORT usPCIEClkSSPercentage; ///< + USHORT usPCIEClkSSType; ///< + USHORT usLvdsSSPercentage; ///< + USHORT usLvdsSSpreadRateIn10Hz; ///< + USHORT usHDMISSPercentage; ///< + USHORT usHDMISSpreadRateIn10Hz; ///< + USHORT usDVISSPercentage; ///< + USHORT usDVISSpreadRateIn10Hz; ///< + ULONG ulReserved5[5]; ///< + USHORT usMaxLVDSPclkFreqInSingleLink; ///< + UCHAR ucLvdsMisc; ///< + UCHAR ucLVDSVoltAdjust; ///< + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; ///< + UCHAR ucLVDSOffToOnDelay_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///< + UCHAR ucMinAllowedBL_Level; ///< + ULONG ulLCDBitDepthControlVal; ///< + ULONG ulNbpStateMemclkFreq[4]; ///< + ULONG ulReserved6; ///< + ULONG ulNbpStateNClkFreq[4]; ///< + USHORT usNBPStateVoltage[4]; ///< + USHORT usBootUpNBVoltage; ///< + USHORT usReserved2; ///< + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< +} ATOM_INTEGRATED_SYSTEM_INFO_V1_8; + +/// this Table is used for Kaveri/Kabini APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 { + ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition. + ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +} ATOM_FUSION_SYSTEM_INFO_V3; + +#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0) + +/// Define configuration values for ulGPUCapInfo +// BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use single PLL mode. +#define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE 0x01ul + +// BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode +#define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE 0x02ul + +// BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE 0x00ul +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE 0x08ul + +// BIT[4] - DFS bypass 0: Disable, 1: Enable +#define GPUCAPINFO_DFS_BYPASS_DISABLE 0x00ul +#define GPUCAPINFO_DFS_BYPASS_ENABLE 0x10ul + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h new file mode 100644 index 0000000000..b4160e6e87 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBGFXFAMSERVICES_H_ +#define _GNBGFXFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" + +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +typedef AGESA_STATUS F_GFXMAPENGINETODISPLAYPATH ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT32 F_GFXCALCULATECLOCK ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +typedef BOOLEAN F_GFXISVBIOSPOSTED ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID F_GFXDISABLECONTROLLER ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GFX Family services +typedef struct { + F_GFXMAPENGINETODISPLAYPATH *GfxMapEngineToDisplayPath; ///< GfxMapEngineToDisplayPath + F_GFXDISABLECONTROLLER *GfxDisableController; ///< GfxDisableController + F_GFXCALCULATECLOCK *GfxCalculateClock; ///< GfxCalculateClock + F_GFXISVBIOSPOSTED *GfxIsVbiosPosted; ///< GfxIsVbiosPosted; +} GFX_FAM_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h new file mode 100644 index 0000000000..c37c2148fa --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h @@ -0,0 +1,195 @@ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBIOMMU_H_ +#define _GNBIOMMU_H_ + +#pragma pack (push, 1) + + +/// IVRS block +typedef enum { + IvrsIvhdBlock = 0x10, ///< I/O Virtualization Hardware Definition Block + IvrsIvmdBlock = 0x20, ///< I/O Virtualization Memory Definition Block for all peripherals + IvrsIvmdBlockSingle = 0x21, ///< IVMD block for specified peripheral + IvrsIvmdBlockRange = 0x22, ///< IVMD block for peripheral range + IvrsIvhdrBlock = 0x40, ///< IVHDR (Relative) block + IvrsIvmdrBlock = 0x50, ///< IVMDR (Relative) block for all peripherals + IvrsIvmdrBlockSingle = 0x51 ///< IVMDR block for last IVHDR +} IVRS_BLOCK_TYPE; + +#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function) + +/// IVHD entry types +typedef enum { + IvhdEntryPadding = 0, ///< Table padding + IvhdEntrySelect = 2, ///< Select + IvhdEntryStartRange = 3, ///< Start Range + IvhdEntryEndRange = 4, ///< End Range + IvhdEntryAliasSelect = 66, ///< Alias select + IvhdEntryAliasStartRange = 67, ///< Alias start range + IvhdEntryExtendedSelect = 70, ///< Extended select + IvhdEntryExtendedStartRange = 71, ///< Extended Start range + IvhdEntrySpecialDevice = 72 ///< Special device +} IVHD_ENTRY_TYPE; + +/// Special device variety +typedef enum { + IvhdSpecialDeviceIoapic = 0x1, ///< IOAPIC + IvhdSpecialDeviceHpet = 0x2 ///< HPET +} IVHD_SPECIAL_DEVICE; + + +#define IVHD_FLAG_COHERENT BIT5 +#define IVHD_FLAG_IOTLBSUP BIT4 +#define IVHD_FLAG_ISOC BIT3 +#define IVHD_FLAG_RESPASSPW BIT2 +#define IVHD_FLAG_PASSPW BIT1 +#define IVHD_FLAG_PPRSUB BIT7 +#define IVHD_FLAG_PREFSUP BIT6 + +#define IVHD_EFR_XTSUP_OFFSET 0 +#define IVHD_EFR_NXSUP_OFFSET 1 +#define IVHD_EFR_GTSUP_OFFSET 2 +#define IVHD_EFR_GLXSUP_OFFSET 3 +#define IVHD_EFR_IASUP_OFFSET 5 +#define IVHD_EFR_GASUP_OFFSET 6 +#define IVHD_EFR_HESUP_OFFSET 7 +#define IVHD_EFR_PASMAX_OFFSET 8 +#define IVHD_EFR_PNCOUNTERS_OFFSET 13 +#define IVHD_EFR_PNBANKS_OFFSET 17 +#define IVHD_EFR_MSINUMPPR_OFFSET 23 +#define IVHD_EFR_GATS_OFFSET 28 +#define IVHD_EFR_HATS_OFFSET 30 + +#define IVINFO_HTATSRESV_MASK 0x00400000ul +#define IVINFO_VASIZE_MASK 0x003F8000ul +#define IVINFO_PASIZE_MASK 0x00007F00ul +#define IVINFO_GASIZE_MASK 0x000000E0ul + +#define IVHD_INFO_MSINUM_OFFSET 0 +#define IVHD_INFO_UNITID_OFFSET 8 + +#define IVMD_FLAG_EXCLUSION_RANGE BIT3 +#define IVMD_FLAG_IW BIT2 +#define IVMD_FLAG_IR BIT1 +#define IVMD_FLAG_UNITY BIT0 + +/// IVRS header +typedef struct { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 IvInfo; ///< IvInfo + UINT64 Reserved; ///< Reserved +} IOMMU_IVRS_HEADER; + +/// IVRS IVHD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 CapabilityOffset; ///< CapabilityOffset + UINT64 BaseAddress; ///< BaseAddress + UINT16 PciSegment; ///< Pci segment + UINT16 IommuInfo; ///< IOMMU info + UINT32 IommuEfr; ///< reserved +} IVRS_IVHD_ENTRY; + +/// IVHD generic entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings +} IVHD_GENERIC_ENTRY; + +///IVHD alias entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT8 Reserved; ///< Reserved + UINT16 AliasDeviceId; ///< Alias device id + UINT8 Reserved2; ///< Reserved +} IVHD_ALIAS_ENTRY; + +///IVHD extended entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT32 ExtSetting; ///< Extended settings +} IVHD_EXT_ENTRY; + +/// IVHD special entry +typedef struct { + UINT8 Type; ///< Type + UINT16 Reserved; ///< Reserved + UINT8 DataSetting; ///< Data settings + UINT8 Handle; ///< Handle + UINT16 AliasDeviceId; ///< Alis device id + UINT8 Variety; ///< Variety +} IVHD_SPECIAL_ENTRY; + +/// IVRS IVMD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 AuxiliaryData; ///< Auxiliary data + UINT64 Reserved; ///< Reserved (0000_0000_0000_0000) + UINT64 BlockStart; ///< IVMD start address + UINT64 BlockLength; ///< IVMD memory block length +} IVRS_IVMD_ENTRY; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c new file mode 100644 index 0000000000..4606d3d1a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ + /** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Dispatch feature table + * + * + */ + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + CPU_LOGICAL_ID LogicalId; + + AgesaStatus = AGESA_SUCCESS; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + while (ConfigTable->GnbFeature != NULL) { + if ((ConfigTable->Type & LogicalId.Family) != 0) { + if (ConfigTable->TestPoint != 0) { + AGESA_TESTPOINT (ConfigTable->TestPoint, StdHeader); + } + Status = ConfigTable->GnbFeature (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + ConfigTable++; + } + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h new file mode 100644 index 0000000000..6d27c4b76b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBFEATURES_H_ +#define _GNBLIBFEATURES_H_ + + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h new file mode 100644 index 0000000000..87a8b357c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h @@ -0,0 +1,398 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe component definitions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** + +* +*/ + +#ifndef _GNBPCIE_H_ +#define _GNBPCIE_H_ + +#pragma pack (push, 1) + +#define MAX_NUMBER_OF_COMPLEXES 4 + +#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull +#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull +#define DESCRIPTOR_ALLOCATED 0x10000000ull +#define DESCRIPTOR_VIRTUAL 0x08000000ull +#define DESCRIPTOR_PLATFORM 0x04000000ull +#define DESCRIPTOR_COMPLEX 0x02000000ull +#define DESCRIPTOR_SILICON 0x01000000ull +#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull +#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull +#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull +#define DESCRIPTOR_DDI_ENGINE 0x00100000ull + +#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER) +#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) + +#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) + +#define UNUSED_LANE_ID 128 +//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) +//#define PCIE_LINK_L0_POOLING (60 * 1000) +//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) +//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) + +// Get lowest PHY lane on engine +#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0) +// Get highest PHY lane on engine +#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0) +// Get number of lanes on wrapper +#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) +// Check if virtual descriptor +#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE) +// Check if it is allocated descriptor +#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE) +// Check if it is last descriptor in list +#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE) +// Check if descriptor a PCIe engine +#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI engine +#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI wrapper +#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL) + +#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001ul +#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002ul +#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004ul +#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008ul +#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010ul +#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020ul +#define LANE_TYPE_PCIE_PHY 0x00000100ul +#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400ul +#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000ul +#define LANE_TYPE_DDI_PHY 0x00010000ul +#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000ul +#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000ul +#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000ul +#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL 0x00200000ul +#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL +#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL + +#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \ + LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \ + LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \ + LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \ + LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \ + LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) + +#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) + + +#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull +#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull +#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull +#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull +#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull +#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull +#define INIT_STATUS_DDI_ACTIVE 0x00000040ull +#define INIT_STATUS_ALLOCATED 0x00000080ull + +#define PCIE_PORT_GEN_CAP_BOOT 0x00000001ul +#define PCIE_PORT_GEN_CAP_MAX 0x00000002ul +#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010ul +#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000014ul +#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000018ul + +#define PCIE_POWERGATING_SKIP_CORE 0x00000001ul +#define PCIE_POWERGATING_SKIP_PHY 0x00000002ul + +/// PCIe Link Training State +typedef enum { + PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. + ///< PCIe device accessible after AmdEarlyInit complete + PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore + ///< PCIe device accessible after AmdPostInit complete. + ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. +} PCIE_TRAINING_ALGORITHM; + +/// PCIe Link Training State +typedef enum { + LinkStateResetAssert, ///< Assert port GPIO reset + LinkStateResetDuration, ///< Timeout for reset duration + LinkStateResetExit, ///< Deassert port GPIO reset + LinkTrainingResetTimeout, ///< Port GPIO reset timeout + LinkStateReleaseTraining, ///< Release link training + LinkStateDetectPresence, ///< Detect device presence + LinkStateDetecting, ///< Detect link training. + LinkStateBrokenLane, ///< Check and handle broken lane + LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised + LinkStateL0, ///< Device trained to L0 + LinkStateVcoNegotiation, ///< Check VCO negotiation complete + LinkStateRetrain, ///< Force retrain link. + LinkStateTrainingFail, ///< Link training fail + LinkStateTrainingSuccess, ///< Link training success + LinkStateGfxWorkaround, ///< GFX workaround + LinkStateCompliance, ///< Link in compliance mode + LinkStateDeviceNotPresent, ///< Link is not connected + LinkStateTrainingCompleted ///< Link training completed +} PCIE_LINK_TRAINING_STATE; + +/// PCIe Port Visibility +typedef enum { + UnhidePorts, ///< Command to unhide port + HidePorts, ///< Command to hide unused ports +} PCIE_PORT_VISIBILITY; + + +/// Table Register Entry +typedef struct { + UINT16 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_PORT_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_PORT_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_PORT_REGISTER_TABLE_HEADER; + +/// Table Register Entry +typedef struct { + UINT32 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_HOST_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_HOST_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_HOST_REGISTER_TABLE_HEADER; + +///Link ASPM info +typedef struct { + PCI_ADDR DownstreamPort; ///< PCI address of downstream port + PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm + PCI_ADDR UpstreamPort; ///< PCI address of upstream port + PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability + PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM + BOOLEAN BlackList; ///< Blacklist device +} PCIe_LINK_ASPM; + +///PCIe ASPM Latency Information +typedef struct { + UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us + UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us +} PCIe_ASPM_LATENCY_INFO; + +/// PCI address association +typedef struct { + UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion) + UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion) +} PCI_ADDR_LIST; + +/// The return status for GFX Card Workaround. +typedef enum { + GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready. + GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset. + GFX_WORKAROUND_SUCCESS ///< The service completed normally. +} GFX_WORKAROUND_STATUS; + +/// GFX workaround control +typedef enum { + GfxWorkaroundDisable, ///< GFX Workaround disabled + GfxWorkaroundEnable ///< GFX Workaround enabled +} GFX_WORKAROUND_CONTROL; + +/// PIF lane power state +typedef enum { + PifPowerStateL0, ///< + PifPowerStateLS1, ///< + PifPowerStateLS2, ///< + PifPowerStateOff = 0x7, ///< +} PCIE_PIF_POWER_STATE; + +/// PIF lane power control +typedef enum { + PowerDownPifs, ///< + PowerUpPifs ///< +} PCIE_PIF_POWER_CONTROL; + +///PLL rumup time +typedef enum { + NormalRampup, ///< + LongRampup, ///< +} PCIE_PLL_RAMPUP_TIME; + +typedef UINT16 PCIe_ENGINE_INIT_STATUS; + +/// PCIe port configuration info +typedef struct { + PCIe_PORT_DATA PortData; ///< Port data + UINT8 StartCoreLane; ///< Start Core Lane + UINT8 EndCoreLane; ///< End Core lane + UINT8 NativeDevNumber :5; ///< Native PCI device number of the port + UINT8 NativeFunNumber :3; ///< Native PCI function number of the port + UINT8 CoreId :4; ///< PCIe core ID + UINT8 PortId :4; ///< Port ID on wrapper + PCI_ADDR Address; ///< PCI address of the port + UINT8 State; ///< Training state + UINT8 PcieBridgeId:4; ///< IOC PCIe bridge ID + UINT16 UnitId:12; ///< Port start unit ID + UINT16 NumberOfUnitId:4; ///< Def number of unitIDs assigned to port + UINT8 GfxWrkRetryCount:4; ///< Number of retry for GFX workaround + UINT32 TimeStamp; ///< Time stamp used to during training process + UINT8 LogicalBridgeId; ///< Logical Bridge ID +} PCIe_PORT_CONFIG; + +///Descriptor header +typedef struct { + UINT32 DescriptorFlags; ///< Descriptor flags + UINT16 Parent; ///< Offset of parent descriptor + UINT16 Peer; ///< Offset of the peer descriptor + UINT16 Child; ///< Offset of the list of child descriptors +} PCIe_DESCRIPTOR_HEADER; + +/// DDI (Digital Display Interface) configuration info +typedef struct { + PCIe_DDI_DATA DdiData; ///< DDI Data + UINT8 DisplayPriorityIndex; ///< Display priority index + UINT8 ConnectorId; ///< Connector id determined by enumeration + UINT8 DisplayDeviceId; ///< Display device id determined by enumeration +} PCIe_DDI_CONFIG; + + +/// Engine configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor header + PCIe_ENGINE_DATA EngineData; ///< Engine Data + PCIe_ENGINE_INIT_STATUS InitStatus; ///< Initialization Status + UINT8 Scratch; ///< Scratch pad + union { + PCIe_PORT_CONFIG Port; ///< PCIe port configuration data + PCIe_DDI_CONFIG Ddi; ///< DDI configuration data + } Type; +} PCIe_ENGINE_CONFIG; + +/// Wrapper configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 WrapId; ///< Wrapper ID + UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper + UINT8 StartPhyLane; ///< Start PHY Lane + UINT8 EndPhyLane; ///< End PHY Lane + UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID + UINT8 EndPcieCoreId:4; ///< End PCIe Core ID + UINT8 NumberOfLanes; ///< Number of lanes + struct { + UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes + UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls + UINT8 ClkGating:1; ///< TXCLK gating + UINT8 LclkGating:1; ///< LCLK gating + UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down + UINT8 PllOffInL1:1; ///< PLL off in L1 + UINT8 AccessEncoding:1; ///< Reg access encoding + } Features; + UINT8 MasterPll; ///< Bitmap of master PLL +} PCIe_WRAPPER_CONFIG; + + +/// Silicon configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 SiliconId; ///< Gnb silicon(module) ID + UINT8 NodeId; ///< Node to which GNB connected + UINT8 LinkId; ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4 + PCI_ADDR Address; ///< PCI address of GNB host bridge +} PCIe_SILICON_CONFIG; + +typedef PCIe_SILICON_CONFIG GNB_HANDLE; + +/// Complex configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 SocketId; ///< Processor socket ID +} PCIe_COMPLEX_CONFIG; + +/// PCIe platform configuration info +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + PVOID StdHeader; ///< Standard configuration header + UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. + UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us + UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us + UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// + UINT8 GfxCardWorkaround; ///< GFX Card Workaround + UINT8 PsppPolicy; ///< PSPP policy + UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) + PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex +} PCIe_PLATFORM_CONFIG; + +/// PCIe Engine Description +typedef struct { + UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor on wrapper + * @li @b Bit30 - Descriptor allocated for PCIe port or DDI + */ + PCIe_ENGINE_DATA EngineData; ///< Engine Data +} PCIe_ENGINE_DESCRIPTOR; + +/// PCIe Lane allocation descriptor +typedef struct { + UINT32 Flags; ///< Flags + UINT8 WrapId; ///< Wrapper ID + UINT8 EngineType; ///< Engine Type + UINT8 NumberOfEngines; ///< Number of engines to configure + UINT8 NumberOfConfigurations; ///< Number of possible configurations + UINT8 *ConfigTable; ///< Pointer to config table +} PCIe_LANE_ALLOC_DESCRIPTOR; + +/// Lane Control +typedef enum { + EnableLanes, ///< Enable Lanes + DisableLanes ///< Disable Lanes +} LANE_CONTROL; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h new file mode 100644 index 0000000000..6ec63993d3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h @@ -0,0 +1,242 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEFAMSERVICES_H_ +#define _GNBPCIEFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" + +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef VOID F_PCIEFMSETLINKSPEEDCAP ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/// PCIe config services +typedef struct { + F_PCIEFMGETCOMPLEXDATALENGTH *PcieFmGetComplexDataLength; ///< PcieFmGetComplexDataLength + F_PCIEFMBUILDCOMPLEXCONFIGURATION *PcieFmBuildComplexConfiguration; ///< PcieFmBuildComplexConfiguration + F_PCIEFMCONFIGUREENGINESLANEALLOCATION *PcieFmConfigureEnginesLaneAllocation; ///< PcieFmConfigureEnginesLaneAllocation + F_PCIEFMCHECKPORTPCIDEVICEMAPPING *PcieFmCheckPortPciDeviceMapping; ///< PcieFmCheckPortPciDeviceMapping + F_PCIEFMMAPPORTPCIADDRESS *PcieFmMapPortPciAddress; ///< PcieFmMapPortPciAddress + F_PCIEFMCHECKPORTPCIELANECANBEMUXED *PcieFmCheckPortPcieLaneCanBeMuxed; ///< PcieFmCheckPortPcieLaneCanBeMuxed + F_PCIEFMGETSBCONFIGINFO *PcieFmGetSbConfigInfo; ///< PcieFmGetSbConfigInfo +} PCIe_FAM_CONFIG_SERVICES; + +/// PCIe init services +typedef struct { + F_PCIEFMGETCORECONFIGURATIONVALUE *PcieFmGetCoreConfigurationValue; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMGETLINKSPEEDCAP *PcieFmGetLinkSpeedCap; ///< PcieFmGetLinkSpeedCap + F_PCIEFMGETNATIVEPHYLANEBITMAP *PcieFmGetNativePhyLaneBitmap; ///< PcieFmGetNativePhyLaneBitmap + F_PCIEFMSETLINKSPEEDCAP *PcieFmSetLinkSpeedCap; ///< PcieFmSetLinkSpeedCap +} PCIe_FAM_INIT_SERVICES; + +///PCIe debug services +typedef struct { + F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMDEBUGGETWRAPPERNAMESTRING *PcieFmDebugGetWrapperNameString; ///< PcieFmDebugGetWrapperNameString + F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING *PcieFmDebugGetCoreConfigurationString; ///< PcieFmDebugGetCoreConfigurationString +} PCIe_FAM_DEBUG_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h new file mode 100644 index 0000000000..b67058f291 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h @@ -0,0 +1,1557 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERSCOMMON_H_ +#define _GNBREGISTERSCOMMON_H_ + + +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xE4 0x5 +#define TYPE_DxF0 0x6 +#define TYPE_DxF0xE4 0x7 +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define D18F2x9C 0xe +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +// **** D0F0x00 Register Definition **** +// Address +#define D0F0x00_ADDRESS 0x0 + +// Type +#define D0F0x00_TYPE TYPE_D0F0 +// Field Data +#define D0F0x00_VendorID_OFFSET 0 +#define D0F0x00_VendorID_WIDTH 16 +#define D0F0x00_VendorID_MASK 0xffff +#define D0F0x00_DeviceID_OFFSET 16 +#define D0F0x00_DeviceID_WIDTH 16 +#define D0F0x00_DeviceID_MASK 0xffff0000 + +/// D0F0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x00_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 + +// Type +#define D0F0x04_TYPE TYPE_D0F0 +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_7_7_OFFSET 7 +#define D0F0x04_Reserved_7_7_WIDTH 1 +#define D0F0x04_Reserved_7_7_MASK 0x80 +#define D0F0x04_Reserved_19_10_OFFSET 10 +#define D0F0x04_Reserved_19_10_WIDTH 10 +#define D0F0x04_Reserved_19_10_MASK 0xffc00 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_19_10:10; ///< + UINT32 CapList:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x04_STRUCT; + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 + +// Type +#define D0F0x64_TYPE TYPE_D0F0 +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xffffffff + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_STRUCT; + + + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// Type +#define D0F0x90_TYPE TYPE_D0F0 +// Field Data +#define D0F0x90_Reserved_22_0_OFFSET 0 +#define D0F0x90_Reserved_22_0_WIDTH 23 +#define D0F0x90_Reserved_22_0_MASK 0x7fffff +#define D0F0x90_TopOfDram_OFFSET 23 +#define D0F0x90_TopOfDram_WIDTH 9 +#define D0F0x90_TopOfDram_MASK 0xff800000 + +/// D0F0x90 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 TopOfDram:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x90_STRUCT; + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xe0 + +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE0_PcieIndxAddr_OFFSET 0 +#define D0F0xE0_PcieIndxAddr_WIDTH 16 +#define D0F0xE0_PcieIndxAddr_MASK 0xffff +#define D0F0xE0_FrameType_OFFSET 16 +#define D0F0xE0_FrameType_WIDTH 8 +#define D0F0xE0_FrameType_MASK 0xff0000 +#define D0F0xE0_BlockSelect_OFFSET 24 +#define D0F0xE0_BlockSelect_WIDTH 8 +#define D0F0xE0_BlockSelect_MASK 0xff000000 + +/// D0F0xE0 +typedef union { + struct { ///< + UINT32 PcieIndxAddr:16; ///< + UINT32 FrameType:8 ; ///< + UINT32 BlockSelect:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE0_STRUCT; + + +// **** D18F3x15C Register Definition **** +// Address +#define D18F3x15C_ADDRESS 0x15c + +// Type +#define D18F3x15C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x15C_SclkVidLevel0_OFFSET 0 +#define D18F3x15C_SclkVidLevel0_WIDTH 7 +#define D18F3x15C_SclkVidLevel0_MASK 0x7f +#define D18F3x15C_Reserved_7_7_OFFSET 7 +#define D18F3x15C_Reserved_7_7_WIDTH 1 +#define D18F3x15C_Reserved_7_7_MASK 0x80 +#define D18F3x15C_SclkVidLevel1_OFFSET 8 +#define D18F3x15C_SclkVidLevel1_WIDTH 7 +#define D18F3x15C_SclkVidLevel1_MASK 0x7f00 +#define D18F3x15C_Reserved_15_15_OFFSET 15 +#define D18F3x15C_Reserved_15_15_WIDTH 1 +#define D18F3x15C_Reserved_15_15_MASK 0x8000 +#define D18F3x15C_SclkVidLevel2_OFFSET 16 +#define D18F3x15C_SclkVidLevel2_WIDTH 7 +#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000 +#define D18F3x15C_Reserved_23_23_OFFSET 23 +#define D18F3x15C_Reserved_23_23_WIDTH 1 +#define D18F3x15C_Reserved_23_23_MASK 0x800000 +#define D18F3x15C_SclkVidLevel3_OFFSET 24 +#define D18F3x15C_SclkVidLevel3_WIDTH 7 +#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000 +#define D18F3x15C_Reserved_31_31_OFFSET 31 +#define D18F3x15C_Reserved_31_31_WIDTH 1 +#define D18F3x15C_Reserved_31_31_MASK 0x80000000 + +/// D18F3x15C +typedef union { + struct { ///< + UINT32 SclkVidLevel0:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SclkVidLevel1:7 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 SclkVidLevel2:7 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 SclkVidLevel3:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x15C_STRUCT; + +// **** D18F3x17C Register Definition **** + + + +// **** DxF0x18 Register Definition **** +// Address +#define DxF0x18_ADDRESS 0x18 + +// Type +#define DxF0x18_TYPE TYPE_D4F0 +// **** DxF0x58 Register Definition **** +// Address + + + + +// **** D0F0x64_x0C Register Definition **** +// Address +#define D0F0x64_x0C_ADDRESS 0xc + +// Type +#define D0F0x64_x0C_TYPE TYPE_D0F0x64 + +/// D0F0x64_x0C +typedef union { + UINT32 Value; ///< +} D0F0x64_x0C_STRUCT; + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x19_TomEn_OFFSET 0 +#define D0F0x64_x19_TomEn_WIDTH 1 +#define D0F0x64_x19_TomEn_MASK 0x1 +#define D0F0x64_x19_Reserved_22_1_OFFSET 1 +#define D0F0x64_x19_Reserved_22_1_WIDTH 22 +#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe +#define D0F0x64_x19_Tom2_31_23__OFFSET 23 +#define D0F0x64_x19_Tom2_31_23__WIDTH 9 +#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 + +/// D0F0x64_x19 +typedef union { + struct { ///< + UINT32 TomEn:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 Tom2_31_23_:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x19_STRUCT; + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 +#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 +#define D0F0x64_x1A_Tom2_39_32__MASK 0xff +#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 +#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 +#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x1A +typedef union { + struct { ///< + UINT32 Tom2_39_32_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1A_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1d + +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1D_STRUCT; + + +// **** D0F0x64_x6A Register Definition **** +// Address +#define D0F0x64_x6A_ADDRESS 0x6a + +// Type +#define D0F0x64_x6A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x6A_VoltageForceEn_OFFSET 0 +#define D0F0x64_x6A_VoltageForceEn_WIDTH 1 +#define D0F0x64_x6A_VoltageForceEn_MASK 0x1 +#define D0F0x64_x6A_VoltageChangeEn_OFFSET 1 +#define D0F0x64_x6A_VoltageChangeEn_WIDTH 1 +#define D0F0x64_x6A_VoltageChangeEn_MASK 0x2 +#define D0F0x64_x6A_VoltageChangeReq_OFFSET 2 +#define D0F0x64_x6A_VoltageChangeReq_WIDTH 1 +#define D0F0x64_x6A_VoltageChangeReq_MASK 0x4 +#define D0F0x64_x6A_VoltageLevel_OFFSET 3 +#define D0F0x64_x6A_VoltageLevel_WIDTH 2 +#define D0F0x64_x6A_VoltageLevel_MASK 0x18 +#define D0F0x64_x6A_Reserved_31_5_OFFSET 5 +#define D0F0x64_x6A_Reserved_31_5_WIDTH 27 +#define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0 + +/// D0F0x64_x6A +typedef union { + struct { ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 VoltageLevel:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x6A_STRUCT; + +// **** D0F0x64_x6B Register Definition **** +// Address +#define D0F0x64_x6B_ADDRESS 0x6b + +// Type +#define D0F0x64_x6B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x6B_VoltageChangeAck_OFFSET 0 +#define D0F0x64_x6B_VoltageChangeAck_WIDTH 1 +#define D0F0x64_x6B_VoltageChangeAck_MASK 0x1 +#define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1 +#define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2 +#define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6 +#define D0F0x64_x6B_Reserved_31_3_OFFSET 3 +#define D0F0x64_x6B_Reserved_31_3_WIDTH 29 +#define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8 + +/// D0F0x64_x6B +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:2 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x6B_STRUCT; + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +// Type +#define D0F0x98_x06_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x06_Reserved_25_0_OFFSET 0 +#define D0F0x98_x06_Reserved_25_0_WIDTH 26 +#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 +#define D0F0x98_x06_Reserved_31_27_OFFSET 27 +#define D0F0x98_x06_Reserved_31_27_WIDTH 5 +#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x98_x06 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 UmiNpMemWrEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x06_STRUCT; + + +// **** D0F0x98_x2C Register Definition **** +// Address +#define D0F0x98_x2C_ADDRESS 0x2c + +// Type +#define D0F0x98_x2C_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 +#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 +#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 +#define D0F0x98_x2C_DynWakeEn_OFFSET 1 +#define D0F0x98_x2C_DynWakeEn_WIDTH 1 +#define D0F0x98_x2C_DynWakeEn_MASK 0x2 +#define D0F0x98_x2C_Reserved_15_2_OFFSET 2 +#define D0F0x98_x2C_Reserved_15_2_WIDTH 14 +#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc +#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 +#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 +#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 DynWakeEn:1 ; ///< + UINT32 Reserved_15_2:14; ///< + UINT32 WakeHysteresis:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x2C_STRUCT; + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3a + +// Type + + +// **** D0F0xE4_WRAP_0080 Register Definition **** +// Address +#define D0F0xE4_WRAP_0080_ADDRESS 0x80 + +// Type +#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf +#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 +#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 +#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_WRAP_0080 +typedef union { + struct { ///< + UINT32 StrapBifLinkConfig:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0080_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 + +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0800_STRUCT; + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +// **** D0F0xE4_WRAP_0903 Register Definition **** +// Address +#define D0F0xE4_WRAP_0903_ADDRESS 0x903 + +// Type +#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0903 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0903_STRUCT; + + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 + +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 Reserved_30_25:6 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Reserved_21_16:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_24_29:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 + +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 +// Field Data + +// **** D0F0xE4_WRAP_8023 Register Definition **** +// Address +#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 + +// Type +#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 +/// D0F0xE4_WRAP_8023 +typedef union { + UINT32 Value; ///< +} D0F0xE4_WRAP_8023_STRUCT; + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 + +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 +/// D0F0xE4_WRAP_8025 +typedef union { + UINT32 Value; ///< +} D0F0xE4_WRAP_8025_STRUCT; + + +// **** D0F0xE4_WRAP_8040 Register Definition **** +// Address +#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 + +// Type +#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 + + +// **** D0F0xE4_WRAP_8060 Register Definition **** +// Address +#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 + +// Type +#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 +#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xE4_WRAP_8060 +typedef union { + struct { ///< + UINT32 Reconfigure:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetComplete:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BifGlobalReset:1 ; ///< + UINT32 BifCalibrationReset:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8060_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000 +#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 +#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 EiCycleOffTime:3 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 +#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 +#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 +#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 +#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 b12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 Reserved_24_17:8 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_PIF_0013 Register Definition **** +// Address +#define D0F0xE4_PIF_0013_ADDRESS 0x13 + +// Type +#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0013 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0013_STRUCT; + + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf +#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 +#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 +#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_CORE_0011 +typedef union { + struct { ///< + UINT32 DynClkLatency:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0011_STRUCT; + + + + + + + + +// **** DxF0xE4_x70 Register Definition **** +// Address + + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 +#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 +#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 +#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1 ; ///< + UINT32 MasterPciePllB:1 ; ///< + UINT32 MasterPciePllC:1 ; ///< + UINT32 MasterPciePllD:1 ; ///< + UINT32 ClkDividerResetOverrideA:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxclkSelCoreOverride:1 ; ///< + UINT32 TxclkSelPifAOverride:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 +#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 +#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 +#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 +#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 +#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 +#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0x64_x51 Register Definition **** +// Address +#define D0F0x64_x51_ADDRESS 0x51 + +// Type +#define D0F0x64_x51_TYPE TYPE_D0F0x64 + + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET 1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH 3 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK 0xe +#define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET 4 +#define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH 3 +#define D0F0xE4_CORE_0010_Reserved_6_4_MASK 0x70 +#define D0F0xE4_CORE_0010_Reserved_8_8_OFFSET 8 +#define D0F0xE4_CORE_0010_Reserved_8_8_WIDTH 1 +#define D0F0xE4_CORE_0010_Reserved_8_8_MASK 0x100 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_15_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_15_13_WIDTH 3 +#define D0F0xE4_CORE_0010_Reserved_15_13_MASK 0xe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 LcHotPlugDelSel:3 ; ///< + UINT32 Reserved_6_4:3 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxUmiAdjPayloadSize:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :6 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + + +typedef union { + struct { ///< + UINT32 bit_0_0:1 ; ///< + UINT32 bit1:1 ; ///< + UINT32 bit2:1 ; ///< + UINT32 bit3:1 ; ///< + UINT32 bit4:1 ; ///< + UINT32 bit5:1 ; ///< + UINT32 bit6:1 ; ///< + UINT32 bit_7_7:1 ; ///< + UINT32 bit_9_8:2 ; ///< + UINT32 bit_10_10:1 ; ///< + UINT32 bit11:1 ; ///< + UINT32 bit12:1 ; ///< + UINT32 bit13:1 ; ///< + UINT32 bit14:1 ; ///< + UINT32 bit15:1 ; ///< + UINT32 bit16:1 ; ///< + UINT32 bit_17_17:1 ; ///< + UINT32 bit_19_18:2 ; ///< + UINT32 bit20:1 ; ///< + UINT32 bit_21_21:1 ; ///< + UINT32 bit_23_22:2 ; ///< + UINT32 bit24:1 ; ///< + UINT32 bit_25_25:1 ; ///< + UINT32 bit_27_26:2 ; ///< + UINT32 bit_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GNBREGCOMMON_STR1_STRUCT; + + + + +// **** D0F0xE4_PHY_6006 Register Definition **** +// Address +#define D0F0xE4_PHY_6006_ADDRESS 0x6006 + +// Type +#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 +#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 +#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff +#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET 16 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK 0xff0000 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET 24 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK 0xff000000 + +/// D0F0xE4_PHY_6006 +typedef union { + struct { ///< + UINT32 TxMarginNom:8 ; ///< + UINT32 DeemphGen1Nom:8 ; ///< + UINT32 Deemph35Gen2Nom:8 ; ///< + UINT32 Deemph60Gen2Nom:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6006_STRUCT; + +// **** GMMx00 Register Definition **** +// Address +#define GMMx00_ADDRESS 0x0 + +// Type +#define GMMx00_TYPE TYPE_GMM +// Field Data +#define GMMx00_Offset_OFFSET 0 +#define GMMx00_Offset_WIDTH 31 +#define GMMx00_Offset_MASK 0x7fffffff +#define GMMx00_Aper_OFFSET 31 +#define GMMx00_Aper_WIDTH 1 +#define GMMx00_Aper_MASK 0x80000000 + +/// GMMx00 +typedef union { + struct { ///< + UINT32 Offset:31; ///< + UINT32 Aper:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx00_STRUCT; + +// **** GMMx04 Register Definition **** +// Address +#define GMMx04_ADDRESS 0x4 + +// Type +#define GMMx04_TYPE TYPE_GMM +// Field Data +#define GMMx04_Data_OFFSET 0 +#define GMMx04_Data_WIDTH 32 +#define GMMx04_Data_MASK 0xffffffff + +/// GMMx04 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx04_STRUCT; + + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f +#define D0F0xE4_WRAP_8016_Reserved_7_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_7_6_WIDTH 2 +#define D0F0xE4_WRAP_8016_Reserved_7_6_MASK 0xc0 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_OFFSET 8 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_WIDTH 1 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_MASK 0x100 +#define D0F0xE4_WRAP_8016_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8016_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8016_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8016_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8016_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8016_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_OFFSET 12 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_WIDTH 1 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_MASK 0x1000 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_OFFSET 13 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_WIDTH 1 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_MASK 0x2000 +#define D0F0xE4_WRAP_8016_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8016_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8016_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CalibDoneSelPifA:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Gen1OnlyEngage:1 ; ///< + UINT32 Gen1OnlyEngaged:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h new file mode 100644 index 0000000000..4458039349 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h @@ -0,0 +1,1445 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87271 $ @e \$Date: 2013-01-31 10:11:23 -0600 (Thu, 31 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERS_CV2_H_ +#define _GNBREGISTERS_CV2_H_ + +#define SMC_MSG_FIRMWARE_AUTH 0 + +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif + +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif + +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + + +// **** D0F0xFC_x01 Register Definition **** +// Address +#define D0F0xFC_x01_ADDRESS 0x01 + +// **** D0F0xFC_x02 Register Definition **** +// Address +#define D0F0xFC_x02_ADDRESS 0x02 + +// **** D0F0xFC_x10 Register Definition **** +// Address +#define D0F0xFC_x10_ADDRESS 0x10 +// Type +#define D0F0xFC_x10_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x10_BrExtIntrGrp_OFFSET 0 +#define D0F0xFC_x10_BrExtIntrGrp_WIDTH 3 +#define D0F0xFC_x10_BrExtIntrGrp_MASK 0x7 +#define D0F0xFC_x10_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x10_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x10_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x10_BrExtIntrSwz_OFFSET 4 +#define D0F0xFC_x10_BrExtIntrSwz_WIDTH 2 +#define D0F0xFC_x10_BrExtIntrSwz_MASK 0x30 +#define D0F0xFC_x10_Reserved_15_6_OFFSET 6 +#define D0F0xFC_x10_Reserved_15_6_WIDTH 10 +#define D0F0xFC_x10_Reserved_15_6_MASK 0xFFC0 +#define D0F0xFC_x10_BrIntIntrMap_OFFSET 16 +#define D0F0xFC_x10_BrIntIntrMap_WIDTH 5 +#define D0F0xFC_x10_BrIntIntrMap_MASK 0x1F0000 +#define D0F0xFC_x10_Reserved_31_21_OFFSET 21 +#define D0F0xFC_x10_Reserved_31_21_WIDTH 11 +#define D0F0xFC_x10_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0xFC_x10 +typedef union { + struct { ///< + UINT32 BrExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 BrExtIntrSwz:2; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 BrIntIntrMap:5; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x10_STRUCT; + +// **** D0F0xB8 Register Definition **** +// Address +#define D0F0xB8_ADDRESS 0xb8 + +// **** DxF0xE4_xC1 Register Definition **** +// Address +#define D2FxxE4_xC1_ADDRESS 0xc1 + +// Type +#define D2FxxE4_xC1_TYPE TYPE_D4F0xE4 +// Field Data + +#define D2FxxE4_xC1_StrapReverseLanes_OFFSET 0 +#define D2FxxE4_xC1_StrapReverseLanes_WIDTH 1 +#define D2FxxE4_xC1_StrapReverseLanes_MASK 0x1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_OFFSET 1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_WIDTH 1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_MASK 0x2 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_OFFSET 2 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_WIDTH 1 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_MASK 0x4 +#define D2FxxE4_xC1_Reserved_31_3_OFFSET 3 +#define D2FxxE4_xC1_Reserved_31_3_WIDTH 29 +#define D2FxxE4_xC1_Reserved_31_3_MASK 0xfffffff8 + +// Type +// Address +#define D0F0xE4_WRAP_0046_ADDRESS 0x46 + +// Address +#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 + + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + + +// Type +#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET 0 +#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH 1 +#define D0F0xE4_WRAP_8040_OwnSlice_MASK 0x1 + + +// **** D0F0xBC_x1F630 Register Definition **** +// Address +#define D0F0xBC_x1F630_ADDRESS 0x1f630 + +// Type +#define D0F0xBC_x1F630_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK 0x00ff00 + + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xFC00 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7E0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_WRAP_8011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6; ///< + UINT32 TxclkPermGateEven:1; ///< + UINT32 TxclkDynGateEnable:1; ///< + UINT32 TxclkPermStop:1; ///< + UINT32 TxclkRegsGateEnable:1; ///< + UINT32 TxclkRegsGateLatency:6; ///< + UINT32 Bitfield_16_16:1; ///< + UINT32 TxclkPermGateLatency:6; ///< + UINT32 Reserved_23_23:1; ///< + UINT32 TxclkLcntGateEnable:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8011_STRUCT; + + + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 + +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf + + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 +#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 :3 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D2FxxE4_xA4 Register Definition **** +// Address +#define D2FxxE4_xA4_ADDRESS 0xa4 + +// Type +#define D2FxxE4_xA4_TYPE TYPE_D4F0xE4 +// Field Data +#define D2FxxE4_xA4_LcGen2EnStrap_OFFSET 0 +#define D2FxxE4_xA4_LcGen2EnStrap_WIDTH 1 +#define D2FxxE4_xA4_LcGen2EnStrap_MASK 0x1 +#define D2FxxE4_xA4_Reserved_5_1_OFFSET 1 +#define D2FxxE4_xA4_Reserved_5_1_WIDTH 5 +#define D2FxxE4_xA4_Reserved_5_1_MASK 0x3e +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_OFFSET 6 +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_MASK 0x40 +#define D2FxxE4_xA4_Reserved_8_7_OFFSET 7 +#define D2FxxE4_xA4_Reserved_8_7_WIDTH 2 +#define D2FxxE4_xA4_Reserved_8_7_MASK 0x180 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_OFFSET 9 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_MASK 0x200 +#define D2FxxE4_xA4_Reserved_11_10_OFFSET 10 +#define D2FxxE4_xA4_Reserved_11_10_WIDTH 2 +#define D2FxxE4_xA4_Reserved_11_10_MASK 0xc00 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 12 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x1000 +#define D2FxxE4_xA4_Reserved_18_13_OFFSET 13 +#define D2FxxE4_xA4_Reserved_18_13_WIDTH 6 +#define D2FxxE4_xA4_Reserved_18_13_MASK 0x7e000 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_OFFSET 19 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_MASK 0x80000 +#define D2FxxE4_xA4_Reserved_26_20_OFFSET 20 +#define D2FxxE4_xA4_Reserved_26_20_WIDTH 7 +#define D2FxxE4_xA4_Reserved_26_20_MASK 0x7f00000 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 27 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x8000000 +#define D2FxxE4_xA4_Reserved_31_28_OFFSET 28 +#define D2FxxE4_xA4_Reserved_31_28_WIDTH 4 +#define D2FxxE4_xA4_Reserved_31_28_MASK 0xf0000000 + +/// D2FxxE4_xA4 +typedef union { + struct { ///< + UINT32 LcGen2EnStrap:1 ; ///< + UINT32 Reserved_5_1:5 ; ///< + UINT32 LcForceDisSwSpeedChange:1 ; ///< + UINT32 Reserved_8_7:2 ; ///< + UINT32 LcInitiateLinkSpeedChange:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 LcSpeedChangeAttemptFailed:1 ; ///< + UINT32 Reserved_18_13:6 ; ///< + UINT32 LcOtherSideSupportsGen2:1 ; ///< + UINT32 Reserved_26_20:7 ; ///< + UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D2FxxE4_xA4_STRUCT; + + +// **** D2FxxE4_xC0 Register Definition **** +// Address +#define D2FxxE4_xC0_ADDRESS 0xc0 + +// Type +#define D2FxxE4_xC0_TYPE TYPE_D4F0xE4 +// Field Data +#define D2FxxE4_xC0_Reserved_12_0_OFFSET 0 +#define D2FxxE4_xC0_Reserved_12_0_WIDTH 13 +#define D2FxxE4_xC0_Reserved_12_0_MASK 0x1fff +#define D2FxxE4_xC0_StrapForceCompliance_OFFSET 13 +#define D2FxxE4_xC0_StrapForceCompliance_WIDTH 1 +#define D2FxxE4_xC0_StrapForceCompliance_MASK 0x2000 +#define D2FxxE4_xC0_Reserved_14_14_OFFSET 14 +#define D2FxxE4_xC0_Reserved_14_14_WIDTH 1 +#define D2FxxE4_xC0_Reserved_14_14_MASK 0x4000 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define D2FxxE4_xC0_Reserved_31_16_OFFSET 16 +#define D2FxxE4_xC0_Reserved_31_16_WIDTH 16 +#define D2FxxE4_xC0_Reserved_31_16_MASK 0xffff0000 + +/// D2FxxE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D2FxxE4_xC0_STRUCT; + + +// **** D2Fxx88 Register Definition **** +// Address +#define D2Fxx88_ADDRESS 0x88 + +// Type +#define D2Fxx88_TYPE TYPE_D4F0 +// Field Data +#define D2Fxx88_TargetLinkSpeed_OFFSET 0 +#define D2Fxx88_TargetLinkSpeed_WIDTH 4 +#define D2Fxx88_TargetLinkSpeed_MASK 0xf +#define D2Fxx88_EnterCompliance_OFFSET 4 +#define D2Fxx88_EnterCompliance_WIDTH 1 +#define D2Fxx88_EnterCompliance_MASK 0x10 +#define D2Fxx88_HwAutonomousSpeedDisable_OFFSET 5 +#define D2Fxx88_HwAutonomousSpeedDisable_WIDTH 1 +#define D2Fxx88_HwAutonomousSpeedDisable_MASK 0x20 +#define D2Fxx88_SelectableDeemphasis_OFFSET 6 +#define D2Fxx88_SelectableDeemphasis_WIDTH 1 +#define D2Fxx88_SelectableDeemphasis_MASK 0x40 +#define D2Fxx88_XmitMargin_OFFSET 7 +#define D2Fxx88_XmitMargin_WIDTH 3 +#define D2Fxx88_XmitMargin_MASK 0x380 +#define D2Fxx88_EnterModCompliance_OFFSET 10 +#define D2Fxx88_EnterModCompliance_WIDTH 1 +#define D2Fxx88_EnterModCompliance_MASK 0x400 +#define D2Fxx88_ComplianceSOS_OFFSET 11 +#define D2Fxx88_ComplianceSOS_WIDTH 1 +#define D2Fxx88_ComplianceSOS_MASK 0x800 +#define D2Fxx88_ComplianceDeemphasis_OFFSET 12 +#define D2Fxx88_ComplianceDeemphasis_WIDTH 1 +#define D2Fxx88_ComplianceDeemphasis_MASK 0x1000 +#define D2Fxx88_Reserved_15_13_OFFSET 13 +#define D2Fxx88_Reserved_15_13_WIDTH 3 +#define D2Fxx88_Reserved_15_13_MASK 0xe000 +#define D2Fxx88_CurDeemphasisLevel_OFFSET 16 +#define D2Fxx88_CurDeemphasisLevel_WIDTH 1 +#define D2Fxx88_CurDeemphasisLevel_MASK 0x10000 +#define D2Fxx88_Reserved_31_17_OFFSET 17 +#define D2Fxx88_Reserved_31_17_WIDTH 15 +#define D2Fxx88_Reserved_31_17_MASK 0xfffe0000 + +/// D2Fxx88 +typedef union { + struct { ///< + UINT32 TargetLinkSpeed:4 ; ///< + UINT32 EnterCompliance:1 ; ///< + UINT32 HwAutonomousSpeedDisable:1 ; ///< + UINT32 SelectableDeemphasis:1 ; ///< + UINT32 XmitMargin:3 ; ///< + UINT32 EnterModCompliance:1 ; ///< + UINT32 ComplianceSOS:1 ; ///< + UINT32 ComplianceDeemphasis:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 CurDeemphasisLevel:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D2Fxx88_STRUCT; + + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +/* + * Needed by GnbNbInitLibV4.c + */ + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + + + + + +/// D0F0xBC_x80010000 +typedef union { +UINT32 Value; ///< +} GRC1_STRUCT; + + + + + + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_8_1:8 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxSbAdjPayloadSize:3 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3a + + +// **** D18F0x110 Register Definition **** +// Address +#define D18F0x110_ADDRESS 0x110 + + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 + +/* + * Needed by GnbNbInitLibV4.c - end + */ + +/* + * Needed by GnbIommuScratch.c + */ + + + + +/* + * Needed by GnbIommuScratch.c - end + */ + +/* + * Needed by GnbIoapic.c + */ + + +// **** D0F0xF8 Register Definition **** +// Address +#define D0F0xF8_ADDRESS 0xf8 + +// **** D0F0xFC_x00 Register Definition **** +// Address +#define D0F0xFC_x00_ADDRESS 0x0 + +// Type +#define D0F0xFC_x00_TYPE TYPE_D0F0xFC +// Field Data +#define D0F0xFC_x00_IoapicEnable_OFFSET 0 +#define D0F0xFC_x00_IoapicEnable_WIDTH 1 +#define D0F0xFC_x00_IoapicEnable_MASK 0x01 +#define D0F0xFC_x00_Reserved_1_1_OFFSET 2 +#define D0F0xFC_x00_Reserved_1_1_WIDTH 1 +#define D0F0xFC_x00_Reserved_1_1_MASK 0x02 +#define D0F0xFC_x00_IoapicIdExtEn_OFFSET 3 +#define D0F0xFC_x00_IoapicIdExtEn_WIDTH 1 +#define D0F0xFC_x00_IoapicIdExtEn_MASK 0x04 +#define D0F0xFC_x00_Reserved_3_3_OFFSET 4 +#define D0F0xFC_x00_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x00_Reserved_3_3_MASK 0x08 +#define D0F0xFC_x00_IoapicSbFeatureEn_OFFSET 4 +#define D0F0xFC_x00_IoapicSbFeatureEn_WIDTH 1 +#define D0F0xFC_x00_IoapicSbFeatureEn_MASK 0x10 +#define D0F0xFC_x00_Reserved_31_5_OFFSET 5 +#define D0F0xFC_x00_Reserved_31_5_WIDTH 27 +#define D0F0xFC_x00_Reserved_31_5_MASK 0xffffffe0 + +/// D0F0xFC_x00 +typedef union { + struct { ///< + UINT32 IoapicEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 IoapicIdExtEn:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 IoapicSbFeatureEn:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xFC_x00_STRUCT; + +/* + * Needed by GnbIoapic.c - end + */ + +/* + * Needed by GnbPcieInitLibV5 + */ + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + + +// **** D0F0xCC_x01 Register Definition **** +// Address +#define D0F0xCC_x01_ADDRESS 0x1 + +// Type +#define D0F0xCC_x01_TYPE TYPE_D0F0xCC +// Field Data +#define D0F0xCC_x01_BridgeDis_OFFSET 0 +#define D0F0xCC_x01_BridgeDis_WIDTH 1 +#define D0F0xCC_x01_BridgeDis_MASK 0x1 +#define D0F0xCC_x01_Reserved_1_1_OFFSET 1 +#define D0F0xCC_x01_Reserved_1_1_WIDTH 1 +#define D0F0xCC_x01_Reserved_1_1_MASK 0x2 +#define D0F0xCC_x01_CfgDis_OFFSET 2 +#define D0F0xCC_x01_CfgDis_WIDTH 1 +#define D0F0xCC_x01_CfgDis_MASK 0x4 +#define D0F0xCC_x01_P2pDis_OFFSET 3 +#define D0F0xCC_x01_P2pDis_WIDTH 1 +#define D0F0xCC_x01_P2pDis_MASK 0x8 +#define D0F0xCC_x01_Reserved_15_4_OFFSET 4 +#define D0F0xCC_x01_Reserved_15_4_WIDTH 12 +#define D0F0xCC_x01_Reserved_15_4_MASK 0xfff0 +#define D0F0xCC_x01_ExtDevPlug_OFFSET 16 +#define D0F0xCC_x01_ExtDevPlug_WIDTH 1 +#define D0F0xCC_x01_ExtDevPlug_MASK 0x10000 +#define D0F0xCC_x01_ExtDevCsrEn_OFFSET 17 +#define D0F0xCC_x01_ExtDevCsrEn_WIDTH 1 +#define D0F0xCC_x01_ExtDevCsrEn_MASK 0x20000 +#define D0F0xCC_x01_CsrEnable_OFFSET 18 +#define D0F0xCC_x01_CsrEnable_WIDTH 1 +#define D0F0xCC_x01_CsrEnable_MASK 0x40000 +#define D0F0xCC_x01_SetPowEn_OFFSET 20 +#define D0F0xCC_x01_SetPowEn_WIDTH 1 +#define D0F0xCC_x01_SetPowEn_MASK 0x100000 +#define D0F0xCC_x01_Reserved_22_21_OFFSET 21 +#define D0F0xCC_x01_Reserved_22_21_WIDTH 2 +#define D0F0xCC_x01_Reserved_22_21_MASK 0x600000 +#define D0F0xCC_x01_ApicEnable_OFFSET 23 +#define D0F0xCC_x01_ApicEnable_WIDTH 1 +#define D0F0xCC_x01_ApicEnable_MASK 0x800000 +#define D0F0xCC_x01_ApicRange_OFFSET 24 +#define D0F0xCC_x01_ApicRange_WIDTH 8 +#define D0F0xCC_x01_ApicRange_MASK 0xff000000 + +/// D0F0xCC_x1 +typedef union { + struct { ///< + UINT32 BridgeDis:1 ; ///< + UINT32 Reserved_1_1:2 ; ///< + UINT32 CfgDis:1 ; ///< + UINT32 P2pDis:1 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 ExtDevPlug:1 ; ///< + UINT32 ExtDevCsrEn:1 ; ///< + UINT32 CsrEnable:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_22_21:2 ; ///< + UINT32 ApicEnable:1 ; ///< + UINT32 ApicRange:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xCC_x01_STRUCT; + + +// **** D0F0xC8 Register Definition **** +// Address +#define D0F0xC8_ADDRESS 0xc8 + +// Type +#define D0F0xC8_TYPE TYPE_D0F0 +// Field Data +#define D0F0xC8_NB_DEV_IND_ADDR_OFFSET 0 +#define D0F0xC8_NB_DEV_IND_ADDR_WIDTH 7 +#define D0F0xC8_NB_DEV_IND_ADDR_MASK 0x7F +#define D0F0xC8_Reserved_15_7_OFFSET 7 +#define D0F0xC8_Reserved_15_7_WIDTH 9 +#define D0F0xC8_Reserved_15_7_MASK 0xFF80 +#define D0F0xC8_NB_DEV_IND_SEL_OFFSET 16 +#define D0F0xC8_NB_DEV_IND_SEL_WIDTH 8 +#define D0F0xC8_NB_DEV_IND_SEL_MASK 0xFF0000 +#define D0F0xC8_Reserved_31_24_OFFSET 24 +#define D0F0xC8_Reserved_31_24_WIDTH 8 +#define D0F0xC8_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xC8 +typedef union { + struct { ///< + UINT32 NB_DEV_IND_ADDR:7; ///< + UINT32 Reserved_15_7:9; ///< + UINT32 NB_DEV_IND_SEL:8; ///< + UINT32 Reserved_31_24:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xC8_STRUCT; + + + +#ifdef _GNBPCIEINITLIBV4_H_ + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGateDigCEnable:1 ; ///< + UINT32 DdiGateDigDEnable:1 ; ///< + UINT32 SpareRegRw:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +#endif + +#ifdef _GNBPCIEINITLIBV5_H_ // KV version of WRAP_8014 + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Type +#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_OFFSET 2 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_MASK 0x4 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_OFFSET 3 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_MASK 0x8 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_OFFSET 4 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_MASK 0x10 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_OFFSET 5 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_11_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_WIDTH 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_MASK 0xfc0 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET 14 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK 0x4000 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET 15 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK 0x8000 +#define D0F0xE4_WRAP_8014_Reserved_19_16_OFFSET 16 +#define D0F0xE4_WRAP_8014_Reserved_19_16_WIDTH 4 +#define D0F0xE4_WRAP_8014_Reserved_19_16_MASK 0xf0000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3 +#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xe00000 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_OFFSET 25 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_MASK 0x2000000 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_OFFSET 26 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_MASK 0x4000000 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_OFFSET 27 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_MASK 0x8000000 +#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28 +#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4 +#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiPifa1xGateEnable:1 ; ///< + UINT32 DdiPifb1xGateEnable:1 ; ///< + UINT32 DdiPifc1xGateEnable:1 ; ///< + UINT32 DdiPifd1xGateEnable:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdiDigaGateEnable:1 ; ///< + UINT32 DdiDigbGateEnable:1 ; ///< + UINT32 DdiDigcGateEnable:1 ; ///< + UINT32 DdiDigdGateEnable:1 ; ///< + UINT32 SpareRegRw:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8029 Register Definition **** +// Address +#define D0F0xE4_WRAP_8029_ADDRESS 0x8029 +// Type +#define D0F0xE4_WRAP_8029_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8029_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8029_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8029_LaneEnable_MASK 0xFFFF +#define D0F0xE4_WRAP_8029_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_WRAP_8029 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8029_STRUCT; + +#endif + +#ifdef _GNBPCIETRAININGV2_H_ + +// **** DxFxx68 Register Definition **** +// Address +#define DxFxx68_ADDRESS 0x68 +// Type +#define DxFxx68_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx68_PmControl_OFFSET 0 +#define DxFxx68_PmControl_WIDTH 2 +#define DxFxx68_PmControl_MASK 0x3 +#define DxFxx68_Reserved_2_2_OFFSET 2 +#define DxFxx68_Reserved_2_2_WIDTH 1 +#define DxFxx68_Reserved_2_2_MASK 0x4 +#define DxFxx68_ReadCplBoundary_OFFSET 3 +#define DxFxx68_ReadCplBoundary_WIDTH 1 +#define DxFxx68_ReadCplBoundary_MASK 0x8 +#define DxFxx68_LinkDis_OFFSET 4 +#define DxFxx68_LinkDis_WIDTH 1 +#define DxFxx68_LinkDis_MASK 0x10 +#define DxFxx68_RetrainLink_OFFSET 5 +#define DxFxx68_RetrainLink_WIDTH 1 +#define DxFxx68_RetrainLink_MASK 0x20 +#define DxFxx68_CommonClockCfg_OFFSET 6 +#define DxFxx68_CommonClockCfg_WIDTH 1 +#define DxFxx68_CommonClockCfg_MASK 0x40 +#define DxFxx68_ExtendedSync_OFFSET 7 +#define DxFxx68_ExtendedSync_WIDTH 1 +#define DxFxx68_ExtendedSync_MASK 0x80 +#define DxFxx68_ClockPowerManagementEn_OFFSET 8 +#define DxFxx68_ClockPowerManagementEn_WIDTH 1 +#define DxFxx68_ClockPowerManagementEn_MASK 0x100 +#define DxFxx68_HWAutonomousWidthDisable_OFFSET 9 +#define DxFxx68_HWAutonomousWidthDisable_WIDTH 1 +#define DxFxx68_HWAutonomousWidthDisable_MASK 0x200 +#define DxFxx68_LinkBWManagementEn_OFFSET 10 +#define DxFxx68_LinkBWManagementEn_WIDTH 1 +#define DxFxx68_LinkBWManagementEn_MASK 0x400 +#define DxFxx68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxFxx68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxFxx68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxFxx68_Reserved_15_12_OFFSET 12 +#define DxFxx68_Reserved_15_12_WIDTH 4 +#define DxFxx68_Reserved_15_12_MASK 0xF000 +#define DxFxx68_LinkSpeed_OFFSET 16 +#define DxFxx68_LinkSpeed_WIDTH 4 +#define DxFxx68_LinkSpeed_MASK 0xF0000 +#define DxFxx68_NegotiatedLinkWidth_OFFSET 20 +#define DxFxx68_NegotiatedLinkWidth_WIDTH 6 +#define DxFxx68_NegotiatedLinkWidth_MASK 0x3F00000 +#define DxFxx68_Reserved_26_26_OFFSET 26 +#define DxFxx68_Reserved_26_26_WIDTH 1 +#define DxFxx68_Reserved_26_26_MASK 0x4000000 +#define DxFxx68_LinkTraining_OFFSET 27 +#define DxFxx68_LinkTraining_WIDTH 1 +#define DxFxx68_LinkTraining_MASK 0x8000000 +#define DxFxx68_SlotClockCfg_OFFSET 28 +#define DxFxx68_SlotClockCfg_WIDTH 1 +#define DxFxx68_SlotClockCfg_MASK 0x10000000 +#define DxFxx68_DlActive_OFFSET 29 +#define DxFxx68_DlActive_WIDTH 1 +#define DxFxx68_DlActive_MASK 0x20000000 +#define DxFxx68_LinkBWManagementStatus_OFFSET 30 +#define DxFxx68_LinkBWManagementStatus_WIDTH 1 +#define DxFxx68_LinkBWManagementStatus_MASK 0x40000000 +#define DxFxx68_LinkAutonomousBWStatus_OFFSET 31 +#define DxFxx68_LinkAutonomousBWStatus_WIDTH 1 +#define DxFxx68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxFxx68 +typedef union { + struct { ///< + UINT32 PmControl:2; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 ReadCplBoundary:1; ///< + UINT32 LinkDis:1; ///< + UINT32 RetrainLink:1; ///< + UINT32 CommonClockCfg:1; ///< + UINT32 ExtendedSync:1; ///< + UINT32 ClockPowerManagementEn:1; ///< + UINT32 HWAutonomousWidthDisable:1; ///< + UINT32 LinkBWManagementEn:1; ///< + UINT32 LinkAutonomousBWIntEn:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 LinkSpeed:4; ///< + UINT32 NegotiatedLinkWidth:6; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 LinkTraining:1; ///< + UINT32 SlotClockCfg:1; ///< + UINT32 DlActive:1; ///< + UINT32 LinkBWManagementStatus:1; ///< + UINT32 LinkAutonomousBWStatus:1; ///< + + } Field; + + UINT32 Value; +} DxFxx68_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_0800_STRUCT; + +// **** DxFxx128 Register Definition **** +// Address +#define DxFxx128_ADDRESS 0x128 +// Type +#define DxFxx128_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx128_Reserved_15_0_OFFSET 0 +#define DxFxx128_Reserved_15_0_WIDTH 16 +#define DxFxx128_Reserved_15_0_MASK 0xFFFF +#define DxFxx128_PortArbTableStatus_OFFSET 16 +#define DxFxx128_PortArbTableStatus_WIDTH 1 +#define DxFxx128_PortArbTableStatus_MASK 0x10000 +#define DxFxx128_VcNegotiationPending_OFFSET 17 +#define DxFxx128_VcNegotiationPending_WIDTH 1 +#define DxFxx128_VcNegotiationPending_MASK 0x20000 +#define DxFxx128_Reserved_31_18_OFFSET 18 +#define DxFxx128_Reserved_31_18_WIDTH 14 +#define DxFxx128_Reserved_31_18_MASK 0xFFFC0000 + +/// DxFxx128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1; ///< + UINT32 VcNegotiationPending:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} DxFxx128_STRUCT; + +// **** DxFxx18 Register Definition **** +// Address +#define DxFxx18_ADDRESS 0x18 +// Type +#define DxFxx18_TYPE TYPE_D2F1 + +// **** DxFxx20 Register Definition **** +// Address +#define DxFxx20_ADDRESS 0x20 +// Type +#define DxFxx20_TYPE TYPE_D2F1 + +// **** DxFxx24 Register Definition **** +// Address +#define DxFxx24_ADDRESS 0x24 +// Type +#define DxFxx24_TYPE TYPE_D2F1 + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 +// Type +#define D0F0x04_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_19_3_OFFSET 3 +#define D0F0x04_Reserved_19_3_WIDTH 17 +#define D0F0x04_Reserved_19_3_MASK 0xFFFF8 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_Reserved_31_21_OFFSET 21 +#define D0F0x04_Reserved_31_21_WIDTH 11 +#define D0F0x04_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1; ///< + UINT32 MemAccessEn:1; ///< + UINT32 BusMasterEn:1; ///< + UINT32 Reserved_19_3:17; ///< + UINT32 CapList:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0x04_STRUCT; + +#endif + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_X2Lane98_OFFSET 4 +#define D0F0xE4_PIF_0011_X2Lane98_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane98_MASK 0x10 +#define D0F0xE4_PIF_0011_X2Lane1110_OFFSET 5 +#define D0F0xE4_PIF_0011_X2Lane1110_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1110_MASK 0x20 +#define D0F0xE4_PIF_0011_X2Lane1312_OFFSET 6 +#define D0F0xE4_PIF_0011_X2Lane1312_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1312_MASK 0x40 +#define D0F0xE4_PIF_0011_X2Lane1514_OFFSET 7 +#define D0F0xE4_PIF_0011_X2Lane1514_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1514_MASK 0x80 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_X4Lane118_OFFSET 10 +#define D0F0xE4_PIF_0011_X4Lane118_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane118_MASK 0x400 +#define D0F0xE4_PIF_0011_X4Lane1512_OFFSET 11 +#define D0F0xE4_PIF_0011_X4Lane1512_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane1512_MASK 0x800 +#define D0F0xE4_PIF_0011_Reserved_15_12_OFFSET 12 +#define D0F0xE4_PIF_0011_Reserved_15_12_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_15_12_MASK 0xf000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_X8Lane158_OFFSET 17 +#define D0F0xE4_PIF_0011_X8Lane158_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane158_MASK 0x20000 +#define D0F0xE4_PIF_0011_Reserved_19_18_OFFSET 18 +#define D0F0xE4_PIF_0011_Reserved_19_18_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_19_18_MASK 0xc0000 +#define D0F0xE4_PIF_0011_X16Lane150_OFFSET 20 +#define D0F0xE4_PIF_0011_X16Lane150_WIDTH 1 +#define D0F0xE4_PIF_0011_X16Lane150_MASK 0x100000 +#define D0F0xE4_PIF_0011_Reserved_24_21_OFFSET 21 +#define D0F0xE4_PIF_0011_Reserved_24_21_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_24_21_MASK 0x1e00000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 X2Lane98:1 ; ///< + UINT32 X2Lane1110:1 ; ///< + UINT32 X2Lane1312:1 ; ///< + UINT32 X2Lane1514:1 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 X4Lane118:1 ; ///< + UINT32 X4Lane1512:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 X8Lane158:1 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 X16Lane150:1 ; ///< + UINT32 Reserved_24_21:4 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + + +// **** D0F0xE4_PIF_0017 Register Definition **** +// Address +#define D0F0xE4_PIF_0017_ADDRESS 0x17 + +// Type +#define D0F0xE4_PIF_0017_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0017_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0017_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0017_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0017_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0017_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0017_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0017_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0017_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0017_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0017_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0017_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0017_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0017 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0017_STRUCT; + + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Bitfield_6_6_MASK 0x40 +#define D0F0xE4_CORE_00B0_Reserved_31_7_OFFSET 7 +#define D0F0xE4_CORE_00B0_Reserved_31_7_WIDTH 25 +#define D0F0xE4_CORE_00B0_Reserved_31_7_MASK 0xffffff80 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 StrapF0AerEn:1 ; ///< + UINT32 Bitfield_6_6:1 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; +typedef union { + struct { ///< + UINT32 Bitfield_0_0:1; ///< + UINT32 Bitfield_1_1:1 ; ///< + UINT32 Reserved_15_2:14; ///< + UINT32 Bitfield_16_16:1; ///< + UINT32 Bitfield_17_17:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} GRC2_STRUCT; + + + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h new file mode 100644 index 0000000000..a469eb35a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h @@ -0,0 +1,3954 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88282 $ @e \$Date: 2013-02-19 11:20:56 -0600 (Tue, 19 Feb 2013) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +#ifndef _GNBREGISTERSKB_H_ +#define _GNBREGISTERSKB_H_ +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xBC 0x4 +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_D18F4 0xe +#define TYPE_D18F5 0xf +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define TYPE_D18F2x9C_dct0 0x13 +#define TYPE_D18F2x9C_dct0_mp0 0x14 +#define TYPE_D18F2x9C_dct0_mp1 0x15 +#define TYPE_D18F2x9C_dct1 0x16 +#define TYPE_D18F2x9C_dct1_mp0 0x17 +#define TYPE_D18F2x9C_dct1_mp1 0x18 +#define TYPE_D18F2_dct0 0x19 +#define TYPE_D18F2_dct1 0x1a +#define TYPE_D18F2_dct0_mp0 0x1b +#define TYPE_D18F2_dct0_mp1 0x1c +#define TYPE_D1F1 0x1d +#define TYPE_D18F2_dct1_mp0 0x1e +#define TYPE_D18F2_dct1_mp1 0x1f +#define TYPE_CGIND 0x20 +#define TYPE_SMU_MSG 0x21 +#define TYPE_D0F0xD4 0x22 +#define TYPE_D18F0 0x24 + +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + +#define INVALID_SMU_MSG 0xFF +#define SMU_MSG_TYPE TYPE_SMU_MSG +#define SMC_MSG_TEST INVALID_SMU_MSG // 1 +#define SMC_MSG_PHY_LN_OFF INVALID_SMU_MSG // 2 +#define SMC_MSG_PHY_LN_ON INVALID_SMU_MSG // 3 +#define SMC_MSG_DDI_PHY_OFF INVALID_SMU_MSG // 4 +#define SMC_MSG_DDI_PHY_ON INVALID_SMU_MSG // 5 +#define SMC_MSG_CASCADE_PLL_OFF INVALID_SMU_MSG // 6 +#define SMC_MSG_CASCADE_PLL_ON INVALID_SMU_MSG // 7 +#define SMC_MSG_PWR_OFF_x16 INVALID_SMU_MSG // 8 +#define SMC_MSG_FLUSH_DATA_CACHE INVALID_SMU_MSG // 10 +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE INVALID_SMU_MSG // 11 +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 12 +#define SMC_MSG_RECONFIGURE_SB 25 +#define SMC_MSG_UPDATE_BAPM INVALID_SMU_MSG // 26 +#define SMC_MSG_PCIE_PLLSWITCH INVALID_SMU_MSG // 27 +#define SMC_MSG_FORCE_LCLK_DPM_STATE INVALID_SMU_MSG // 28 +#define SMC_MSG_UNFORCE_LCLK_DPM_STATE INVALID_SMU_MSG // 29 +#define SMC_MSG_LCLK_DPM_ENABLE 30 +#define SMC_MSG_LCLK_DPM_DISABLE 31 +#define SMC_MSG_DDI_PHY_IDLE INVALID_SMU_MSG // 34 +#define SMC_MSG_DDI_PHY_BUSY INVALID_SMU_MSG // 35 +#define SMC_MSG_DSMU INVALID_SMU_MSG // 36 +#define SMC_MSG_NBDPM_DISABLE INVALID_SMU_MSG // 37 +#define SMC_MSG_NBDPM_FORCENOMINAL INVALID_SMU_MSG // 38 +#define SMC_MSG_NBDPM_FORCEPERFORMANCE INVALID_SMU_MSG // 39 +#define SMC_MSG_NBDPM_UNFORCE INVALID_SMU_MSG // 40 +#define SMC_MSG_RESET INVALID_SMU_MSG // 41 +#define SMC_MSG_AVS_ENABLE INVALID_SMU_MSG // 42 +#define SMC_MSG_AVS_DISABLE INVALID_SMU_MSG // 43 +#define SMC_MSG_LPMX_ENABLE INVALID_SMU_MSG // 44 +#define SMC_MSG_LPMX_DISABLE INVALID_SMU_MSG // 45 +#define SMC_MSG_TDC_LIMIT_DISABLE 47 +#define SMC_MSG_BAPM_DISABLE 49 +#define SMC_MSG_TDP_LIMIT_ENABLE INVALID_SMU_MSG // 50 +#define SMC_MSG_TDP_LIMIT_DISABLE INVALID_SMU_MSG // 51 +#define SMC_MSG_SPMI_ENABLE INVALID_SMU_MSG // 52 +#define SMC_MSG_SPMI_DISABLE INVALID_SMU_MSG // 53 +#define SMC_MSG_SPMI_TEST INVALID_SMU_MSG // 54 +#define SMC_MSG_EXT_API INVALID_SMU_MSG // 55 +#define SMC_MSG_THERMAL_CNTL_DISABLE 57 +#define SMC_MSG_VDDNB_REQUEST 58 +#define SMC_MSG_VOLTAGE_CNTL_ENABLE 59 +#define SMC_MSG_VOLTAGE_CNTL_DISABLE 60 +#define SMC_MSG_NBDPM_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MCARB_UPDATE_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MCARB_UPDATE_DISABLE INVALID_SMU_MSG +#define SMC_MSG_LHTC_LIMIT_DISABLE 71 +#define SMC_MSG_PWR_OFF_IOMMU INVALID_SMU_MSG +#define SMC_MSG_PWR_ON_IOMMU INVALID_SMU_MSG +#define SMC_MSG_MONITOR_PORT80_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MONITOR_PORT80_DISABLE INVALID_SMU_MSG +#define SMC_MSG_LCLKDPM_SETENABLEMASK INVALID_SMU_MSG +#define SMC_MSG_READ_SCS 80 +#define SMC_MSG_ENABLE_PKGPWRLIMIT 81 +#define SMC_MSG_DISABLE_PKGPWRLIMIT 82 +#define SMC_MSG_ENABLE_ALLCLK_MONITOR 83 +#define SMC_MSG_DISABLE_ALLCLK_MONITOR INVALID_SMU_MSG +#define SMC_MSG_LHTC_LIMIT_SetLimit 90 // 0x5A + +#define L1_SEL_PPD 0 +#define L1_SEL_BIF 1 +#define L1_SEL_INTGEN 2 + +// **** D18F0x110 Register Definition **** +// Address +#define D18F0x110_ADDRESS 0x110 + +// Type +#define D18F0x110_TYPE TYPE_D18F0 + +// **** D18F1x44 Register Definition **** +// Address +#define D18F1x44_ADDRESS 0x44 +// Type +#define D18F1x44_TYPE TYPE_D18F1 + +// Field Data +#define D18F1x44_DstNode_OFFSET 0 +#define D18F1x44_DstNode_WIDTH 3 +#define D18F1x44_DstNode_MASK 0x7 +#define D18F1x44_Reserved_7_3_OFFSET 3 +#define D18F1x44_Reserved_7_3_WIDTH 5 +#define D18F1x44_Reserved_7_3_MASK 0xF8 +#define D18F1x44_Reserved_10_8_OFFSET 8 +#define D18F1x44_Reserved_10_8_WIDTH 3 +#define D18F1x44_Reserved_10_8_MASK 0x700 +#define D18F1x44_Reserved_15_11_OFFSET 11 +#define D18F1x44_Reserved_15_11_WIDTH 5 +#define D18F1x44_Reserved_15_11_MASK 0xF800 +#define D18F1x44_DramLimit_39_24_OFFSET 16 +#define D18F1x44_DramLimit_39_24_WIDTH 16 +#define D18F1x44_DramLimit_39_24_MASK 0xFFFF0000 + +/// D18F1x44 +typedef union { + struct { ///< + UINT32 DstNode:3; ///< + UINT32 Reserved_7_3:5; ///< + UINT32 Reserved_10_8:3; ///< + UINT32 Reserved_15_11:5; ///< + UINT32 DramLimit_39_24:16; ///< + + } Field; + + UINT32 Value; +} D18F1x44_STRUCT; + + + +// **** D18F2x90_dct0 Register Definition **** +// Address +#define D18F2x90_dct0_ADDRESS 0x90 +// Type +#define D18F2x90_dct0_TYPE TYPE_D18F2 + +// Field Data +#define D18F2x90_dct0_ExitSelfRef_OFFSET 1 +#define D18F2x90_dct0_ExitSelfRef_WIDTH 1 +#define D18F2x90_dct0_ExitSelfRef_MASK 0x2 +#define D18F2x90_dct0_Reserved_7_2_OFFSET 2 +#define D18F2x90_dct0_Reserved_7_2_WIDTH 6 +#define D18F2x90_dct0_Reserved_7_2_MASK 0xfc +#define D18F2x90_dct0_Reserved_8_8_OFFSET 8 +#define D18F2x90_dct0_Reserved_8_8_WIDTH 1 +#define D18F2x90_dct0_Reserved_8_8_MASK 0x100 +#define D18F2x90_dct0_Reserved_10_9_OFFSET 9 +#define D18F2x90_dct0_Reserved_10_9_WIDTH 2 +#define D18F2x90_dct0_Reserved_10_9_MASK 0x600 +#define D18F2x90_dct0_Reserved_11_11_OFFSET 11 +#define D18F2x90_dct0_Reserved_11_11_WIDTH 1 +#define D18F2x90_dct0_Reserved_11_11_MASK 0x800 +#define D18F2x90_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x90_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x90_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x90_dct0_UnbuffDimm_OFFSET 16 +#define D18F2x90_dct0_UnbuffDimm_WIDTH 1 +#define D18F2x90_dct0_UnbuffDimm_MASK 0x10000 +#define D18F2x90_dct0_UnbuffDimm_VALUE 0x1 +#define D18F2x90_dct0_EnterSelfRef_OFFSET 17 +#define D18F2x90_dct0_EnterSelfRef_WIDTH 1 +#define D18F2x90_dct0_EnterSelfRef_MASK 0x20000 +#define D18F2x90_dct0_PendRefPayback_OFFSET 18 +#define D18F2x90_dct0_PendRefPayback_WIDTH 1 +#define D18F2x90_dct0_PendRefPayback_MASK 0x40000 +#define D18F2x90_dct0_PendRefPayback_VALUE 0x0 +#define D18F2x90_dct0_DimmEccEn_OFFSET 19 +#define D18F2x90_dct0_DimmEccEn_WIDTH 1 +#define D18F2x90_dct0_DimmEccEn_MASK 0x80000 +#define D18F2x90_dct0_DynPageCloseEn_OFFSET 20 +#define D18F2x90_dct0_DynPageCloseEn_WIDTH 1 +#define D18F2x90_dct0_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_dct0_IdleCycLowLimit_OFFSET 21 +#define D18F2x90_dct0_IdleCycLowLimit_WIDTH 2 +#define D18F2x90_dct0_IdleCycLowLimit_MASK 0x600000 +#define D18F2x90_dct0_ForceAutoPchg_OFFSET 23 +#define D18F2x90_dct0_ForceAutoPchg_WIDTH 1 +#define D18F2x90_dct0_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_dct0_StagRefEn_OFFSET 24 +#define D18F2x90_dct0_StagRefEn_WIDTH 1 +#define D18F2x90_dct0_StagRefEn_MASK 0x1000000 +#define D18F2x90_dct0_StagRefEn_VALUE 0x1 +#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET 25 +#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH 1 +#define D18F2x90_dct0_PendRefPaybackS3En_MASK 0x2000000 +#define D18F2x90_dct0_PendRefPaybackS3En_VALUE 0x1 +#define D18F2x90_dct0_Reserved_26_26_OFFSET 26 +#define D18F2x90_dct0_Reserved_26_26_WIDTH 1 +#define D18F2x90_dct0_Reserved_26_26_MASK 0x4000000 +#define D18F2x90_dct0_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_dct0_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_dct0_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_dct0_IdleCycLimit_OFFSET 28 +#define D18F2x90_dct0_IdleCycLimit_WIDTH 4 +#define D18F2x90_dct0_IdleCycLimit_MASK 0xf0000000 +#define D18F2x90_dct0_IdleCycLimit_VALUE 0x8 + +/// D18F2x90_dct0 +typedef union { + struct { ///< + UINT32 ExitSelfRef:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_10_9:2 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 UnbuffDimm:1 ; ///< + UINT32 EnterSelfRef:1 ; ///< + UINT32 PendRefPayback:1 ; ///< + UINT32 DimmEccEn:1 ; ///< + UINT32 DynPageCloseEn:1 ; ///< + UINT32 IdleCycLowLimit:2 ; ///< + UINT32 ForceAutoPchg:1 ; ///< + UINT32 StagRefEn:1 ; ///< + UINT32 PendRefPaybackS3En:1 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 DisDllShutdownSR:1 ; ///< + UINT32 IdleCycLimit:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x90_dct0_STRUCT; + + +// **** D18F2x94_dct0 Register Definition **** +// Address +#define D18F2x94_dct0_ADDRESS 0x94 +// Type +#define D18F2x94_dct0_TYPE TYPE_D18F2_dct0 + +// Field Data +#define D18F2x94_dct0_MemClkFreq_OFFSET 0 +#define D18F2x94_dct0_MemClkFreq_WIDTH 5 +#define D18F2x94_dct0_MemClkFreq_MASK 0x1f +#define D18F2x94_dct0_Reserved_6_5_OFFSET 5 +#define D18F2x94_dct0_Reserved_6_5_WIDTH 2 +#define D18F2x94_dct0_Reserved_6_5_MASK 0x60 +#define D18F2x94_dct0_MemClkFreqVal_OFFSET 7 +#define D18F2x94_dct0_MemClkFreqVal_WIDTH 1 +#define D18F2x94_dct0_MemClkFreqVal_MASK 0x80 +#define D18F2x94_dct0_Reserved_9_8_OFFSET 8 +#define D18F2x94_dct0_Reserved_9_8_WIDTH 2 +#define D18F2x94_dct0_Reserved_9_8_MASK 0x300 +#define D18F2x94_dct0_ZqcsInterval_OFFSET 10 +#define D18F2x94_dct0_ZqcsInterval_WIDTH 2 +#define D18F2x94_dct0_ZqcsInterval_MASK 0xc00 +#define D18F2x94_dct0_RDqsEn_OFFSET 12 +#define D18F2x94_dct0_RDqsEn_WIDTH 1 +#define D18F2x94_dct0_RDqsEn_MASK 0x1000 +#define D18F2x94_dct0_Reserved_13_13_OFFSET 13 +#define D18F2x94_dct0_Reserved_13_13_WIDTH 1 +#define D18F2x94_dct0_Reserved_13_13_MASK 0x2000 +#define D18F2x94_dct0_DisDramInterface_OFFSET 14 +#define D18F2x94_dct0_DisDramInterface_WIDTH 1 +#define D18F2x94_dct0_DisDramInterface_MASK 0x4000 +#define D18F2x94_dct0_PowerDownEn_OFFSET 15 +#define D18F2x94_dct0_PowerDownEn_WIDTH 1 +#define D18F2x94_dct0_PowerDownEn_MASK 0x8000 +#define D18F2x94_dct0_PowerDownMode_OFFSET 16 +#define D18F2x94_dct0_PowerDownMode_WIDTH 1 +#define D18F2x94_dct0_PowerDownMode_MASK 0x10000 +#define D18F2x94_dct0_PowerDownMode_VALUE 0x1 +#define D18F2x94_dct0_Reserved_17_17_OFFSET 17 +#define D18F2x94_dct0_Reserved_17_17_WIDTH 1 +#define D18F2x94_dct0_Reserved_17_17_MASK 0x20000 +#define D18F2x94_dct0_Reserved_18_18_OFFSET 18 +#define D18F2x94_dct0_Reserved_18_18_WIDTH 1 +#define D18F2x94_dct0_Reserved_18_18_MASK 0x40000 +#define D18F2x94_dct0_Reserved_19_19_OFFSET 19 +#define D18F2x94_dct0_Reserved_19_19_WIDTH 1 +#define D18F2x94_dct0_Reserved_19_19_MASK 0x80000 +#define D18F2x94_dct0_SlowAccessMode_OFFSET 20 +#define D18F2x94_dct0_SlowAccessMode_WIDTH 1 +#define D18F2x94_dct0_SlowAccessMode_MASK 0x100000 +#define D18F2x94_dct0_FreqChgInProg_OFFSET 21 +#define D18F2x94_dct0_FreqChgInProg_WIDTH 1 +#define D18F2x94_dct0_FreqChgInProg_MASK 0x200000 +#define D18F2x94_dct0_BankSwizzleMode_OFFSET 22 +#define D18F2x94_dct0_BankSwizzleMode_WIDTH 1 +#define D18F2x94_dct0_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_dct0_ProcOdtDis_OFFSET 23 +#define D18F2x94_dct0_ProcOdtDis_WIDTH 1 +#define D18F2x94_dct0_ProcOdtDis_MASK 0x800000 +#define D18F2x94_dct0_DcqBypassMax_OFFSET 24 +#define D18F2x94_dct0_DcqBypassMax_WIDTH 5 +#define D18F2x94_dct0_DcqBypassMax_MASK 0x1f000000 +#define D18F2x94_dct0_Reserved_30_29_OFFSET 29 +#define D18F2x94_dct0_Reserved_30_29_WIDTH 2 +#define D18F2x94_dct0_Reserved_30_29_MASK 0x60000000 +#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET 31 +#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH 1 +#define D18F2x94_dct0_DphyMemPsSelEn_MASK 0x80000000 +#define D18F2x94_dct0_DphyMemPsSelEn_VALUE 0x1 + +/// D18F2x94_dct0 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 RDqsEn:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 FreqChgInProg:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:5 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 DphyMemPsSelEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_dct0_STRUCT; + +#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET 16 +#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH 2 + +// **** D18F2x2E0_dct0 Register Definition **** +// Address +#define D18F2x2E0_dct0_ADDRESS 0x2e0 + +// Type +#define D18F2x2E0_dct0_TYPE TYPE_D18F2 +// Field Data + +#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET 24 +#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH 5 + +/// D18F2x2E0_dct0 +typedef union { + struct { ///< + UINT32 Reserved_1:1 ; ///< + UINT32 Reserved_19_1:19; ///< + UINT32 Reserved_22_20:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 M1MemClkFreq:5 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E0_dct0_STRUCT; + +// **** D18F4x110 Register Definition **** +// Address +#define D18F4x110_ADDRESS 0x110 + +// Type +#define D18F4x110_TYPE TYPE_D18F4 +// Field Data +#define D18F4x110_CSampleTimer_OFFSET 0 +#define D18F4x110_CSampleTimer_WIDTH 12 +#define D18F4x110_CSampleTimer_MASK 0xfff +#define D18F4x110_CSampleTimer_VALUE 0x2 +#define D18F4x110_FastCSampleTimer_OFFSET 12 +#define D18F4x110_FastCSampleTimer_WIDTH 1 +#define D18F4x110_FastCSampleTimer_MASK 0x1000 +#define D18F4x110_MinResTmr_OFFSET 13 +#define D18F4x110_MinResTmr_WIDTH 8 +#define D18F4x110_MinResTmr_MASK 0x1fe000 +#define D18F4x110_Reserved_31_21_OFFSET 21 +#define D18F4x110_Reserved_31_21_WIDTH 11 +#define D18F4x110_Reserved_31_21_MASK 0xffe00000 + +/// D18F4x110 +typedef union { + struct { ///< + UINT32 CSampleTimer:12; ///< + UINT32 FastCSampleTimer:1 ; ///< + UINT32 MinResTmr:8 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x110_STRUCT; + +// **** D18F5xE0 Register Definition **** +// Address +#define D18F5xE0_ADDRESS 0xe0 + +// Type +#define D18F5xE0_TYPE TYPE_D18F5 +// Field Data +#define D18F5xE0_RunAvgRange_OFFSET 0 +#define D18F5xE0_RunAvgRange_WIDTH 4 +#define D18F5xE0_RunAvgRange_MASK 0xf +#define D18F5xE0_RunAvgRange_VALUE 0x2 +#define D18F5xE0_Reserved_31_4_OFFSET 4 +#define D18F5xE0_Reserved_31_4_WIDTH 28 +#define D18F5xE0_Reserved_31_4_MASK 0xfffffff0 + +/// D18F5xE0 +typedef union { + struct { ///< + UINT32 RunAvgRange:4 ; ///< + UINT32 Reserved_31_4:28 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5xE0_STRUCT; + +// **** D18F5x160 Register Definition **** +// Address +#define D18F5x160_ADDRESS 0x160 + +// Type +#define D18F5x160_TYPE TYPE_D18F5 +#define D18F5x160_NbPstateEn_OFFSET 0 +#define D18F5x160_NbPstateEn_WIDTH 1 + +#define D18F5x160_MemPstate_OFFSET 18 +#define D18F5x160_MemPstate_WIDTH 1 +#define D18F5x160_NbFid_OFFSET 1 +#define D18F5x160_NbFid_WIDTH 6 +#define D18F5x160_NbDid_OFFSET 7 +#define D18F5x160_NbDid_WIDTH 1 +#define D18F5x160_NbVid_6_0_OFFSET 10 +#define D18F5x160_NbVid_6_0_WIDTH 7 +#define D18F5x160_NbVid_7_OFFSET 21 +#define D18F5x160_NbVid_7_WIDTH 1 + +#define D18F5x160_NbVid_7__OFFSET 21 +#define D18F5x160_NbVid_7__WIDTH 1 + +/// D18F5x160 +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x160_STRUCT; + +// **** D18F5x164 Register Definition **** +// Address +#define D18F5x164_ADDRESS 0x164 + +// Type +#define D18F5x164_TYPE TYPE_D18F5 +#define D18F5x164_NbPstateEn_OFFSET 0 +#define D18F5x164_NbPstateEn_WIDTH 1 +#define D18F5x164_MemPstate_OFFSET 18 +#define D18F5x164_MemPstate_WIDTH 1 +#define D18F5x164_NbFid_OFFSET 1 +#define D18F5x164_NbFid_WIDTH 6 +#define D18F5x164_NbDid_OFFSET 7 +#define D18F5x164_NbDid_WIDTH 1 +#define D18F5x164_NbVid_6_0_OFFSET 10 +#define D18F5x164_NbVid_6_0_WIDTH 7 +#define D18F5x164_NbVid_7_OFFSET 21 +#define D18F5x164_NbVid_7_WIDTH 1 + +// **** D18F5x168 Register Definition **** +// Address +#define D18F5x168_ADDRESS 0x168 + +// Type +#define D18F5x168_TYPE TYPE_D18F5 +#define D18F5x168_NbPstateEn_OFFSET 0 +#define D18F5x168_NbPstateEn_WIDTH 1 +#define D18F5x168_NbFid_OFFSET 1 +#define D18F5x168_NbFid_WIDTH 6 +#define D18F5x168_NbDid_OFFSET 7 +#define D18F5x168_NbDid_WIDTH 1 +#define D18F5x168_NbVid_6_0_OFFSET 10 +#define D18F5x168_NbVid_6_0_WIDTH 7 +#define D18F5x168_MemPstate_OFFSET 18 +#define D18F5x168_MemPstate_WIDTH 1 +#define D18F5x168_NbVid_7_OFFSET 21 +#define D18F5x168_NbVid_7_WIDTH 1 + +// **** D18F5x16C Register Definition **** +// Address +#define D18F5x16C_ADDRESS 0x16c + +// Type +#define D18F5x16C_TYPE TYPE_D18F5 +#define D18F5x16C_NbPstateEn_OFFSET 0 +#define D18F5x16C_NbPstateEn_WIDTH 1 +#define D18F5x16C_NbFid_OFFSET 1 +#define D18F5x16C_NbFid_WIDTH 6 +#define D18F5x16C_NbDid_OFFSET 7 +#define D18F5x16C_NbDid_WIDTH 1 +#define D18F5x16C_NbVid_6_0_OFFSET 10 +#define D18F5x16C_NbVid_6_0_WIDTH 7 +#define D18F5x16C_MemPstate_OFFSET 18 +#define D18F5x16C_MemPstate_WIDTH 1 +#define D18F5x16C_NbVid_7_OFFSET 21 +#define D18F5x16C_NbVid_7_WIDTH 1 + +// **** D18F5x170 Register Definition **** +// Address +#define D18F5x170_ADDRESS 0x170 + +// Type +#define D18F5x170_TYPE TYPE_D18F5 +// Field Data +#define D18F5x170_NbPstateMaxVal_OFFSET 0 +#define D18F5x170_NbPstateMaxVal_WIDTH 2 +#define D18F5x170_NbPstateMaxVal_MASK 0x3 +#define D18F5x170_Reserved_2_2_OFFSET 2 +#define D18F5x170_Reserved_2_2_WIDTH 1 +#define D18F5x170_Reserved_2_2_MASK 0x4 +#define D18F5x170_NbPstateLo_OFFSET 3 +#define D18F5x170_NbPstateLo_WIDTH 2 +#define D18F5x170_NbPstateLo_MASK 0x18 +#define D18F5x170_Reserved_5_5_OFFSET 5 +#define D18F5x170_Reserved_5_5_WIDTH 1 +#define D18F5x170_Reserved_5_5_MASK 0x20 +#define D18F5x170_NbPstateHi_OFFSET 6 +#define D18F5x170_NbPstateHi_WIDTH 2 +#define D18F5x170_NbPstateHi_MASK 0xc0 +#define D18F5x170_Reserved_8_8_OFFSET 8 +#define D18F5x170_Reserved_8_8_WIDTH 1 +#define D18F5x170_Reserved_8_8_MASK 0x100 +#define D18F5x170_NbPstateThreshold_OFFSET 9 +#define D18F5x170_NbPstateThreshold_WIDTH 4 +#define D18F5x170_NbPstateThreshold_MASK 0x1e00 +#define D18F5x170_Reserved_12_12_OFFSET 12 +#define D18F5x170_Reserved_12_12_WIDTH 1 +#define D18F5x170_Reserved_12_12_MASK 0x1000 +#define D18F5x170_NbPstateDisOnP0_OFFSET 13 +#define D18F5x170_NbPstateDisOnP0_WIDTH 1 +#define D18F5x170_NbPstateDisOnP0_MASK 0x2000 +#define D18F5x170_SwNbPstateLoDis_OFFSET 14 +#define D18F5x170_SwNbPstateLoDis_WIDTH 1 +#define D18F5x170_SwNbPstateLoDis_MASK 0x4000 +#define D18F5x170_Reserved_22_15_OFFSET 15 +#define D18F5x170_Reserved_22_15_WIDTH 8 +#define D18F5x170_Reserved_22_15_MASK 0x3f8000 +#define D18F5x170_NbPstateGnbSlowDis_OFFSET 23 +#define D18F5x170_NbPstateGnbSlowDis_WIDTH 1 +#define D18F5x170_NbPstateGnbSlowDis_MASK 0x800000 +#define D18F5x170_NbPstateLoRes_OFFSET 24 +#define D18F5x170_NbPstateLoRes_WIDTH 3 +#define D18F5x170_NbPstateLoRes_MASK 0x7000000 +#define D18F5x170_NbPstateHiRes_OFFSET 27 +#define D18F5x170_NbPstateHiRes_WIDTH 3 +#define D18F5x170_NbPstateHiRes_MASK 0x38000000 +#define D18F5x170_NbPstateFidVidSbcEn_OFFSET 30 +#define D18F5x170_NbPstateFidVidSbcEn_WIDTH 1 +#define D18F5x170_NbPstateFidVidSbcEn_MASK 0x40000000 +#define D18F5x170_MemPstateDis_OFFSET 31 +#define D18F5x170_MemPstateDis_WIDTH 1 +#define D18F5x170_MemPstateDis_MASK 0x80000000 + +/// D18F5x170 +typedef union { + struct { ///< + UINT32 NbPstateMaxVal:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NbPstateLo:2 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 NbPstateHi:2 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 NbPstateThreshold:4 ; ///< + UINT32 NbPstateDisOnP0:1 ; ///< + UINT32 SwNbPstateLoDis:1 ; ///< + UINT32 Reserved_22_15:8 ; ///< + UINT32 NbPstateGnbSlowDis:1 ; ///< + UINT32 NbPstateLoRes:3 ; ///< + UINT32 NbPstateHiRes:3 ; ///< + UINT32 NbPstateFidVidSbcEn:1 ; ///< + UINT32 MemPstateDis:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x170_STRUCT; + +// **** D18F2x118 Register Definition **** +// Address +#define D18F2x118_ADDRESS 0x118 +// Type +#define D18F2x118_TYPE TYPE_D18F2 + +// Field Data +#define D18F2x118_MctPriCpuRd_OFFSET 0 +#define D18F2x118_MctPriCpuRd_WIDTH 2 +#define D18F2x118_MctPriCpuRd_MASK 0x3 +#define D18F2x118_MctPriCpuWr_OFFSET 2 +#define D18F2x118_MctPriCpuWr_WIDTH 2 +#define D18F2x118_MctPriCpuWr_MASK 0xC +#define D18F2x118_MctPriIsocRd_OFFSET 4 +#define D18F2x118_MctPriIsocRd_WIDTH 2 +#define D18F2x118_MctPriIsocRd_MASK 0x30 +#define D18F2x118_MctPriIsocWr_OFFSET 6 +#define D18F2x118_MctPriIsocWr_WIDTH 2 +#define D18F2x118_MctPriIsocWr_MASK 0xC0 +#define D18F2x118_MctPriDefault_OFFSET 8 +#define D18F2x118_MctPriDefault_WIDTH 2 +#define D18F2x118_MctPriDefault_MASK 0x300 +#define D18F2x118_MctPriWr_OFFSET 10 +#define D18F2x118_MctPriWr_WIDTH 2 +#define D18F2x118_MctPriWr_MASK 0xC00 +#define D18F2x118_MctPriIsoc_OFFSET 12 +#define D18F2x118_MctPriIsoc_WIDTH 2 +#define D18F2x118_MctPriIsoc_MASK 0x3000 +#define D18F2x118_MctPriTrace_OFFSET 14 +#define D18F2x118_MctPriTrace_WIDTH 2 +#define D18F2x118_MctPriTrace_MASK 0xC000 +#define D18F2x118_MctPriScrub_OFFSET 16 +#define D18F2x118_MctPriScrub_WIDTH 2 +#define D18F2x118_MctPriScrub_MASK 0x30000 +#define D18F2x118_CC6SaveEn_OFFSET 18 +#define D18F2x118_CC6SaveEn_WIDTH 1 +#define D18F2x118_CC6SaveEn_MASK 0x40000 +#define D18F2x118_LockDramCfg_OFFSET 19 +#define D18F2x118_LockDramCfg_WIDTH 1 +#define D18F2x118_LockDramCfg_MASK 0x80000 +#define D18F2x118_McqMedPriByPassMax_OFFSET 20 +#define D18F2x118_McqMedPriByPassMax_WIDTH 3 +#define D18F2x118_McqMedPriByPassMax_MASK 0x700000 +#define D18F2x118_Reserved_23_23_OFFSET 23 +#define D18F2x118_Reserved_23_23_WIDTH 1 +#define D18F2x118_Reserved_23_23_MASK 0x800000 +#define D18F2x118_McqHiPriByPassMax_OFFSET 24 +#define D18F2x118_McqHiPriByPassMax_WIDTH 3 +#define D18F2x118_McqHiPriByPassMax_MASK 0x7000000 +#define D18F2x118_Reserved_27_27_OFFSET 27 +#define D18F2x118_Reserved_27_27_WIDTH 1 +#define D18F2x118_Reserved_27_27_MASK 0x8000000 +#define D18F2x118_MctVarPriCntLmt_OFFSET 28 +#define D18F2x118_MctVarPriCntLmt_WIDTH 4 +#define D18F2x118_MctVarPriCntLmt_MASK 0xF0000000 + +/// D18F2x118 +typedef union { + struct { ///< + UINT32 MctPriCpuRd:2; ///< + UINT32 MctPriCpuWr:2; ///< + UINT32 MctPriIsocRd:2; ///< + UINT32 MctPriIsocWr:2; ///< + UINT32 MctPriDefault:2; ///< + UINT32 MctPriWr:2; ///< + UINT32 MctPriIsoc:2; ///< + UINT32 MctPriTrace:2; ///< + UINT32 MctPriScrub:2; ///< + UINT32 CC6SaveEn:1; ///< + UINT32 LockDramCfg:1; ///< + UINT32 McqMedPriByPassMax:3; ///< + UINT32 Reserved_23_23:1; ///< + UINT32 McqHiPriByPassMax:3; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 MctVarPriCntLmt:4; ///< + + } Field; + + UINT32 Value; +} D18F2x118_STRUCT; + + +// **** D18F3x44 Register Definition **** +// Address +#define D18F3x44_ADDRESS 0x44 + +// Type +#define D18F3x44_TYPE TYPE_D18F3 +// Field Data +#define D18F3x44_Reserved_0_0_OFFSET 0 +#define D18F3x44_Reserved_0_0_WIDTH 1 +#define D18F3x44_Reserved_0_0_MASK 0x1 +#define D18F3x44_CpuRdDatErrEn_OFFSET 1 +#define D18F3x44_CpuRdDatErrEn_WIDTH 1 +#define D18F3x44_CpuRdDatErrEn_MASK 0x2 +#define D18F3x44_SyncFloodOnDramUcEcc_OFFSET 2 +#define D18F3x44_SyncFloodOnDramUcEcc_WIDTH 1 +#define D18F3x44_SyncFloodOnDramUcEcc_MASK 0x4 +#define D18F3x44_SyncFloodOnDramUcEcc_VALUE 0x1 +#define D18F3x44_SyncPktGenDis_OFFSET 3 +#define D18F3x44_SyncPktGenDis_WIDTH 1 +#define D18F3x44_SyncPktGenDis_MASK 0x8 +#define D18F3x44_SyncPktGenDis_VALUE 0x0 +#define D18F3x44_SyncPktPropDis_OFFSET 4 +#define D18F3x44_SyncPktPropDis_WIDTH 1 +#define D18F3x44_SyncPktPropDis_MASK 0x10 +#define D18F3x44_SyncPktPropDis_VALUE 0x0 +#define D18F3x44_IoMstAbortDis_OFFSET 5 +#define D18F3x44_IoMstAbortDis_WIDTH 1 +#define D18F3x44_IoMstAbortDis_MASK 0x20 +#define D18F3x44_CpuErrDis_OFFSET 6 +#define D18F3x44_CpuErrDis_WIDTH 1 +#define D18F3x44_CpuErrDis_MASK 0x40 +#define D18F3x44_CpuErrDis_VALUE 0x1 +#define D18F3x44_IoErrDis_OFFSET 7 +#define D18F3x44_IoErrDis_WIDTH 1 +#define D18F3x44_IoErrDis_MASK 0x80 +#define D18F3x44_WDTDis_OFFSET 8 +#define D18F3x44_WDTDis_WIDTH 1 +#define D18F3x44_WDTDis_MASK 0x100 +#define D18F3x44_WDTCntSel_2_0__OFFSET 9 +#define D18F3x44_WDTCntSel_2_0__WIDTH 3 +#define D18F3x44_WDTCntSel_2_0__MASK 0xe00 +#define D18F3x44_WDTBaseSel_OFFSET 12 +#define D18F3x44_WDTBaseSel_WIDTH 2 +#define D18F3x44_WDTBaseSel_MASK 0x3000 +#define D18F3x44_GenLinkSel_OFFSET 14 +#define D18F3x44_GenLinkSel_WIDTH 2 +#define D18F3x44_GenLinkSel_MASK 0xc000 +#define D18F3x44_GenCrcErrByte0_OFFSET 16 +#define D18F3x44_GenCrcErrByte0_WIDTH 1 +#define D18F3x44_GenCrcErrByte0_MASK 0x10000 +#define D18F3x44_GenCrcErrByte1_OFFSET 17 +#define D18F3x44_GenCrcErrByte1_WIDTH 1 +#define D18F3x44_GenCrcErrByte1_MASK 0x20000 +#define D18F3x44_GenSubLinkSel_OFFSET 18 +#define D18F3x44_GenSubLinkSel_WIDTH 2 +#define D18F3x44_GenSubLinkSel_MASK 0xc0000 +#define D18F3x44_SyncFloodOnWDT_OFFSET 20 +#define D18F3x44_SyncFloodOnWDT_WIDTH 1 +#define D18F3x44_SyncFloodOnWDT_MASK 0x100000 +#define D18F3x44_SyncFloodOnWDT_VALUE 0x1 +#define D18F3x44_SyncFloodOnAnyUcErr_OFFSET 21 +#define D18F3x44_SyncFloodOnAnyUcErr_WIDTH 1 +#define D18F3x44_SyncFloodOnAnyUcErr_MASK 0x200000 +#define D18F3x44_SyncFloodOnAnyUcErr_VALUE 0x1 +#define D18F3x44_DramEccEn_OFFSET 22 +#define D18F3x44_DramEccEn_WIDTH 1 +#define D18F3x44_DramEccEn_MASK 0x400000 +#define D18F3x44_ChipKillEccCap_OFFSET 23 +#define D18F3x44_ChipKillEccCap_WIDTH 1 +#define D18F3x44_ChipKillEccCap_MASK 0x800000 +#define D18F3x44_IoRdDatErrEn_OFFSET 24 +#define D18F3x44_IoRdDatErrEn_WIDTH 1 +#define D18F3x44_IoRdDatErrEn_MASK 0x1000000 +#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET 25 +#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH 1 +#define D18F3x44_DisPciCfgCpuErrRsp_MASK 0x2000000 +#define D18F3x44_FlagMcaCorrErr_OFFSET 26 +#define D18F3x44_FlagMcaCorrErr_WIDTH 1 +#define D18F3x44_FlagMcaCorrErr_MASK 0x4000000 +#define D18F3x44_NbMcaToMstCpuEn_OFFSET 27 +#define D18F3x44_NbMcaToMstCpuEn_WIDTH 1 +#define D18F3x44_NbMcaToMstCpuEn_MASK 0x8000000 +#define D18F3x44_NbMcaToMstCpuEn_VALUE 0x1 +#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET 28 +#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisTgtAbortCpuErrRsp_MASK 0x10000000 +#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET 29 +#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisMstAbortCpuErrRsp_MASK 0x20000000 +#define D18F3x44_SyncFloodOnDramAdrParErr_OFFSET 30 +#define D18F3x44_SyncFloodOnDramAdrParErr_WIDTH 1 +#define D18F3x44_SyncFloodOnDramAdrParErr_MASK 0x40000000 +#define D18F3x44_SyncFloodOnDramAdrParErr_VALUE 0x1 +#define D18F3x44_NbMcaLogEn_OFFSET 31 +#define D18F3x44_NbMcaLogEn_WIDTH 1 +#define D18F3x44_NbMcaLogEn_MASK 0x80000000 + +/// D18F3x44 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 CpuRdDatErrEn:1 ; ///< + UINT32 SyncFloodOnDramUcEcc:1 ; ///< + UINT32 SyncPktGenDis:1 ; ///< + UINT32 SyncPktPropDis:1 ; ///< + UINT32 IoMstAbortDis:1 ; ///< + UINT32 CpuErrDis:1 ; ///< + UINT32 IoErrDis:1 ; ///< + UINT32 WDTDis:1 ; ///< + UINT32 WDTCntSel_2_0_:3 ; ///< + UINT32 WDTBaseSel:2 ; ///< + UINT32 GenLinkSel:2 ; ///< + UINT32 GenCrcErrByte0:1 ; ///< + UINT32 GenCrcErrByte1:1 ; ///< + UINT32 GenSubLinkSel:2 ; ///< + UINT32 SyncFloodOnWDT:1 ; ///< + UINT32 SyncFloodOnAnyUcErr:1 ; ///< + UINT32 DramEccEn:1 ; ///< + UINT32 ChipKillEccCap:1 ; ///< + UINT32 IoRdDatErrEn:1 ; ///< + UINT32 DisPciCfgCpuErrRsp:1 ; ///< + UINT32 FlagMcaCorrErr:1 ; ///< + UINT32 NbMcaToMstCpuEn:1 ; ///< + UINT32 DisTgtAbortCpuErrRsp:1 ; ///< + UINT32 DisMstAbortCpuErrRsp:1 ; ///< + UINT32 SyncFloodOnDramAdrParErr:1 ; ///< + UINT32 NbMcaLogEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x44_STRUCT; + +// **** D18F3x64 Register Definition **** +// Address +#define D18F3x64_ADDRESS 0x64 + +// Type +#define D18F3x64_TYPE TYPE_D18F3 +// Field Data +#define D18F3x64_HtcEn_OFFSET 0 +#define D18F3x64_HtcEn_WIDTH 1 +#define D18F3x64_HtcEn_MASK 0x1 +#define D18F3x64_HtcEn_VALUE 0x0 +#define D18F3x64_HtcAct_OFFSET 4 +#define D18F3x64_HtcAct_WIDTH 1 +#define D18F3x64_HtcAct_MASK 0x10 +#define D18F3x64_HtcActSts_OFFSET 5 +#define D18F3x64_HtcActSts_WIDTH 1 +#define D18F3x64_HtcActSts_MASK 0x20 +#define D18F3x64_PslApicHiEn_OFFSET 6 +#define D18F3x64_PslApicHiEn_WIDTH 1 +#define D18F3x64_PslApicHiEn_MASK 0x40 +#define D18F3x64_PslApicLoEn_OFFSET 7 +#define D18F3x64_PslApicLoEn_WIDTH 1 +#define D18F3x64_PslApicLoEn_MASK 0x80 +#define D18F3x64_HtcTmpLmt_OFFSET 16 +#define D18F3x64_HtcTmpLmt_WIDTH 7 +#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 +#define D18F3x64_HtcSlewSel_OFFSET 23 +#define D18F3x64_HtcSlewSel_WIDTH 1 +#define D18F3x64_HtcSlewSel_MASK 0x800000 +#define D18F3x64_HtcHystLmt_OFFSET 24 +#define D18F3x64_HtcHystLmt_WIDTH 4 +#define D18F3x64_HtcHystLmt_MASK 0xf000000 +#define D18F3x64_HtcPstateLimit_OFFSET 28 +#define D18F3x64_HtcPstateLimit_WIDTH 3 +#define D18F3x64_HtcPstateLimit_MASK 0x70000000 +#define D18F3x64_Reserved_31_31_OFFSET 31 +#define D18F3x64_Reserved_31_31_WIDTH 1 +#define D18F3x64_Reserved_31_31_MASK 0x80000000 + +/// D18F3x64 +typedef union { + struct { ///< + UINT32 HtcEn:1 ; ///< + UINT32 bit1:1; + UINT32 bit2:1; + UINT32 Reserved_3_3:1 ; ///< + UINT32 HtcAct:1 ; ///< + UINT32 HtcActSts:1 ; ///< + UINT32 PslApicHiEn:1 ; ///< + UINT32 PslApicLoEn:1 ; ///< + UINT32 bit10_8:3; + UINT32 Reserved_11_11:1 ; ///< + UINT32 bit14_12:3 ; + UINT32 Reserved_15_15:1 ; ///< + UINT32 HtcTmpLmt:7 ; ///< + UINT32 HtcSlewSel:1 ; ///< + UINT32 HtcHystLmt:4 ; ///< + UINT32 HtcPstateLimit:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x64_STRUCT; + + +// **** D18F3xA0 Register Definition **** +// Address +#define D18F3xA0_ADDRESS 0xa0 + +// Type +#define D18F3xA0_TYPE TYPE_D18F3 +// Field Data +#define D18F3xA0_PsiVid_6_0__OFFSET 0 +#define D18F3xA0_PsiVid_6_0__WIDTH 7 +#define D18F3xA0_PsiVid_6_0__MASK 0x7f +#define D18F3xA0_PsiVidEn_OFFSET 7 +#define D18F3xA0_PsiVidEn_WIDTH 1 +#define D18F3xA0_PsiVidEn_MASK 0x80 +#define D18F3xA0_PsiVid_7__OFFSET 8 +#define D18F3xA0_PsiVid_7__WIDTH 1 +#define D18F3xA0_PsiVid_7__MASK 0x100 +#define D18F3xA0_Reserved_9_9_OFFSET 9 +#define D18F3xA0_Reserved_9_9_WIDTH 1 +#define D18F3xA0_Reserved_9_9_MASK 0x200 +#define D18F3xA0_IdleExitEn_OFFSET 10 +#define D18F3xA0_IdleExitEn_WIDTH 1 +#define D18F3xA0_IdleExitEn_MASK 0x400 +#define D18F3xA0_PllLockTime_OFFSET 11 +#define D18F3xA0_PllLockTime_WIDTH 3 +#define D18F3xA0_PllLockTime_MASK 0x3800 +#define D18F3xA0_PllLockTime_VALUE 0x1 +#define D18F3xA0_Svi2HighFreqSel_OFFSET 14 +#define D18F3xA0_Svi2HighFreqSel_WIDTH 1 +#define D18F3xA0_Svi2HighFreqSel_MASK 0x4000 +#define D18F3xA0_Svi2HighFreqSel_VALUE 0x1 +#define D18F3xA0_ConfigId_OFFSET 16 +#define D18F3xA0_ConfigId_WIDTH 12 +#define D18F3xA0_ConfigId_MASK 0xfff0000 +#define D18F3xA0_Reserved_29_29_OFFSET 29 +#define D18F3xA0_Reserved_29_29_WIDTH 1 +#define D18F3xA0_Reserved_29_29_MASK 0x20000000 +#define D18F3xA0_CofVidProg_OFFSET 31 +#define D18F3xA0_CofVidProg_WIDTH 1 +#define D18F3xA0_CofVidProg_MASK 0x80000000 + +/// D18F3xA0 +typedef union { + struct { ///< + UINT32 PsiVid_6_0_:7 ; ///< + UINT32 PsiVidEn:1 ; ///< + UINT32 PsiVid_7_:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 IdleExitEn:1 ; ///< + UINT32 PllLockTime:3 ; ///< + UINT32 Svi2HighFreqSel:1 ; ///< + UINT32 :1 ; ///< + UINT32 ConfigId:12; ///< + UINT32 :1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 :1 ; ///< + UINT32 CofVidProg:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xA0_STRUCT; + + +// **** D18F3xA8 Register Definition **** +// Address +#define D18F3xA8_ADDRESS 0xA8 +// Type +#define D18F3xA8_TYPE TYPE_D18F3 + +// Field Data +#define D18F3xA8_Reserved_28_0_OFFSET 0 +#define D18F3xA8_Reserved_28_0_WIDTH 29 +#define D18F3xA8_Reserved_28_0_MASK 0x1FFFFFFF +#define D18F3xA8_PopDownPstate_OFFSET 29 +#define D18F3xA8_PopDownPstate_WIDTH 3 +#define D18F3xA8_PopDownPstate_MASK 0xE0000000 + +/// D18F3xA8 +typedef union { + struct { ///< + UINT32 Reserved_28_0:29; ///< + UINT32 PopDownPstate:3; ///< + + } Field; + + UINT32 Value; +} D18F3xA8_STRUCT; + +// **** D18F5x12C Register Definition **** +// Address +#define D18F5x12C_ADDRESS 0x12C +// Type +#define D18F5x12C_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x12C_CoreOffsetTrim_OFFSET 0 +#define D18F5x12C_CoreOffsetTrim_WIDTH 2 +#define D18F5x12C_CoreOffsetTrim_MASK 0x3 +#define D18F5x12C_CoreLoadLineTrim_OFFSET 2 +#define D18F5x12C_CoreLoadLineTrim_WIDTH 3 +#define D18F5x12C_CoreLoadLineTrim_MASK 0x1C +#define D18F5x12C_CorePsi1En_OFFSET 5 +#define D18F5x12C_CorePsi1En_WIDTH 1 +#define D18F5x12C_CorePsi1En_MASK 0x20 +#define D18F5x12C_RAZ_29_7_OFFSET 7 +#define D18F5x12C_RAZ_29_7_WIDTH 23 +#define D18F5x12C_RAZ_29_7_MASK 0x3FFFFF80 +#define D18F5x12C_WaitVidCompDis_OFFSET 30 +#define D18F5x12C_WaitVidCompDis_WIDTH 1 +#define D18F5x12C_WaitVidCompDis_MASK 0x40000000 +#define D18F5x12C_Svi2CmdBusy_OFFSET 31 +#define D18F5x12C_Svi2CmdBusy_WIDTH 1 +#define D18F5x12C_Svi2CmdBusy_MASK 0x80000000 + +/// D18F5x12C +typedef union { + struct { ///< + UINT32 CoreOffsetTrim:2; ///< + UINT32 CoreLoadLineTrim:3; ///< + UINT32 CorePsi1En:1; ///< + UINT32 :1; ///< + UINT32 RAZ_29_7:23; ///< + UINT32 WaitVidCompDis:1; ///< + UINT32 Svi2CmdBusy:1; ///< + + } Field; + + UINT32 Value; +} D18F5x12C_STRUCT; + +// **** D18F5x178 Register Definition **** +// Address +#define D18F5x178_ADDRESS 0x178 +// Type +#define D18F5x178_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x178_Reserved_1_0_OFFSET 0 +#define D18F5x178_Reserved_1_0_WIDTH 2 +#define D18F5x178_Reserved_1_0_MASK 0x3 +#define D18F5x178_CstateFusionDis_OFFSET 2 +#define D18F5x178_CstateFusionDis_WIDTH 1 +#define D18F5x178_CstateFusionDis_MASK 0x4 +#define D18F5x178_CstateThreeWayHsEn_OFFSET 3 +#define D18F5x178_CstateThreeWayHsEn_WIDTH 1 +#define D18F5x178_CstateThreeWayHsEn_MASK 0x8 +#define D18F5x178_Reserved_17_4_OFFSET 4 +#define D18F5x178_Reserved_17_4_WIDTH 14 +#define D18F5x178_Reserved_17_4_MASK 0x3FFF0 +#define D18F5x178_CstateFusionHsDis_OFFSET 18 +#define D18F5x178_CstateFusionHsDis_WIDTH 1 +#define D18F5x178_CstateFusionHsDis_MASK 0x40000 +#define D18F5x178_SwGfxDis_OFFSET 19 +#define D18F5x178_SwGfxDis_WIDTH 1 +#define D18F5x178_SwGfxDis_MASK 0x80000 +#define D18F5x178_Reserved_31_20_OFFSET 20 +#define D18F5x178_Reserved_31_20_WIDTH 12 +#define D18F5x178_Reserved_31_20_MASK 0xFFF00000 + +/// D18F5x178 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 CstateFusionDis:1; ///< + UINT32 CstateThreeWayHsEn:1; ///< + UINT32 Reserved_17_4:14; ///< + UINT32 CstateFusionHsDis:1; ///< + UINT32 SwGfxDis:1; ///< + UINT32 Reserved_31_20:12; ///< + + } Field; + + UINT32 Value; +} D18F5x178_STRUCT; + +// **** D18F5x188 Register Definition **** +// Address +#define D18F5x188_ADDRESS 0x188 +// Type +#define D18F5x188_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x188_NbOffsetTrim_OFFSET 0 +#define D18F5x188_NbOffsetTrim_WIDTH 2 +#define D18F5x188_NbOffsetTrim_MASK 0x3 +#define D18F5x188_NbLoadLineTrim_OFFSET 2 +#define D18F5x188_NbLoadLineTrim_WIDTH 3 +#define D18F5x188_NbLoadLineTrim_MASK 0x1C +#define D18F5x188_NbPsi1_OFFSET 5 +#define D18F5x188_NbPsi1_WIDTH 1 +#define D18F5x188_NbPsi1_MASK 0x20 +#define D18F5x188_RAZ_31_7_OFFSET 7 +#define D18F5x188_RAZ_31_7_WIDTH 25 +#define D18F5x188_RAZ_31_7_MASK 0xFFFFFF80 + +/// D18F5x188 +typedef union { + struct { ///< + UINT32 NbOffsetTrim:2; ///< + UINT32 NbLoadLineTrim:3; ///< + UINT32 NbPsi1:1; ///< + UINT32 :1; ///< + UINT32 RAZ_31_7:25; ///< + + } Field; + + UINT32 Value; +} D18F5x188_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 +// Type +#define D0F0x04_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_19_3_OFFSET 3 +#define D0F0x04_Reserved_19_3_WIDTH 17 +#define D0F0x04_Reserved_19_3_MASK 0xFFFF8 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_Reserved_31_21_OFFSET 21 +#define D0F0x04_Reserved_31_21_WIDTH 11 +#define D0F0x04_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1; ///< + UINT32 MemAccessEn:1; ///< + UINT32 BusMasterEn:1; ///< + UINT32 Reserved_19_3:17; ///< + UINT32 CapList:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0x04_STRUCT; + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 +// Type +#define D0F0x64_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xFFFFFFFF + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0x64_STRUCT; + +// **** DxF0x3C Register Definition **** +// Address +#define DxF0x3C_ADDRESS 0x3c + +// Type +#define DxF0x3C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x3C_IntLine_OFFSET 0 +#define DxF0x3C_IntLine_WIDTH 8 +#define DxF0x3C_IntLine_MASK 0xff +#define DxF0x3C_IntPin_OFFSET 8 +#define DxF0x3C_IntPin_WIDTH 3 +#define DxF0x3C_IntPin_MASK 0x700 +#define DxF0x3C_IntPinR_OFFSET 11 +#define DxF0x3C_IntPinR_WIDTH 5 +#define DxF0x3C_IntPinR_MASK 0xf800 +#define DxF0x3C_ParityResponseEn_OFFSET 16 +#define DxF0x3C_ParityResponseEn_WIDTH 1 +#define DxF0x3C_ParityResponseEn_MASK 0x10000 +#define DxF0x3C_SerrEn_OFFSET 17 +#define DxF0x3C_SerrEn_WIDTH 1 +#define DxF0x3C_SerrEn_MASK 0x20000 +#define DxF0x3C_IsaEn_OFFSET 18 +#define DxF0x3C_IsaEn_WIDTH 1 +#define DxF0x3C_IsaEn_MASK 0x40000 +#define DxF0x3C_VgaEn_OFFSET 19 +#define DxF0x3C_VgaEn_WIDTH 1 +#define DxF0x3C_VgaEn_MASK 0x80000 +#define DxF0x3C_Vga16En_OFFSET 20 +#define DxF0x3C_Vga16En_WIDTH 1 +#define DxF0x3C_Vga16En_MASK 0x100000 +#define DxF0x3C_MasterAbortMode_OFFSET 21 +#define DxF0x3C_MasterAbortMode_WIDTH 1 +#define DxF0x3C_MasterAbortMode_MASK 0x200000 +#define DxF0x3C_SecondaryBusReset_OFFSET 22 +#define DxF0x3C_SecondaryBusReset_WIDTH 1 +#define DxF0x3C_SecondaryBusReset_MASK 0x400000 +#define DxF0x3C_FastB2BCap_OFFSET 23 +#define DxF0x3C_FastB2BCap_WIDTH 1 +#define DxF0x3C_FastB2BCap_MASK 0x800000 +#define DxF0x3C_Reserved_31_24_OFFSET 24 +#define DxF0x3C_Reserved_31_24_WIDTH 8 +#define DxF0x3C_Reserved_31_24_MASK 0xff000000 + +/// DxF0x3C +typedef union { + struct { ///< + UINT32 IntLine:8 ; ///< + UINT32 IntPin:3 ; ///< + UINT32 IntPinR:5 ; ///< + UINT32 ParityResponseEn:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 IsaEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 MasterAbortMode:1 ; ///< + UINT32 SecondaryBusReset:1 ; ///< + UINT32 FastB2BCap:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x3C_STRUCT; + +// **** DxF0x58 Register Definition **** +// Address +#define DxF0x58_ADDRESS 0x58 + +// Type +#define DxF0x58_TYPE TYPE_D4F0 +// Field Data +#define DxF0x58_CapID_OFFSET 0 +#define DxF0x58_CapID_WIDTH 8 +#define DxF0x58_CapID_MASK 0xff +#define DxF0x58_NextPtr_OFFSET 8 +#define DxF0x58_NextPtr_WIDTH 8 +#define DxF0x58_NextPtr_MASK 0xff00 +#define DxF0x58_Version_OFFSET 16 +#define DxF0x58_Version_WIDTH 4 +#define DxF0x58_Version_MASK 0xf0000 +#define DxF0x58_DeviceType_OFFSET 20 +#define DxF0x58_DeviceType_WIDTH 4 +#define DxF0x58_DeviceType_MASK 0xf00000 +#define DxF0x58_SlotImplemented_OFFSET 24 +#define DxF0x58_SlotImplemented_WIDTH 1 +#define DxF0x58_SlotImplemented_MASK 0x1000000 +#define DxF0x58_IntMessageNum_OFFSET 25 +#define DxF0x58_IntMessageNum_WIDTH 5 +#define DxF0x58_IntMessageNum_MASK 0x3e000000 +#define DxF0x58_Reserved_31_30_OFFSET 30 +#define DxF0x58_Reserved_31_30_WIDTH 2 +#define DxF0x58_Reserved_31_30_MASK 0xc0000000 + +/// DxF0x58 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:4 ; ///< + UINT32 DeviceType:4 ; ///< + UINT32 SlotImplemented:1 ; ///< + UINT32 IntMessageNum:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x58_STRUCT; + +// **** DxFxx68 Register Definition **** +// Address +#define DxFxx68_ADDRESS 0x68 +// Type +#define DxFxx68_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx68_PmControl_OFFSET 0 +#define DxFxx68_PmControl_WIDTH 2 +#define DxFxx68_PmControl_MASK 0x3 +#define DxFxx68_Reserved_2_2_OFFSET 2 +#define DxFxx68_Reserved_2_2_WIDTH 1 +#define DxFxx68_Reserved_2_2_MASK 0x4 +#define DxFxx68_ReadCplBoundary_OFFSET 3 +#define DxFxx68_ReadCplBoundary_WIDTH 1 +#define DxFxx68_ReadCplBoundary_MASK 0x8 +#define DxFxx68_LinkDis_OFFSET 4 +#define DxFxx68_LinkDis_WIDTH 1 +#define DxFxx68_LinkDis_MASK 0x10 +#define DxFxx68_RetrainLink_OFFSET 5 +#define DxFxx68_RetrainLink_WIDTH 1 +#define DxFxx68_RetrainLink_MASK 0x20 +#define DxFxx68_CommonClockCfg_OFFSET 6 +#define DxFxx68_CommonClockCfg_WIDTH 1 +#define DxFxx68_CommonClockCfg_MASK 0x40 +#define DxFxx68_ExtendedSync_OFFSET 7 +#define DxFxx68_ExtendedSync_WIDTH 1 +#define DxFxx68_ExtendedSync_MASK 0x80 +#define DxFxx68_ClockPowerManagementEn_OFFSET 8 +#define DxFxx68_ClockPowerManagementEn_WIDTH 1 +#define DxFxx68_ClockPowerManagementEn_MASK 0x100 +#define DxFxx68_HWAutonomousWidthDisable_OFFSET 9 +#define DxFxx68_HWAutonomousWidthDisable_WIDTH 1 +#define DxFxx68_HWAutonomousWidthDisable_MASK 0x200 +#define DxFxx68_LinkBWManagementEn_OFFSET 10 +#define DxFxx68_LinkBWManagementEn_WIDTH 1 +#define DxFxx68_LinkBWManagementEn_MASK 0x400 +#define DxFxx68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxFxx68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxFxx68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxFxx68_Reserved_15_12_OFFSET 12 +#define DxFxx68_Reserved_15_12_WIDTH 4 +#define DxFxx68_Reserved_15_12_MASK 0xF000 +#define DxFxx68_LinkSpeed_OFFSET 16 +#define DxFxx68_LinkSpeed_WIDTH 4 +#define DxFxx68_LinkSpeed_MASK 0xF0000 +#define DxFxx68_NegotiatedLinkWidth_OFFSET 20 +#define DxFxx68_NegotiatedLinkWidth_WIDTH 6 +#define DxFxx68_NegotiatedLinkWidth_MASK 0x3F00000 +#define DxFxx68_Reserved_26_26_OFFSET 26 +#define DxFxx68_Reserved_26_26_WIDTH 1 +#define DxFxx68_Reserved_26_26_MASK 0x4000000 +#define DxFxx68_LinkTraining_OFFSET 27 +#define DxFxx68_LinkTraining_WIDTH 1 +#define DxFxx68_LinkTraining_MASK 0x8000000 +#define DxFxx68_SlotClockCfg_OFFSET 28 +#define DxFxx68_SlotClockCfg_WIDTH 1 +#define DxFxx68_SlotClockCfg_MASK 0x10000000 +#define DxFxx68_DlActive_OFFSET 29 +#define DxFxx68_DlActive_WIDTH 1 +#define DxFxx68_DlActive_MASK 0x20000000 +#define DxFxx68_LinkBWManagementStatus_OFFSET 30 +#define DxFxx68_LinkBWManagementStatus_WIDTH 1 +#define DxFxx68_LinkBWManagementStatus_MASK 0x40000000 +#define DxFxx68_LinkAutonomousBWStatus_OFFSET 31 +#define DxFxx68_LinkAutonomousBWStatus_WIDTH 1 +#define DxFxx68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxFxx68 +typedef union { + struct { ///< + UINT32 PmControl:2; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 ReadCplBoundary:1; ///< + UINT32 LinkDis:1; ///< + UINT32 RetrainLink:1; ///< + UINT32 CommonClockCfg:1; ///< + UINT32 ExtendedSync:1; ///< + UINT32 ClockPowerManagementEn:1; ///< + UINT32 HWAutonomousWidthDisable:1; ///< + UINT32 LinkBWManagementEn:1; ///< + UINT32 LinkAutonomousBWIntEn:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 LinkSpeed:4; ///< + UINT32 NegotiatedLinkWidth:6; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 LinkTraining:1; ///< + UINT32 SlotClockCfg:1; ///< + UINT32 DlActive:1; ///< + UINT32 LinkBWManagementStatus:1; ///< + UINT32 LinkAutonomousBWStatus:1; ///< + + } Field; + + UINT32 Value; +} DxFxx68_STRUCT; + +// **** D0F0x7C Register Definition **** +// Address +#define D0F0x7C_ADDRESS 0x7C +// Type +#define D0F0x7C_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x7C_ForceIntGfxDisable_OFFSET 0 +#define D0F0x7C_ForceIntGfxDisable_WIDTH 1 +#define D0F0x7C_ForceIntGfxDisable_MASK 0x1 +#define D0F0x7C_Reserved_31_1_OFFSET 1 +#define D0F0x7C_Reserved_31_1_WIDTH 31 +#define D0F0x7C_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0x7C +typedef union { + struct { ///< + UINT32 ForceIntGfxDisable:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0x7C_STRUCT; + +// **** D0F0x98 Register Definition **** +// Address +#define D0F0x98_ADDRESS 0x98 +// Type +#define D0F0x98_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x98_OrbIndData_OFFSET 0 +#define D0F0x98_OrbIndData_WIDTH 32 +#define D0F0x98_OrbIndData_MASK 0xFFFFFFFF + +/// D0F0x98 +typedef union { + struct { ///< + UINT32 OrbIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0x98_STRUCT; + +// **** D0F0xBC Register Definition **** +// Address +#define D0F0xBC_ADDRESS 0xBC +// Type +#define D0F0xBC_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xBC_NbSmuIndData_OFFSET 0 +#define D0F0xBC_NbSmuIndData_WIDTH 32 +#define D0F0xBC_NbSmuIndData_MASK 0xFFFFFFFF + +/// D0F0xBC +typedef union { + struct { ///< + UINT32 NbSmuIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xBC_STRUCT; + +// **** D0F0xC8 Register Definition **** +// Address +#define D0F0xC8_ADDRESS 0xC8 +// Type +#define D0F0xC8_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xC8_NbDevIndAddr_OFFSET 0 +#define D0F0xC8_NbDevIndAddr_WIDTH 7 +#define D0F0xC8_NbDevIndAddr_MASK 0x7F +#define D0F0xC8_Reserved_15_7_OFFSET 7 +#define D0F0xC8_Reserved_15_7_WIDTH 9 +#define D0F0xC8_Reserved_15_7_MASK 0xFF80 +#define D0F0xC8_NbDevIndSel_OFFSET 16 +#define D0F0xC8_NbDevIndSel_WIDTH 8 +#define D0F0xC8_NbDevIndSel_MASK 0xFF0000 +#define D0F0xC8_Reserved_31_24_OFFSET 24 +#define D0F0xC8_Reserved_31_24_WIDTH 8 +#define D0F0xC8_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xC8 +typedef union { + struct { ///< + UINT32 NbDevIndAddr:7; ///< + UINT32 Reserved_15_7:9; ///< + UINT32 NbDevIndSel:8; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xC8_STRUCT; + +// **** D0F0xCC Register Definition **** +// Address +#define D0F0xCC_ADDRESS 0xCC +// Type +#define D0F0xCC_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xCC_NbDevIndData_OFFSET 0 +#define D0F0xCC_NbDevIndData_WIDTH 32 +#define D0F0xCC_NbDevIndData_MASK 0xFFFFFFFF + +/// D0F0xCC +typedef union { + struct { ///< + UINT32 NbDevIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xCC_STRUCT; + +// **** D0F0xE4 Register Definition **** +// Address +#define D0F0xE4_ADDRESS 0xE4 +// Type +#define D0F0xE4_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xE4_PcieIndxData_OFFSET 0 +#define D0F0xE4_PcieIndxData_WIDTH 32 +#define D0F0xE4_PcieIndxData_MASK 0xFFFFFFFF + +/// D0F0xE4 +typedef union { + struct { ///< + UINT32 PcieIndxData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_STRUCT; + +// **** DxFxxE4_x6A Register Definition **** +// Address +#define DxFxxE4_x6A_ADDRESS 0x6A +// Type +#define DxFxxE4_x6A_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_x6A_ErrReportingDis_OFFSET 0 +#define DxFxxE4_x6A_ErrReportingDis_WIDTH 1 +#define DxFxxE4_x6A_ErrReportingDis_MASK 0x1 + +// **** DxFxxE4_xA2 Register Definition **** +// Address +#define DxFxxE4_xA2_ADDRESS 0xA2 +// Type +#define DxFxxE4_xA2_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA2_LcLinkWidth_OFFSET 0 +#define DxFxxE4_xA2_LcLinkWidth_WIDTH 3 +#define DxFxxE4_xA2_LcLinkWidth_MASK 0x7 +#define DxFxxE4_xA2_Reserved_3_3_OFFSET 3 +#define DxFxxE4_xA2_Reserved_3_3_WIDTH 1 +#define DxFxxE4_xA2_Reserved_3_3_MASK 0x8 +#define DxFxxE4_xA2_LcLinkWidthRd_OFFSET 4 +#define DxFxxE4_xA2_LcLinkWidthRd_WIDTH 3 +#define DxFxxE4_xA2_LcLinkWidthRd_MASK 0x70 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 +#define DxFxxE4_xA2_LcReconfigNow_OFFSET 8 +#define DxFxxE4_xA2_LcReconfigNow_WIDTH 1 +#define DxFxxE4_xA2_LcReconfigNow_MASK 0x100 +#define DxFxxE4_xA2_LcRenegotiationSupport_OFFSET 9 +#define DxFxxE4_xA2_LcRenegotiationSupport_WIDTH 1 +#define DxFxxE4_xA2_LcRenegotiationSupport_MASK 0x200 +#define DxFxxE4_xA2_LcRenegotiateEn_OFFSET 10 +#define DxFxxE4_xA2_LcRenegotiateEn_WIDTH 1 +#define DxFxxE4_xA2_LcRenegotiateEn_MASK 0x400 +#define DxFxxE4_xA2_LcShortReconfigEn_OFFSET 11 +#define DxFxxE4_xA2_LcShortReconfigEn_WIDTH 1 +#define DxFxxE4_xA2_LcShortReconfigEn_MASK 0x800 +#define DxFxxE4_xA2_LcUpconfigureSupport_OFFSET 12 +#define DxFxxE4_xA2_LcUpconfigureSupport_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigureSupport_MASK 0x1000 +#define DxFxxE4_xA2_LcUpconfigureDis_OFFSET 13 +#define DxFxxE4_xA2_LcUpconfigureDis_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigureDis_MASK 0x2000 +#define DxFxxE4_xA2_Reserved_19_14_OFFSET 14 +#define DxFxxE4_xA2_Reserved_19_14_WIDTH 6 +#define DxFxxE4_xA2_Reserved_19_14_MASK 0xFC000 +#define DxFxxE4_xA2_LcUpconfigCapable_OFFSET 20 +#define DxFxxE4_xA2_LcUpconfigCapable_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigCapable_MASK 0x100000 +#define DxFxxE4_xA2_LcDynLanesPwrState_OFFSET 21 +#define DxFxxE4_xA2_LcDynLanesPwrState_WIDTH 2 +#define DxFxxE4_xA2_LcDynLanesPwrState_MASK 0x600000 +#define DxFxxE4_xA2_Reserved_31_23_OFFSET 23 +#define DxFxxE4_xA2_Reserved_31_23_WIDTH 9 +#define DxFxxE4_xA2_Reserved_31_23_MASK 0xFF800000 + +/// DxFxxE4_xA2 +typedef union { + struct { ///< + UINT32 LcLinkWidth:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 LcLinkWidthRd:3; ///< + UINT32 LcReconfigArcMissingEscape:1; ///< + UINT32 LcReconfigNow:1; ///< + UINT32 LcRenegotiationSupport:1; ///< + UINT32 LcRenegotiateEn:1; ///< + UINT32 LcShortReconfigEn:1; ///< + UINT32 LcUpconfigureSupport:1; ///< + UINT32 LcUpconfigureDis:1; ///< + UINT32 Reserved_19_14:6; ///< + UINT32 LcUpconfigCapable:1; ///< + UINT32 LcDynLanesPwrState:2; ///< + UINT32 Reserved_31_23:9; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA2_STRUCT; + +// **** DxFxx128 Register Definition **** +// Address +#define DxFxx128_ADDRESS 0x128 +// Type +#define DxFxx128_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx128_Reserved_15_0_OFFSET 0 +#define DxFxx128_Reserved_15_0_WIDTH 16 +#define DxFxx128_Reserved_15_0_MASK 0xFFFF +#define DxFxx128_PortArbTableStatus_OFFSET 16 +#define DxFxx128_PortArbTableStatus_WIDTH 1 +#define DxFxx128_PortArbTableStatus_MASK 0x10000 +#define DxFxx128_VcNegotiationPending_OFFSET 17 +#define DxFxx128_VcNegotiationPending_WIDTH 1 +#define DxFxx128_VcNegotiationPending_MASK 0x20000 +#define DxFxx128_Reserved_31_18_OFFSET 18 +#define DxFxx128_Reserved_31_18_WIDTH 14 +#define DxFxx128_Reserved_31_18_MASK 0xFFFC0000 + +/// DxFxx128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1; ///< + UINT32 VcNegotiationPending:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} DxFxx128_STRUCT; + +// **** D0F0x64_x0D Register Definition **** +// Address +#define D0F0x64_x0D_ADDRESS 0xD +// Type +#define D0F0x64_x0D_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET 0 +#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH 1 +#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK 0x1 +#define D0F0x64_x0D_Reserved_30_1_OFFSET 1 +#define D0F0x64_x0D_Reserved_30_1_WIDTH 30 +#define D0F0x64_x0D_Reserved_30_1_MASK 0x7FFFFFFE +#define D0F0x64_x0D_IommuDis_OFFSET 31 +#define D0F0x64_x0D_IommuDis_WIDTH 1 +#define D0F0x64_x0D_IommuDis_MASK 0x80000000 + +/// D0F0x64_x0D +typedef union { + struct { ///< + UINT32 PciDev0Fn2RegEn:1; ///< + UINT32 Reserved_30_1:30; ///< + UINT32 IommuDis:1; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x0D_STRUCT; + +// **** D0F0x64_x16 Register Definition **** +// Address +#define D0F0x64_x16_ADDRESS 0x16 + +// Type +#define D0F0x64_x16_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x16_AerUrMsgEn_OFFSET 0 +#define D0F0x64_x16_AerUrMsgEn_WIDTH 1 +#define D0F0x64_x16_AerUrMsgEn_MASK 0x1 +#define D0F0x64_x16_Reserved_31_1_OFFSET 1 +#define D0F0x64_x16_Reserved_31_1_WIDTH 31 +#define D0F0x64_x16_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x64_x16 +typedef union { + struct { ///< + UINT32 AerUrMsgEn:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x16_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1D +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x1D_Reserved_0_0_OFFSET 0 +#define D0F0x64_x1D_Reserved_0_0_WIDTH 1 +#define D0F0x64_x1D_Reserved_0_0_MASK 0x1 +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xFFFFFFF0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 VgaEn:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Vga16En:1; ///< + UINT32 Reserved_31_4:28; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x1D_STRUCT; + +// **** D0F0x64_x22 Register Definition **** +// Address +#define D0F0x64_x22_ADDRESS 0x22 +// Type +#define D0F0x64_x22_TYPE TYPE_D0F0x64 + + +// **** D0F0x64_x23 Register Definition **** +// Address +#define D0F0x64_x23_ADDRESS 0x23 +// Type +#define D0F0x64_x23_TYPE TYPE_D0F0x64 + + +// **** D0F0x64_x30 Register Definition **** +// Address +#define D0F0x64_x30_ADDRESS 0x30 +// Type +#define D0F0x64_x30_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x30_DevFnMap_OFFSET 0 +#define D0F0x64_x30_DevFnMap_WIDTH 8 +#define D0F0x64_x30_DevFnMap_MASK 0xFF +#define D0F0x64_x30_Reserved_31_8_OFFSET 8 +#define D0F0x64_x30_Reserved_31_8_WIDTH 24 +#define D0F0x64_x30_Reserved_31_8_MASK 0xFFFFFF00 + +/// D0F0x64_x30 +typedef union { + struct { ///< + UINT32 DevFnMap:8; ///< + UINT32 Reserved_31_8:24; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x30_STRUCT; + +// **** D0F0x64_x46 Register Definition **** +// Address +#define D0F0x64_x46_ADDRESS 0x46 +// Type +#define D0F0x64_x46_TYPE TYPE_D0F0x64 + + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + +// **** D0F0x98_x07 Register Definition **** +// Address +#define D0F0x98_x07_ADDRESS 0x7 +// Type +#define D0F0x98_x07_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x07_IocBwOptEn_OFFSET 0 +#define D0F0x98_x07_IocBwOptEn_WIDTH 1 +#define D0F0x98_x07_IocBwOptEn_MASK 0x1 +#define D0F0x98_x07_IocWrROMapDis_OFFSET 1 +#define D0F0x98_x07_IocWrROMapDis_WIDTH 1 +#define D0F0x98_x07_IocWrROMapDis_MASK 0x2 +#define D0F0x98_x07_IocRdROMapDis_OFFSET 2 +#define D0F0x98_x07_IocRdROMapDis_WIDTH 1 +#define D0F0x98_x07_IocRdROMapDis_MASK 0x4 +#define D0F0x98_x07_Reserved_3_3_OFFSET 3 +#define D0F0x98_x07_Reserved_3_3_WIDTH 1 +#define D0F0x98_x07_Reserved_3_3_MASK 0x8 +#define D0F0x98_x07_IommuBwOptEn_OFFSET 4 +#define D0F0x98_x07_IommuBwOptEn_WIDTH 1 +#define D0F0x98_x07_IommuBwOptEn_MASK 0x10 +#define D0F0x98_x07_Reserved_5_5_OFFSET 5 +#define D0F0x98_x07_Reserved_5_5_WIDTH 1 +#define D0F0x98_x07_Reserved_5_5_MASK 0x20 +#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET 6 +#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH 1 +#define D0F0x98_x07_DmaReqRespPassPWMode_MASK 0x40 +#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET 7 +#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH 1 +#define D0F0x98_x07_IommuIsocPassPWMode_MASK 0x80 +#define D0F0x98_x07_Reserved_14_8_OFFSET 8 +#define D0F0x98_x07_Reserved_14_8_WIDTH 7 +#define D0F0x98_x07_Reserved_14_8_MASK 0x7F00 +#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 +#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 +#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 +#define D0F0x98_x07_SyncFloodOnParityErr_OFFSET 16 +#define D0F0x98_x07_SyncFloodOnParityErr_WIDTH 1 +#define D0F0x98_x07_SyncFloodOnParityErr_MASK 0x10000 +#define D0F0x98_x07_Reserved_30_17_OFFSET 17 +#define D0F0x98_x07_Reserved_30_17_WIDTH 14 +#define D0F0x98_x07_Reserved_30_17_MASK 0x7FFE0000 +#define D0F0x98_x07_SMUCsrIsocEn_OFFSET 31 +#define D0F0x98_x07_SMUCsrIsocEn_WIDTH 1 +#define D0F0x98_x07_SMUCsrIsocEn_MASK 0x80000000 + +/// D0F0x98_x07 +typedef union { + struct { ///< + UINT32 IocBwOptEn:1; ///< + UINT32 IocWrROMapDis:1; ///< + UINT32 IocRdROMapDis:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 IommuBwOptEn:1; ///< + UINT32 Reserved_5_5:1; ///< + UINT32 DmaReqRespPassPWMode:1; ///< + UINT32 IommuIsocPassPWMode:1; ///< + UINT32 Reserved_14_8:7; ///< + UINT32 DropZeroMaskWrEn:1; ///< + UINT32 SyncFloodOnParityErr:1; ///< + UINT32 Reserved_30_17:14; ///< + UINT32 SMUCsrIsocEn:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x07_STRUCT; + +// **** D0F0x98_x08 Register Definition **** +// Address +#define D0F0x98_x08_ADDRESS 0x8 +// Type +#define D0F0x98_x08_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x08_NpWrrLenA_OFFSET 0 +#define D0F0x98_x08_NpWrrLenA_WIDTH 8 +#define D0F0x98_x08_NpWrrLenA_MASK 0xFF +#define D0F0x98_x08_NpWrrLenB_OFFSET 8 +#define D0F0x98_x08_NpWrrLenB_WIDTH 8 +#define D0F0x98_x08_NpWrrLenB_MASK 0xFF00 +#define D0F0x98_x08_NpWrrLenC_OFFSET 16 +#define D0F0x98_x08_NpWrrLenC_WIDTH 8 +#define D0F0x98_x08_NpWrrLenC_MASK 0xFF0000 +#define D0F0x98_x08_Reserved_31_24_OFFSET 24 +#define D0F0x98_x08_Reserved_31_24_WIDTH 8 +#define D0F0x98_x08_Reserved_31_24_MASK 0xFF000000 + +/// D0F0x98_x08 +typedef union { + struct { ///< + UINT32 NpWrrLenA:8; ///< + UINT32 NpWrrLenB:8; ///< + UINT32 NpWrrLenC:8; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x08_STRUCT; + +// **** D0F0x98_x0C Register Definition **** +// Address +#define D0F0x98_x0C_ADDRESS 0xC +// Type +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 +#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenA_MASK 0xFF +#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 +#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenB_MASK 0xFF00 +#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 +#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 +#define D0F0x98_x0C_Reserved_29_16_MASK 0x3FFF0000 +#define D0F0x98_x0C_Reserved_31_31_OFFSET 31 +#define D0F0x98_x0C_Reserved_31_31_WIDTH 1 +#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x0C +typedef union { + struct { ///< + UINT32 GcmWrrLenA:8; ///< + UINT32 GcmWrrLenB:8; ///< + UINT32 Reserved_29_16:14; ///< + UINT32 Reserved_30_30:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x0C_STRUCT; + +// **** D0F0x98_x1E Register Definition **** +// Address +#define D0F0x98_x1E_ADDRESS 0x1E +// Type +#define D0F0x98_x1E_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 +#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 +#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 +#define D0F0x98_x1E_HiPriEn_OFFSET 1 +#define D0F0x98_x1E_HiPriEn_WIDTH 1 +#define D0F0x98_x1E_HiPriEn_MASK 0x2 +#define D0F0x98_x1E_Reserved_23_2_OFFSET 2 +#define D0F0x98_x1E_Reserved_23_2_WIDTH 22 +#define D0F0x98_x1E_Reserved_23_2_MASK 0xFFFFFC +#define D0F0x98_x1E_RxErrStatusDelay_OFFSET 24 +#define D0F0x98_x1E_RxErrStatusDelay_WIDTH 8 +#define D0F0x98_x1E_RxErrStatusDelay_MASK 0xFF000000 + +/// D0F0x98_x1E +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 HiPriEn:1; ///< + UINT32 Reserved_23_2:22; ///< + UINT32 RxErrStatusDelay:8; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x1E_STRUCT; + +// **** D0F0x98_x28 Register Definition **** +// Address +#define D0F0x98_x28_ADDRESS 0x28 +// Type +#define D0F0x98_x28_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x28_Reserved_0_0_OFFSET 0 +#define D0F0x98_x28_Reserved_0_0_WIDTH 1 +#define D0F0x98_x28_Reserved_0_0_MASK 0x1 +#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 +#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 +#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 +#define D0F0x98_x28_Reserved_31_2_OFFSET 2 +#define D0F0x98_x28_Reserved_31_2_WIDTH 30 +#define D0F0x98_x28_Reserved_31_2_MASK 0xFFFFFFFC + +/// D0F0x98_x28 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 ForceCoherentIntr:1; ///< + UINT32 Reserved_31_2:30; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x28_STRUCT; + +// **** D0F0x98_x2C Register Definition **** +// Address +#define D0F0x98_x2C_ADDRESS 0x2C +// Type +#define D0F0x98_x2C_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 +#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 +#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 +#define D0F0x98_x2C_DynWakeEn_OFFSET 1 +#define D0F0x98_x2C_DynWakeEn_WIDTH 1 +#define D0F0x98_x2C_DynWakeEn_MASK 0x2 +#define D0F0x98_x2C_CgttLclkOverride_OFFSET 2 +#define D0F0x98_x2C_CgttLclkOverride_WIDTH 1 +#define D0F0x98_x2C_CgttLclkOverride_MASK 0x4 +#define D0F0x98_x2C_Reserved_8_3_OFFSET 3 +#define D0F0x98_x2C_Reserved_8_3_WIDTH 6 +#define D0F0x98_x2C_Reserved_8_3_MASK 0x1F8 +#define D0F0x98_x2C_SBDmaActiveMask_OFFSET 9 +#define D0F0x98_x2C_SBDmaActiveMask_WIDTH 1 +#define D0F0x98_x2C_SBDmaActiveMask_MASK 0x200 +#define D0F0x98_x2C_Reserved_15_10_OFFSET 10 +#define D0F0x98_x2C_Reserved_15_10_WIDTH 6 +#define D0F0x98_x2C_Reserved_15_10_MASK 0xFC00 +#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 +#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 +#define D0F0x98_x2C_WakeHysteresis_MASK 0xFFFF0000 + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 DynWakeEn:1; ///< + UINT32 CgttLclkOverride:1; ///< + UINT32 Reserved_8_3:6; ///< + UINT32 SBDmaActiveMask:1; ///< + UINT32 Reserved_15_10:6; ///< + UINT32 WakeHysteresis:16; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x2C_STRUCT; + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3A +// Type +#define D0F0x98_x3A_TYPE TYPE_D0F0x98 + +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x49_Reserved_23_0_OFFSET 0 +#define D0F0x98_x49_Reserved_23_0_WIDTH 24 +#define D0F0x98_x49_Reserved_23_0_MASK 0xFFFFFF +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1; ///< + UINT32 SoftOverrideClk5:1; ///< + UINT32 SoftOverrideClk4:1; ///< + UINT32 SoftOverrideClk3:1; ///< + UINT32 SoftOverrideClk2:1; ///< + UINT32 SoftOverrideClk1:1; ///< + UINT32 SoftOverrideClk0:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4A +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x4A_Reserved_23_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_23_0_WIDTH 24 +#define D0F0x98_x4A_Reserved_23_0_MASK 0xFFFFFF +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1; ///< + UINT32 SoftOverrideClk5:1; ///< + UINT32 SoftOverrideClk4:1; ///< + UINT32 SoftOverrideClk3:1; ///< + UINT32 SoftOverrideClk2:1; ///< + UINT32 SoftOverrideClk1:1; ///< + UINT32 SoftOverrideClk0:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x4A_STRUCT; + + + + + + + + + + + +/// D0F0xBC_x3FA04 +typedef union { + struct { ///< + UINT32 Bitfield_15_0:16; ///< + UINT32 Bitfield_31_16:16; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4753_STRUCT; + +// **** D0F0xE4_PHY_0004 Register Definition **** +// Address +#define D0F0xE4_PHY_0004_ADDRESS 0x0004 +// Type +#define D0F0xE4_PHY_0004_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_0004_Reserved_15_0_OFFSET 0 +#define D0F0xE4_PHY_0004_Reserved_15_0_WIDTH 16 +#define D0F0xE4_PHY_0004_Reserved_15_0_MASK 0xFFFF +#define D0F0xE4_PHY_0004_CfgIdleDetTh_OFFSET 16 +#define D0F0xE4_PHY_0004_CfgIdleDetTh_WIDTH 2 +#define D0F0xE4_PHY_0004_CfgIdleDetTh_MASK 0x30000 +#define D0F0xE4_PHY_0004_Reserved_31_18_OFFSET 18 +#define D0F0xE4_PHY_0004_Reserved_31_18_WIDTH 14 +#define D0F0xE4_PHY_0004_Reserved_31_18_MASK 0xFFFC0000 + +/// D0F0xE4_PHY_0004 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 CfgIdleDetTh:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_0004_STRUCT; + +// **** D0F0xE4_PHY_4440 Register Definition **** +// Address +#define D0F0xE4_PHY_4440_ADDRESS 0x4440 +// Type +#define D0F0xE4_PHY_4440_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_4440_Reserved_12_0_OFFSET 0 +#define D0F0xE4_PHY_4440_Reserved_12_0_WIDTH 13 +#define D0F0xE4_PHY_4440_Reserved_12_0_MASK 0x1FFF +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_OFFSET 13 +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_WIDTH 2 +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK 0x6000 +#define D0F0xE4_PHY_4440_Reserved_31_15_OFFSET 15 +#define D0F0xE4_PHY_4440_Reserved_31_15_WIDTH 17 +#define D0F0xE4_PHY_4440_Reserved_31_15_MASK 0xFFFF1000 + +/// D0F0xE4_PHY_4440 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 PllDbgRoIPFDResetCntrl:2 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_4440_STRUCT; + +// **** D0F0xE4_PHY_4450 Register Definition **** +// Address +#define D0F0xE4_PHY_4450_ADDRESS 0x4450 +// Type +#define D0F0xE4_PHY_4450_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_OFFSET 0 +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_WIDTH 8 +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_MASK 0xFF +#define D0F0xE4_PHY_4450_Reserved_29_8_OFFSET 8 +#define D0F0xE4_PHY_4450_Reserved_29_8_WIDTH 22 +#define D0F0xE4_PHY_4450_Reserved_29_8_MASK 0x3FFFFF00 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_OFFSET 30 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_WIDTH 1 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_MASK 0x40000000 +#define D0F0xE4_PHY_4450_Reserved_31_31_OFFSET 31 +#define D0F0xE4_PHY_4450_Reserved_31_31_WIDTH 1 +#define D0F0xE4_PHY_4450_Reserved_31_31_MASK 0x80000000 + +/// D0F0xE4_PHY_4450 +typedef union { + struct { ///< + UINT32 PllCfgROBWCntrlOvrdVal0:8 ; ///< + UINT32 Reserved_29_8:22; ///< + UINT32 PllCfgROVTOIBiasCntrlOvrdVal0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_4450_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_0800_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24; + + } Field; + + UINT32 Value; +} GnbRegistersKB4915_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4940_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4965_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4990_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB5015_STRUCT; + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xFC00 +#define D0F0xE4_WRAP_8011_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8011_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7E0000 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_WRAP_8011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6; ///< + UINT32 TxclkPermGateEven:1; ///< + UINT32 TxclkDynGateEnable:1; ///< + UINT32 TxclkPermStop:1; ///< + UINT32 TxclkRegsGateEnable:1; ///< + UINT32 TxclkRegsGateLatency:6; ///< + UINT32 Reserved_16_16:1; ///< + UINT32 TxclkPermGateLatency:6; ///< + UINT32 Bitfield_23_23:1; ///< + UINT32 TxclkLcntGateEnable:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3F00 +#define D0F0xE4_WRAP_8012_Reserved_31_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_31_14_WIDTH 18 +#define D0F0xE4_WRAP_8012_Reserved_31_14_MASK 0xFFFFC000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6; ///< + UINT32 Reserved_6_6:1; ///< + UINT32 Pif1xIdleGateEnable:1; ///< + UINT32 Pif1xIdleResumeLatency:6; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8012_STRUCT; + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 +// Type +#define D0F0xE4_WRAP_8013_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_OFFSET 1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_OFFSET 5 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_OFFSET 10 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_OFFSET 13 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_WIDTH 2 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_MASK 0x6000 +#define D0F0xE4_WRAP_8013_Reserved_31_15_OFFSET 15 +#define D0F0xE4_WRAP_8013_Reserved_31_15_WIDTH 17 +#define D0F0xE4_WRAP_8013_Reserved_31_15_MASK 0xFFFF8000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1; ///< + UINT32 MasterPciePllB:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 ClkDividerResetOverrideA:1; ///< + UINT32 ClkDividerResetOverrideB:1; ///< + UINT32 Reserved_6_6:1; ///< + UINT32 Reserved_7_7:1; ///< + UINT32 TxclkSelCoreOverride:1; ///< + UINT32 TxclkSelPifAOverride:1; ///< + UINT32 TxclkSelPifBOverride:1; ///< + UINT32 Reserved_11_11:1; ///< + UINT32 Reserved_12_12:1; ///< + UINT32 PhyRxIsoDis:2; ///< + UINT32 Reserved_31_15:17; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 +// Type +#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_11_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_WIDTH 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_MASK 0xFC0 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_Reserved_19_16_OFFSET 16 +#define D0F0xE4_WRAP_8014_Reserved_19_16_WIDTH 4 +#define D0F0xE4_WRAP_8014_Reserved_19_16_MASK 0xF0000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3 +#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xE00000 +#define D0F0xE4_WRAP_8014_Reserved_24_24_OFFSET 24 +#define D0F0xE4_WRAP_8014_Reserved_24_24_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_24_24_MASK 0x1000000 +#define D0F0xE4_WRAP_8014_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8014_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8014_Reserved_26_26_OFFSET 26 +#define D0F0xE4_WRAP_8014_Reserved_26_26_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_26_26_MASK 0x4000000 +#define D0F0xE4_WRAP_8014_Reserved_27_27_OFFSET 27 +#define D0F0xE4_WRAP_8014_Reserved_27_27_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28 +#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4 +#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xF0000000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1; ///< + UINT32 TxclkPrbsGateEnable:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 Reserved_4_4:1; ///< + UINT32 Reserved_5_5:1; ///< + UINT32 Reserved_11_6:6; ///< + UINT32 PcieGatePifA1xEnable:1; ///< + UINT32 PcieGatePifB1xEnable:1; ///< + UINT32 Reserved_14_14:1; ///< + UINT32 Reserved_15_15:1; ///< + UINT32 Reserved_19_16:4; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1; ///< + UINT32 Reserved_23_21:3; ///< + UINT32 Reserved_24_24:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 SpareRegRw:4; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8015 Register Definition **** +// Address +#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 +// Type +#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8015_Bitfield_0_0_OFFSET 0 +#define D0F0xE4_WRAP_8015_Bitfield_0_0_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_0_0_MASK 0x1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8015_Reserved_7_2_OFFSET 2 +#define D0F0xE4_WRAP_8015_Reserved_7_2_WIDTH 6 +#define D0F0xE4_WRAP_8015_Reserved_7_2_MASK 0xFC +#define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8015_Reserved_13_12_OFFSET 12 +#define D0F0xE4_WRAP_8015_Reserved_13_12_WIDTH 2 +#define D0F0xE4_WRAP_8015_Reserved_13_12_MASK 0x3000 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_MASK 0xC000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3F0000 +#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8015_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8015_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8015_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xE4_WRAP_8015 +typedef union { + struct { ///< + UINT32 Bitfield_0_0:1; ///< + UINT32 Reserved_1_1:1; ///< + UINT32 Reserved_7_2:6; ///< + UINT32 Reserved_8_8:1; ///< + UINT32 Bitfield_9_9:1; ///< + UINT32 Bitfield_10_10:1; ///< + UINT32 Bitfield_11_11:1; ///< + UINT32 Reserved_13_12:2; ///< + UINT32 Bitfield_15_14:2; ///< + UINT32 RefclkRegsGateLatency:6; ///< + UINT32 Reserved_22_22:1; ///< + UINT32 RefclkRegsGateEnable:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8015_STRUCT; + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3F +#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH 10 +#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK 0xFFC0 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3F0000 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 LclkDynGateLatency:6; ///< + UINT32 LclkGateFree:1; ///< + UINT32 LclkDynGateEnable:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8016_STRUCT; + +// **** D0F0xE4_WRAP_8029 Register Definition **** +// Address +#define D0F0xE4_WRAP_8029_ADDRESS 0x8029 +// Type +#define D0F0xE4_WRAP_8029_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8029_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8029_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8029_LaneEnable_MASK 0xFFFF +#define D0F0xE4_WRAP_8029_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_WRAP_8029 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8029_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_X2Lane98_OFFSET 4 +#define D0F0xE4_PIF_0011_X2Lane98_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane98_MASK 0x10 +#define D0F0xE4_PIF_0011_X2Lane1110_OFFSET 5 +#define D0F0xE4_PIF_0011_X2Lane1110_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1110_MASK 0x20 +#define D0F0xE4_PIF_0011_X2Lane1312_OFFSET 6 +#define D0F0xE4_PIF_0011_X2Lane1312_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1312_MASK 0x40 +#define D0F0xE4_PIF_0011_X2Lane1514_OFFSET 7 +#define D0F0xE4_PIF_0011_X2Lane1514_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1514_MASK 0x80 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_X4Lane118_OFFSET 10 +#define D0F0xE4_PIF_0011_X4Lane118_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane118_MASK 0x400 +#define D0F0xE4_PIF_0011_X4Lane1512_OFFSET 11 +#define D0F0xE4_PIF_0011_X4Lane1512_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane1512_MASK 0x800 +#define D0F0xE4_PIF_0011_Reserved_15_12_OFFSET 12 +#define D0F0xE4_PIF_0011_Reserved_15_12_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_15_12_MASK 0xF000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_X8Lane158_OFFSET 17 +#define D0F0xE4_PIF_0011_X8Lane158_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane158_MASK 0x20000 +#define D0F0xE4_PIF_0011_Reserved_19_18_OFFSET 18 +#define D0F0xE4_PIF_0011_Reserved_19_18_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_19_18_MASK 0xC0000 +#define D0F0xE4_PIF_0011_X16Lane150_OFFSET 20 +#define D0F0xE4_PIF_0011_X16Lane150_WIDTH 1 +#define D0F0xE4_PIF_0011_X16Lane150_MASK 0x100000 +#define D0F0xE4_PIF_0011_Reserved_24_21_OFFSET 21 +#define D0F0xE4_PIF_0011_Reserved_24_21_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_24_21_MASK 0x1E00000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1; ///< + UINT32 X2Lane32:1; ///< + UINT32 X2Lane54:1; ///< + UINT32 X2Lane76:1; ///< + UINT32 X2Lane98:1; ///< + UINT32 X2Lane1110:1; ///< + UINT32 X2Lane1312:1; ///< + UINT32 X2Lane1514:1; ///< + UINT32 X4Lane30:1; ///< + UINT32 X4Lane74:1; ///< + UINT32 X4Lane118:1; ///< + UINT32 X4Lane1512:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 X8Lane70:1; ///< + UINT32 X8Lane158:1; ///< + UINT32 Reserved_19_18:2; ///< + UINT32 X16Lane150:1; ///< + UINT32 Reserved_24_21:4; ///< + UINT32 MultiPif:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1C00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xE000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xFE0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xE0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3; ///< + UINT32 ForceRxEnInL0s:1; ///< + UINT32 RxPowerStateInRxs2:3; ///< + UINT32 PllPowerStateInTxs2:3; ///< + UINT32 PllPowerStateInOff:3; ///< + UINT32 Reserved_15_13:3; ///< + UINT32 Tx2p5clkClockGatingEn:1; ///< + UINT32 Reserved_23_17:7; ///< + UINT32 PllRampUpTime:3; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 PllPwrOverrideEn:1; ///< + UINT32 PllPwrOverrideVal:3; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_CORE_0002 Register Definition **** +// Address +#define D0F0xE4_CORE_0002_ADDRESS 0x0002 +// Type +#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0002_HwDebug_0_OFFSET 0 +#define D0F0xE4_CORE_0002_HwDebug_0_WIDTH 1 +#define D0F0xE4_CORE_0002_HwDebug_0_MASK 0x1 +#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 +#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 +#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_CORE_0002 +typedef union { + struct { ///< + UINT32 HwDebug_0:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0002_STRUCT; + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1FE +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK 0x1C00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xFFFFE000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1; ///< + UINT32 Reserved_8_1:8; ///< + UINT32 UmiNpMemWrite:1; ///< + UINT32 RxUmiAdjPayloadSize:3; ///< + UINT32 Reserved_31_13:19; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0010_STRUCT; + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 +// Type +#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xF +#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 +#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 +#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xFFFFFFF0 + +/// D0F0xE4_CORE_0011 +typedef union { + struct { ///< + UINT32 DynClkLatency:4; ///< + UINT32 Reserved_31_4:28; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0011_STRUCT; + +// **** D0F0xE4_CORE_001C Register Definition **** +// Address +#define D0F0xE4_CORE_001C_ADDRESS 0x1C +// Type +#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3E +#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 +#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7C0 +#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 +#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 +#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xFFFFF800 + +/// D0F0xE4_CORE_001C +typedef union { + struct { ///< + UINT32 TxArbRoundRobinEn:1; ///< + UINT32 TxArbSlvLimit:5; ///< + UINT32 TxArbMstLimit:5; ///< + UINT32 Reserved_31_11:21; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_001C_STRUCT; + +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x0020 +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH 8 +#define D0F0xE4_CORE_0020_Reserved_7_0_MASK 0xFF +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 +#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 +#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 +#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xFFFFFC00 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8; ///< + UINT32 CiSlvOrderingDis:1; ///< + UINT32 CiRcOrderingDis:1; ///< + UINT32 Reserved_31_10:22; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0020_STRUCT; + +// **** D0F0xE4_CORE_0040 Register Definition **** +// Address +#define D0F0xE4_CORE_0040_ADDRESS 0x40 +// Type +#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 +#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 +#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3FFF +#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 +#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 +#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xC000 +#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_CORE_0040 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 PElecIdleMode:2; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0040_STRUCT; + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xB0 +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 +#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 +#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xFFFFFFC0 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 StrapF0MsiEn:1; ///< + UINT32 Reserved_4_3:2; ///< + UINT32 StrapF0AerEn:1; ///< + UINT32 Reserved_31_6:26; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_00B0_STRUCT; + +// **** D0F0xE4_CORE_00C1 Register Definition **** +// Address +#define D0F0xE4_CORE_00C1_ADDRESS 0xC1 +// Type +#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 +#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xFFFFFFFC + +/// D0F0xE4_CORE_00C1 +typedef union { + struct { ///< + UINT32 StrapLinkBwNotificationCapEn:1; ///< + UINT32 StrapGen2Compliance:1; ///< + UINT32 Reserved_31_2:30; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_00C1_STRUCT; + +// **** DxFxxE4_x70 Register Definition **** +// Address +#define DxFxxE4_x70_ADDRESS 0x70 +// Type +#define DxFxxE4_x70_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_x70_Reserved_15_0_OFFSET 0 +#define DxFxxE4_x70_Reserved_15_0_WIDTH 16 +#define DxFxxE4_x70_Reserved_15_0_MASK 0xFFFF +#define DxFxxE4_x70_RxRcbCplTimeout_OFFSET 16 +#define DxFxxE4_x70_RxRcbCplTimeout_WIDTH 3 +#define DxFxxE4_x70_RxRcbCplTimeout_MASK 0x70000 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET 19 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH 1 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 +#define DxFxxE4_x70_Reserved_31_20_OFFSET 20 +#define DxFxxE4_x70_Reserved_31_20_WIDTH 12 +#define DxFxxE4_x70_Reserved_31_20_MASK 0xFFF00000 + +/// DxFxxE4_x70 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 RxRcbCplTimeout:3; ///< + UINT32 RxRcbCplTimeoutMode:1; ///< + UINT32 Reserved_31_20:12; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_x70_STRUCT; + +// **** DxFxxE4_xA0 Register Definition **** +// Address +#define DxFxxE4_xA0_ADDRESS 0xA0 +// Type +#define DxFxxE4_xA0_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA0_Reserved_3_0_OFFSET 0 +#define DxFxxE4_xA0_Reserved_3_0_WIDTH 4 +#define DxFxxE4_xA0_Reserved_3_0_MASK 0xF +#define DxFxxE4_xA0_Lc16xClearTxPipe_OFFSET 4 +#define DxFxxE4_xA0_Lc16xClearTxPipe_WIDTH 4 +#define DxFxxE4_xA0_Lc16xClearTxPipe_MASK 0xF0 +#define DxFxxE4_xA0_LcL0sInactivity_OFFSET 8 +#define DxFxxE4_xA0_LcL0sInactivity_WIDTH 4 +#define DxFxxE4_xA0_LcL0sInactivity_MASK 0xF00 +#define DxFxxE4_xA0_LcL1Inactivity_OFFSET 12 +#define DxFxxE4_xA0_LcL1Inactivity_WIDTH 4 +#define DxFxxE4_xA0_LcL1Inactivity_MASK 0xF000 +#define DxFxxE4_xA0_Reserved_22_16_OFFSET 16 +#define DxFxxE4_xA0_Reserved_22_16_WIDTH 7 +#define DxFxxE4_xA0_Reserved_22_16_MASK 0x7F0000 +#define DxFxxE4_xA0_LcL1ImmediateAck_OFFSET 23 +#define DxFxxE4_xA0_LcL1ImmediateAck_WIDTH 1 +#define DxFxxE4_xA0_LcL1ImmediateAck_MASK 0x800000 +#define DxFxxE4_xA0_Reserved_31_24_OFFSET 24 +#define DxFxxE4_xA0_Reserved_31_24_WIDTH 8 +#define DxFxxE4_xA0_Reserved_31_24_MASK 0xFF000000 + +/// DxFxxE4_xA0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4; ///< + UINT32 Lc16xClearTxPipe:4; ///< + UINT32 LcL0sInactivity:4; ///< + UINT32 LcL1Inactivity:4; ///< + UINT32 Reserved_22_16:7; ///< + UINT32 LcL1ImmediateAck:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA0_STRUCT; + +// **** DxFxxE4_xA1 Register Definition **** +// Address +#define DxFxxE4_xA1_ADDRESS 0xA1 +// Type +#define DxFxxE4_xA1_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA1_Reserved_10_0_OFFSET 0 +#define DxFxxE4_xA1_Reserved_10_0_WIDTH 11 +#define DxFxxE4_xA1_Reserved_10_0_MASK 0x7FF +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 +#define DxFxxE4_xA1_Reserved_31_12_OFFSET 12 +#define DxFxxE4_xA1_Reserved_31_12_WIDTH 20 +#define DxFxxE4_xA1_Reserved_31_12_MASK 0xFFFFF000 + +/// DxFxxE4_xA1 +typedef union { + struct { ///< + UINT32 Reserved_10_0:11; ///< + UINT32 LcDontGotoL0sifL1Armed:1; ///< + UINT32 Reserved_31_12:20; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA1_STRUCT; + +// **** DxFxxE4_xA3 Register Definition **** +// Address +#define DxFxxE4_xA3_ADDRESS 0xA3 +// Type +#define DxFxxE4_xA3_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA3_Reserved_8_0_OFFSET 0 +#define DxFxxE4_xA3_Reserved_8_0_WIDTH 9 +#define DxFxxE4_xA3_Reserved_8_0_MASK 0x1FF +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 +#define DxFxxE4_xA3_Reserved_31_10_OFFSET 10 +#define DxFxxE4_xA3_Reserved_31_10_WIDTH 22 +#define DxFxxE4_xA3_Reserved_31_10_MASK 0xFFFFFC00 + +/// DxFxxE4_xA3 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9; ///< + UINT32 LcXmitFtsBeforeRecovery:1; ///< + UINT32 Reserved_31_10:22; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA3_STRUCT; + +// **** DxFxxE4_xB1 Register Definition **** +// Address +#define DxFxxE4_xB1_ADDRESS 0xB1 +// Type +#define DxFxxE4_xB1_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xB1_Reserved_13_0_OFFSET 0 +#define DxFxxE4_xB1_Reserved_13_0_WIDTH 14 +#define DxFxxE4_xB1_Reserved_13_0_MASK 0x3FFF +#define DxFxxE4_xB1_LcElecIdleMode_OFFSET 14 +#define DxFxxE4_xB1_LcElecIdleMode_WIDTH 2 +#define DxFxxE4_xB1_LcElecIdleMode_MASK 0xc000 +#define DxFxxE4_xB1_Reserved_18_16_OFFSET 16 +#define DxFxxE4_xB1_Reserved_18_16_WIDTH 3 +#define DxFxxE4_xB1_Reserved_18_16_MASK 0x70000 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 +#define DxFxxE4_xB1_LcBlockElIdleinL0_OFFSET 20 +#define DxFxxE4_xB1_LcBlockElIdleinL0_WIDTH 1 +#define DxFxxE4_xB1_LcBlockElIdleinL0_MASK 0x100000 +#define DxFxxE4_xB1_Reserved_31_21_OFFSET 21 +#define DxFxxE4_xB1_Reserved_31_21_WIDTH 11 +#define DxFxxE4_xB1_Reserved_31_21_MASK 0xFFE00000 + +/// DxFxxE4_xB1 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 LcElecIdleMode:2 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 LcDeassertRxEnInL0s:1; ///< + UINT32 LcBlockElIdleinL0:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + UINT32 Value; +} DxFxxE4_xB1_STRUCT; + +// **** DxFxxE4_xC0 Register Definition **** +// Address +// Type +#define DxFxxE4_xC0_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xC0_Reserved_3_0_OFFSET 0 +#define DxFxxE4_xC0_Reserved_3_0_WIDTH 4 +#define DxFxxE4_xC0_Reserved_3_0_MASK 0xF +#define DxFxxE4_xC0_Reserved_12_6_OFFSET 6 +#define DxFxxE4_xC0_Reserved_12_6_WIDTH 7 +#define DxFxxE4_xC0_Reserved_12_6_MASK 0x1FC0 +#define DxFxxE4_xC0_StrapForceCompliance_OFFSET 13 +#define DxFxxE4_xC0_StrapForceCompliance_WIDTH 1 +#define DxFxxE4_xC0_StrapForceCompliance_MASK 0x2000 +#define DxFxxE4_xC0_Reserved_14_14_OFFSET 14 +#define DxFxxE4_xC0_Reserved_14_14_WIDTH 1 +#define DxFxxE4_xC0_Reserved_14_14_MASK 0x4000 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define DxFxxE4_xC0_Reserved_31_19_OFFSET 19 +#define DxFxxE4_xC0_Reserved_31_19_WIDTH 13 +#define DxFxxE4_xC0_Reserved_31_19_MASK 0xfff80000 + +/// DxFxxE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 StrapMedyTSxCount:2 ; ///< + UINT32 Reserved_12_6:7 ; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 StrapLaneNegotiation:3 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; + UINT32 Value; +} DxFxxE4_xC0_STRUCT; + + + + +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 bit2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 Reserved_7_4:4; ///< + UINT32 Reserved_8_8:1; ///< + UINT32 Reserved_31_9:23; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7208_STRUCT; + + +typedef union { + struct { ///< + UINT32 Reserved_16_0:17; ///< + UINT32 bit17:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} GnbRegistersKB7236_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 bit16:1; ///< + UINT32 Reserved_17_17:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7269_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_7_0:8; ///< + UINT32 StrapBifF0LegacyDeviceTypeDis:1; ///< + UINT32 Reserved_9_9:1; ///< + UINT32 bita:1; ///< + UINT32 Reserved_12_11:2; ///< + UINT32 bit13:1; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7314_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 bit_20:1; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} GnbRegistersKB7341_STRUCT; + + +// **** D0F0xD4_x010914E1 Register Definition **** +// Address +#define D0F0xD4_x010914E1_ADDRESS 0x10914E1 +// Type +#define D0F0xD4_x010914E1_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x010914E1_Reserved_0_0_OFFSET 0 +#define D0F0xD4_x010914E1_Reserved_0_0_WIDTH 1 +#define D0F0xD4_x010914E1_Reserved_0_0_MASK 0x1 +#define D0F0xD4_x010914E1_StrapBifRegApSize_OFFSET 1 +#define D0F0xD4_x010914E1_StrapBifRegApSize_WIDTH 2 +#define D0F0xD4_x010914E1_StrapBifRegApSize_MASK 0x6 +#define D0F0xD4_x010914E1_StrapBifMemApSize_OFFSET 3 +#define D0F0xD4_x010914E1_StrapBifMemApSize_WIDTH 3 +#define D0F0xD4_x010914E1_StrapBifMemApSize_MASK 0x38 +#define D0F0xD4_x010914E1_Reserved_11_6_OFFSET 6 +#define D0F0xD4_x010914E1_Reserved_11_6_WIDTH 6 +#define D0F0xD4_x010914E1_Reserved_11_6_MASK 0xFC0 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_OFFSET 12 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_WIDTH 1 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_MASK 0x1000 +#define D0F0xD4_x010914E1_Bitfield_13_13_OFFSET 13 +#define D0F0xD4_x010914E1_Bitfield_13_13_WIDTH 1 +#define D0F0xD4_x010914E1_Bitfield_13_13_MASK 0x2000 +#define D0F0xD4_x010914E1_Bitfield_15_14_OFFSET 14 +#define D0F0xD4_x010914E1_Bitfield_15_14_WIDTH 2 +#define D0F0xD4_x010914E1_Bitfield_15_14_MASK 0xC000 +#define D0F0xD4_x010914E1_Reserved_31_13_OFFSET 16 +#define D0F0xD4_x010914E1_Reserved_31_13_WIDTH 16 +#define D0F0xD4_x010914E1_Reserved_31_13_MASK 0xFFFF0000 + +/// D0F0xD4_x010914E1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 StrapBifRegApSize:2; ///< + UINT32 StrapBifMemApSize:3; ///< + UINT32 Reserved_11_6:6; ///< + UINT32 StrapBifDoorbellBarDis:1; ///< + UINT32 Bitfield_13_13:1; ///< + UINT32 Bitfield_15_14:2; ///< + UINT32 Reserved_31_13:16; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x010914E1_STRUCT; + +// **** D0F0xD4_x010914E2 Register Definition **** +// Address +#define D0F0xD4_x010914E2_ADDRESS 0x10914E2 +// Type +#define D0F0xD4_x010914E2_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x010914E2_Reserved_0_0_OFFSET 0 +#define D0F0xD4_x010914E2_Reserved_0_0_WIDTH 1 +#define D0F0xD4_x010914E2_Reserved_0_0_MASK 0x1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_OFFSET 1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_WIDTH 1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_MASK 0x2 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_OFFSET 3 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_WIDTH 1 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_MASK 0x8 + +/// D0F0xD4_x010914E2 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 StrapBifIoBarDis:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 StrapBifF064BarDisA:1; ///< + UINT32 Reserved_7_4:4; ///< + UINT32 bit8:1; ///< + UINT32 Reserved_9_9:1; ///< + UINT32 bita:1; ///< + UINT32 Reserved_12_11:2; ///< + UINT32 bit13:1; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x010914E2_STRUCT; + +// **** D0F0xD4_x01091507 Register Definition **** +// Address +#define D0F0xD4_x01091507_ADDRESS 0x1091507 +// Type +#define D0F0xD4_x01091507_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x01091507_StrapBifMemApSizePin_OFFSET 5 +#define D0F0xD4_x01091507_StrapBifMemApSizePin_WIDTH 3 +#define D0F0xD4_x01091507_StrapBifMemApSizePin_MASK 0xE0 + +/// D0F0xD4_x01091507 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5; ///< + UINT32 StrapBifMemApSizePin:3; ///< + UINT32 Reserved_15_8:8; ///< + UINT32 bit16:1; ///< + UINT32 Reserved_31_17:15; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x01091507_STRUCT; + +typedef union { + struct { ///< + UINT32 bit0:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7514_STRUCT; + + +// **** D0F0xFC_x00 Register Definition **** +// Address +#define D0F0xFC_x00_ADDRESS 0x0 +// Type +#define D0F0xFC_x00_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x00_IoapicEnable_OFFSET 0 +#define D0F0xFC_x00_IoapicEnable_WIDTH 1 +#define D0F0xFC_x00_IoapicEnable_MASK 0x1 +#define D0F0xFC_x00_Reserved_1_1_OFFSET 1 +#define D0F0xFC_x00_Reserved_1_1_WIDTH 1 +#define D0F0xFC_x00_Reserved_1_1_MASK 0x2 +#define D0F0xFC_x00_IoapicIdExtEn_OFFSET 2 +#define D0F0xFC_x00_IoapicIdExtEn_WIDTH 1 +#define D0F0xFC_x00_IoapicIdExtEn_MASK 0x4 +#define D0F0xFC_x00_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x00_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x00_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x00_IoapicSbFeatureEn_OFFSET 4 +#define D0F0xFC_x00_IoapicSbFeatureEn_WIDTH 1 +#define D0F0xFC_x00_IoapicSbFeatureEn_MASK 0x10 +#define D0F0xFC_x00_Reserved_31_5_OFFSET 5 +#define D0F0xFC_x00_Reserved_31_5_WIDTH 27 +#define D0F0xFC_x00_Reserved_31_5_MASK 0xFFFFFFE0 + +/// D0F0xFC_x00 +typedef union { + struct { ///< + UINT32 IoapicEnable:1; ///< + UINT32 Reserved_1_1:1; ///< + UINT32 IoapicIdExtEn:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 IoapicSbFeatureEn:1; ///< + UINT32 Reserved_31_5:27; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x00_STRUCT; + +// **** D0F0xFC_x0F Register Definition **** +// Address +#define D0F0xFC_x0F_ADDRESS 0x0F +// Type +#define D0F0xFC_x0F_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x0F_GBIFExtIntrGrp_OFFSET 0 +#define D0F0xFC_x0F_GBIFExtIntrGrp_WIDTH 3 +#define D0F0xFC_x0F_GBIFExtIntrGrp_MASK 0x7 +#define D0F0xFC_x0F_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x0F_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x0F_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x0F_GBIFExtIntrSwz_OFFSET 4 +#define D0F0xFC_x0F_GBIFExtIntrSwz_WIDTH 2 +#define D0F0xFC_x0F_GBIFExtIntrSwz_MASK 0x30 +#define D0F0xFC_x0F_Reserved_31_6_OFFSET 6 +#define D0F0xFC_x0F_Reserved_31_6_WIDTH 26 +#define D0F0xFC_x0F_Reserved_31_6_MASK 0xFFFFFFC0 + +/// D0F0xFC_xOF +typedef union { + struct { ///< + UINT32 GBIFExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 GBIFExtIntrSwz:2; ///< + UINT32 Reserved_31_6:26; ///< + } Field; + + UINT32 Value; +} D0F0xFC_x0F_STRUCT; + +// **** D0F0xFC_x10 Register Definition **** +// Address +#define D0F0xFC_x10_ADDRESS 0x10 +// Type +#define D0F0xFC_x10_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x10_BrExtIntrGrp_OFFSET 0 +#define D0F0xFC_x10_BrExtIntrGrp_WIDTH 3 +#define D0F0xFC_x10_BrExtIntrGrp_MASK 0x7 +#define D0F0xFC_x10_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x10_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x10_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x10_BrExtIntrSwz_OFFSET 4 +#define D0F0xFC_x10_BrExtIntrSwz_WIDTH 2 +#define D0F0xFC_x10_BrExtIntrSwz_MASK 0x30 +#define D0F0xFC_x10_Reserved_15_6_OFFSET 6 +#define D0F0xFC_x10_Reserved_15_6_WIDTH 10 +#define D0F0xFC_x10_Reserved_15_6_MASK 0xFFC0 +#define D0F0xFC_x10_BrIntIntrMap_OFFSET 16 +#define D0F0xFC_x10_BrIntIntrMap_WIDTH 5 +#define D0F0xFC_x10_BrIntIntrMap_MASK 0x1F0000 +#define D0F0xFC_x10_Reserved_31_21_OFFSET 21 +#define D0F0xFC_x10_Reserved_31_21_WIDTH 11 +#define D0F0xFC_x10_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0xFC_x10 +typedef union { + struct { ///< + UINT32 BrExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 BrExtIntrSwz:2; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 BrIntIntrMap:5; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x10_STRUCT; + + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 +// Type +#define D0F0x90_TYPE TYPE_D0F0 + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 +// Type +#define D0F0x94_TYPE TYPE_D0F0 + + +// **** D18F1xF0 Register Definition **** +// Address +#define D18F1xF0_ADDRESS 0xF0 +// Type +#define D18F1xF0_TYPE TYPE_D18F1 + +// **** D18F1x200 Register Definition **** +// Address +#define D18F1x200_ADDRESS 0x200 +// Type +#define D18F1x200_TYPE TYPE_D18F1 + +// **** D18F1x204 Register Definition **** +// Address +#define D18F1x204_ADDRESS 0x204 +// Type +#define D18F1x204_TYPE TYPE_D18F1 + +// **** D18F1x240 Register Definition **** +// Address +#define D18F1x240_ADDRESS 0x240 +// Type +#define D18F1x240_TYPE TYPE_D18F1 + +// **** D18F2x40_dct0 Register Definition **** +// Address +#define D18F2x40_dct0_ADDRESS 0x40 +// Type +#define D18F2x40_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x44_dct0 Register Definition **** +// Address +#define D18F2x44_dct0_ADDRESS 0x44 +// Type +#define D18F2x44_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x48_dct0 Register Definition **** +// Address +#define D18F2x48_dct0_ADDRESS 0x48 +// Type +#define D18F2x48_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x4C_dct0 Register Definition **** +// Address +#define D18F2x4C_dct0_ADDRESS 0x4C +// Type +#define D18F2x4C_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x60_dct0 Register Definition **** +// Address +#define D18F2x60_dct0_ADDRESS 0x60 +// Type +#define D18F2x60_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x64_dct0 Register Definition **** +// Address +#define D18F2x64_dct0_ADDRESS 0x64 +// Type +#define D18F2x64_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x80_dct0 Register Definition **** +// Address +#define D18F2x80_dct0_ADDRESS 0x80 +// Type +#define D18F2x80_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2xA8_dct0 Register Definition **** +// Address +#define D18F2xA8_dct0_ADDRESS 0xA8 +// Type +#define D18F2xA8_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x78_dct0 Register Definition **** +// Address +#define D18F2x78_dct0_ADDRESS 0x78 +// Type +#define D18F2x78_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x110 Register Definition **** +// Address +#define D18F2x110_ADDRESS 0x110 +// Type +#define D18F2x110_TYPE TYPE_D18F2 + +// **** D18F2x114 Register Definition **** +// Address +#define D18F2x114_ADDRESS 0x114 +// Type +#define D18F2x114_TYPE TYPE_D18F2 + +// **** DxFxx18 Register Definition **** +// Address +#define DxFxx18_ADDRESS 0x18 +// Type +#define DxFxx18_TYPE TYPE_D2F1 + +// **** DxFxx20 Register Definition **** +// Address +#define DxFxx20_ADDRESS 0x20 +// Type +#define DxFxx20_TYPE TYPE_D2F1 + +// **** DxFxx24 Register Definition **** +// Address +#define DxFxx24_ADDRESS 0x24 +// Type +#define DxFxx24_TYPE TYPE_D2F1 + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 +// Type +#define D0F0x60_TYPE TYPE_D0F0 + +// **** D0F0xB8 Register Definition **** +// Address +#define D0F0xB8_ADDRESS 0xB8 +// Type +#define D0F0xB8_TYPE TYPE_D0F0 + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xE0 +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// **** D0F0x64_x1F Register Definition **** +// Address +#define D0F0x64_x1F_ADDRESS 0x1F +// Type +#define D0F0x64_x1F_TYPE TYPE_D0F0x64 + +// **** D0F0xE4_PIF_0017 Register Definition **** +// Address +#define D0F0xE4_PIF_0017_ADDRESS 0x17 +// Type +#define D0F0xE4_PIF_0017_TYPE TYPE_D0F0xE4 + +// **** D0F2xF4_x49 Register Definition **** +// Address +// Type + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8026 Register Definition **** +// Address +#define D0F0xE4_WRAP_8026_ADDRESS 0x8026 +// Type +#define D0F0xE4_WRAP_8026_TYPE TYPE_D0F0xE4 + +// **** D0F0xF8 Register Definition **** +// Address +#define D0F0xF8_ADDRESS 0xF8 +// Type +#define D0F0xF8_TYPE TYPE_D0F0 + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1A +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 + +// **** D0F0xBC_x20000 Register Definition **** +// Address +#define D0F0xBC_x20000_ADDRESS 0x20000 +// Type +#define D0F0xBC_x20000_TYPE TYPE_D0F0xBC + +// **** D0F0xBC_x0 Register Definition **** +// Address +#define D0F0xBC_x0_ADDRESS 0x0 +// Type +#define D0F0xBC_x0_TYPE TYPE_D0F0xBC + + + +// **** D0F0xBC_xC210003C Register Definition **** +// Address +#define D0F0xBC_xC210003C_ADDRESS 0xC210003C +// Type +#define D0F0xBC_xC210003C_TYPE TYPE_D0F0xBC + +// **** D0F0xD4_x010914C3 Register Definition **** +// Address +#define D0F0xD4_x010914C3_ADDRESS 0x010914C3 +// Type +#define D0F0xD4_x010914C3_TYPE TYPE_D0F0xD4 + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h new file mode 100644 index 0000000000..2bf8952d29 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBURA_H_ +#define _GNBURA_H_ + +#include "GnbPcie.h" + +/// Generic device object +typedef struct { + PCI_ADDR DevPciAddress; ///< DevPciAddress + GNB_HANDLE *GnbHandle; ///< GnbHandle + AMD_CONFIG_PARAMS *StdHeader; ///< +} DEV_OBJECT; + +/// Register address 32 bit encoding +typedef struct { + UINT32 Address: 31; ///< Register address + UINT32 MultInst: 1; ///< Must equals to 0 +} URA_REGISTER_32B_ENTRY; + +/// Register address encoding that represents a group of registers that have same fields' definitions +typedef struct { + UINT32 Addr: 24; ///< Register address + UINT32 InstOffset: 7; ///< The address offset between register instances + UINT32 MultInst: 1; ///< Must equals to 1 +} URA_MULT_REG_ENTRY; + +/// 16 bit field encoding +typedef struct { + UINT16 BfOffset: 6; ///< Offset of the bit field + UINT16 BfWidth: 6; ///< Width of the bit field + UINT16 Offset: 4; ///< Number of field entries from its register address entry + ///< The first field entry of a register must be place right after its register entry and has offset 1. + ///< The second field is placed right after the first field and has offset 2 and so on. + ///< The offset field is maxed out at 15. So any entries after the 15th entries will take offset 0. +} URA_FIELD_16B_ENTRY; + +/// 32 bit field encoding +typedef struct { + UINT32 BfOffset: 6; ///< Offset of the bit field + UINT32 BfWidth: 6; ///< Width of the bit field + UINT32 RegIndex: 13; ///< Direct index to its register address entry + UINT32 Rev: 6; ///< Contains ID of the family/rev that this bit field is valid + UINT32 Reserved: 1; ///< Reserved +} URA_FIELD_32B_ENTRY; + +/// Register address 64 bit encoding +typedef struct { + UINT64 DomainAddress:32; ///< Register domain address + UINT64 DomainType: 8; ///< Register domain type + UINT64 Reserved: 24; ///< Reserved +} URA_REGISTER_64B_ENTRY; + +/// Register / Field table entry +#define URA_ENTRY UINT16 + +/// Token +typedef union { + UINT32 Encode; ///< Token value + + struct { ///< Sub structure used to parse Token + UINT32 Index: 13; ///< Index into a specific register or field entry in register/field table + UINT32 Type: 3; ///< Entry type: + ///< 000b: 16-bit field location encoding + ///< 001b: Register address encoding + ///< 010b: 32-bit field location encoding + ///< 011b: 64-bit field location encoding + ///< Others would reserved + UINT32 Selector: 6; ///< Used by unified register access to select the access method + UINT32 InstSel: 6; ///< When register/field has multiple instances, this field is used to obtain the register address of a register group. + UINT32 S3Save:1; ///< Indicate whether S3Save is needed. + UINT32 StreamSet:1; ///< Stream Set + UINT32 ParentType:1; ///< Parent token type + UINT32 Reserved: 1; ///< Reserved for device specific usage + } Parser; +} URA_TOKEN_STRUCT; + +#define URA_TOKEN UINT32 + +#define URA_TYPE_FIELD_16 0 +#define URA_TYPE_FIELD_32 1 +#define URA_TYPE_REGISTER_32 2 +#define URA_TYPE_REGISTER_64 3 + +#define URA_TOKEN_PARENT_TYPE_32 0x20000000ul +#define URA_TOKEN_PARENT_TYPE_64 0x00000000ul + +/** + TOKEN_DEF(Index, Type, Selector) + Defines a register of field token + + @param[in] Index + @param[in] Type + @param[in] Selector + @param[in] ParentType + + @return URA_TOKEN Encrypted URA_TOKEN format +--*/ +#define TOKEN_DEF(Index, Type, Selector, ParentType) ( \ + (((UINT32) (Index)) | (((UINT32) (Type)) << 13) | (((UINT32) (Selector)) << 16) | ((UINT32) (ParentType))) \ + ) + +#define _RESERVED 0xFFFFFFFFul +#define _UNUSED 0xFEFEFEFEul +#define GNB_URA_FLAG_S3SAVE 0x00000001ul +#define GNB_URA_STREAM_SET 0x20000000ul + +/// Structure used to pass token info to access methods +typedef struct { + UINT32 RegAddress; ///< Register address + UINT8 BfOffset; ///< Offset of the bit field + UINT8 BfWidth; ///< Width of the bit field + BOOLEAN WholeRegAccess; ///< Whole register access + UINT32 MethodType; ///< Index into the access method table to select access method + UINT32 Flags; ///< S3 + UINT32 StreamSet; ///< StreamSet + UINT8 RegDomainType; ///< Register Domain type +} URA_TOKEN_INFO; + +#define TYPE_GNB_INDIRECT_ACCESS 0 +#define TYPE_GNB_PROTOCOL_ACCESS 1 + +/// URA_TUPLE +typedef struct { + URA_TOKEN Token; ///< Token + UINT32 Value; ///< Token value + UINT32 StepLength; ///< Byte length to next address for stream set usage. +} URA_TUPLE; + +typedef VOID F_GNBURASERVICELOCATEREGTBL ( + IN DEV_OBJECT *Device, + IN UINT32 *UraTableAddress + ); + +typedef VOID F_GNBURASERVICEGET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +typedef VOID F_GNBURASERVICESET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +typedef VOID F_GNBURASERVICESTREAMSET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +/// Register Read/Write protocol +typedef struct { + F_GNBURASERVICELOCATEREGTBL *GnbUraLocateRegTbl; ///< + F_GNBURASERVICEGET *GnbUraGet; ///< + F_GNBURASERVICESET *GnbUraSet; ///< + F_GNBURASERVICESTREAMSET *GnbUraStreamSet; ///< +} GNB_URA_SERVICE; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h new file mode 100644 index 0000000000..c4e51b0588 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBURASERVICES_H_ +#define _GNBURASERVICES_H_ + +#include "GnbUra.h" +#include "GnbUraToken.h" + +/*---------------------------------------------------------------------------- + * FUNCTION PROTOTYPES + * + *---------------------------------------------------------------------------- + */ + +VOID +GnbUraGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN OUT VOID *Value + ); + +VOID +GnbUraSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN VOID *Value + ); + +VOID +GnbUraCombinedGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +VOID +GnbUraCombinedSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h new file mode 100644 index 0000000000..29683607ca --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +#ifndef _GNBURATOKEN_H_ +#define _GNBURATOKEN_H_ + +/// Template structure for register/field table +typedef struct { + URA_REGISTER_64B_ENTRY RxSmuIntReq;///< + URA_FIELD_16B_ENTRY BfxSmuIntToggle;///< + URA_FIELD_16B_ENTRY BfxSmuServiceIndex;///< + URA_REGISTER_64B_ENTRY RxSmuIntSts;///< + URA_FIELD_16B_ENTRY BfxSmuIntAck;///< + URA_FIELD_16B_ENTRY BfxSmuIntDone;///< + URA_REGISTER_64B_ENTRY RxSmuAuthSts;///< + URA_FIELD_16B_ENTRY BfxSmuAuthDone;///< + URA_FIELD_16B_ENTRY BfxSmuAuthPass;///< + URA_REGISTER_64B_ENTRY RxSmuFwAuth;///< + URA_FIELD_16B_ENTRY BfxSmuProtectedMode;///< + URA_REGISTER_64B_ENTRY REG_FIELD_TABLE_STRUCT_fld11;///< + URA_FIELD_16B_ENTRY BfxSmuBootSeqDone;///< + URA_REGISTER_64B_ENTRY RxSmuFwFlags;///< + URA_FIELD_16B_ENTRY BfxSmuInterruptsEnabled;///< + URA_REGISTER_64B_ENTRY RxSmuResetCntl;///< + URA_FIELD_16B_ENTRY BfxSmuRstReg;///< + URA_REGISTER_64B_ENTRY RxSmuClkCntl;///< + URA_FIELD_16B_ENTRY BfxSmuCkDisable;///< + URA_REGISTER_64B_ENTRY RxSmuAuthVector;///< + URA_REGISTER_64B_ENTRY RxSmuRamStartAddr;///< + URA_REGISTER_64B_ENTRY RxSmuRomStartAddr;///< + URA_REGISTER_64B_ENTRY RxSmuIntArgument;///< + +} REG_FIELD_TABLE_STRUCT; + +#define IDX_CALC(VarName) (offsetof (REG_FIELD_TABLE_STRUCT, VarName) / 2) /* TODO: why ## */ +#define SEL_CALC(VarName) VarName +#define FIELD_OFFSET(RegName, FieldName) ((((IDX_CALC(FieldName) - IDX_CALC(RegName) - 1) / 2) <= 15) ? ((IDX_CALC(FieldName) - IDX_CALC(RegName) - 1) / 2) : 0) + +#define TRxSmuIntReq TOKEN_DEF (IDX_CALC (RxSmuIntReq), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntToggle TOKEN_DEF (IDX_CALC (BfxSmuIntToggle), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuServiceIndex TOKEN_DEF (IDX_CALC (BfxSmuServiceIndex), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuIntSts TOKEN_DEF (IDX_CALC (RxSmuIntSts), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntAck TOKEN_DEF (IDX_CALC (BfxSmuIntAck), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntDone TOKEN_DEF (IDX_CALC (BfxSmuIntDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuAuthSts TOKEN_DEF (IDX_CALC (RxSmuAuthSts), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuAuthDone TOKEN_DEF (IDX_CALC (BfxSmuAuthDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuAuthPass TOKEN_DEF (IDX_CALC (BfxSmuAuthPass), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuFwAuth TOKEN_DEF (IDX_CALC (RxSmuFwAuth), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuProtectedMode TOKEN_DEF (IDX_CALC (BfxSmuProtectedMode), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRcuUcEvents TOKEN_DEF (IDX_CALC (REG_FIELD_TABLE_STRUCT_fld11), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuBootSeqDone TOKEN_DEF (IDX_CALC (BfxSmuBootSeqDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuFwFlags TOKEN_DEF (IDX_CALC (RxSmuFwFlags), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_PROTOCOL_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuInterruptsEnabled TOKEN_DEF (IDX_CALC (BfxSmuInterruptsEnabled), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_PROTOCOL_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuResetCntl TOKEN_DEF (IDX_CALC (RxSmuResetCntl), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuRstReg TOKEN_DEF (IDX_CALC (BfxSmuRstReg), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuClkCntl TOKEN_DEF (IDX_CALC (RxSmuClkCntl), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuCkDisable TOKEN_DEF (IDX_CALC (BfxSmuCkDisable), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuAuthVector TOKEN_DEF (IDX_CALC (RxSmuAuthVector), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRamStartAddr TOKEN_DEF (IDX_CALC (RxSmuRamStartAddr), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRomStartAddr TOKEN_DEF (IDX_CALC (RxSmuRomStartAddr), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuIntArgument TOKEN_DEF (IDX_CALC (RxSmuIntArgument), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) + + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c new file mode 100644 index 0000000000..9b1d9084fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c @@ -0,0 +1,128 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB early init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[]; +extern OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[]; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbInitAtEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); + +AGESA_STATUS +GnbInitAtEarlier ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Early + * + * + * + * @param[in,out] EarlyParamsPtr Pointer to early configuration params. + * @retval Initialization status. + */ +AGESA_STATUS +GnbInitAtEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Early before CPU + * + * + * + * @param[in,out] EarlyParamsPtr Pointer to early configuration params. + * @retval Initialization status. + */ +AGESA_STATUS +GnbInitAtEarlier ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ) +{ + AGESA_STATUS Status; + + // Only run code on BSP + if (IsBsp (&EarlyParamsPtr->StdHeader, &Status)) { + Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader); + } + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c new file mode 100644 index 0000000000..7b93e916ae --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB env init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbInitDataStructAtEnvDef ( + IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, + IN AMD_ENV_PARAMS *EnvParamsPtr + ); + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_ENV_PARAMS *EnvParamsPtr + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Env + * + * + * + * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. + * @param[in] EnvParamsPtr Pointer to env configuration params. + */ +VOID +GnbInitDataStructAtEnvDef ( + IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, + IN AMD_ENV_PARAMS *EnvParamsPtr + ) +{ + GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; + GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport; + GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; + GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; + GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe; + GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl; + GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon; + GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe; + GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay; + GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon; + GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl; + GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq; + GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue; + GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode; + GnbEnvConfigPtr->LvdsMiscControl.Value = 0; + GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value; + GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; + GnbEnvConfigPtr->GnbRemoteDisplaySupport = UserOptions.CfgGnbRemoteDisplaySupport; + GnbEnvConfigPtr->LvdsMiscVoltAdjustment = UserOptions.CfgLvdsMiscVoltAdjustment; + GnbEnvConfigPtr->DisplayMiscControl.Value = UserOptions.CfgDisplayMiscControl.Value; + GnbEnvConfigPtr->DpFixedVoltSwingType = UserOptions.CfgDpFixedVoltSwingType; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Env + * + * + * + * @param[in] EnvParamsPtr Pointer to env configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_ENV_PARAMS *EnvParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c new file mode 100644 index 0000000000..c45e10a1ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c @@ -0,0 +1,136 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB late init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85198 $ @e \$Date: 2013-01-03 13:49:32 -0600 (Thu, 03 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbInitDataStructAtLateDef ( + IN OUT GNB_LATE_CONFIGURATION *GnbLateConfigPtr, + IN AMD_LATE_PARAMS *LateParamsPtr + ); + +AGESA_STATUS +GnbInitAtLate ( + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Late + * + * + * + * @param[in] GnbLateConfigPtr Pointer to gnb Late configuration params. + * @param[in] LateParamsPtr Pointer to Late configuration params. + */ +VOID +GnbInitDataStructAtLateDef ( + IN OUT GNB_LATE_CONFIGURATION *GnbLateConfigPtr, + IN AMD_LATE_PARAMS *LateParamsPtr + ) +{ + UINT32 Property; + + Property = TABLE_PROPERTY_DEFAULT; + Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0; + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, + (AMD_CONFIG_PARAMS *)&LateParamsPtr->StdHeader); + + GnbLateConfigPtr->DockedTdpHeadroom = FALSE; + if ((Property & TABLE_PROPERTY_BAPM) && UserOptions.CfgDockedTdpHeadroom) { + GnbLateConfigPtr->DockedTdpHeadroom = TRUE; + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Late post + * + * + * + * @param[in,out] LateParamsPtr Pointer to late configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtLate ( + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c new file mode 100644 index 0000000000..f786d77b92 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB mid init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATMID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbInitDataStructAtMidDef ( + IN OUT GNB_MID_CONFIGURATION *GnbMidConfigPtr, + IN AMD_MID_PARAMS *MidParamsPtr + ); + +AGESA_STATUS +GnbInitAtMid ( + IN OUT AMD_MID_PARAMS *MidParamsPtr + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Mid + * + * + * + * @param[in] GnbMidConfigPtr Pointer to gnb Mid configuration params. + * @param[in] MidParamsPtr Pointer to Mid configuration params. + */ +VOID +GnbInitDataStructAtMidDef ( + IN OUT GNB_MID_CONFIGURATION *GnbMidConfigPtr, + IN AMD_MID_PARAMS *MidParamsPtr + ) +{ + GnbMidConfigPtr->GnbIoapicAddress = UserOptions.CfgGnbIoapicAddress; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Mid post + * + * + * + * @param[in,out] MidParamsPtr Pointer to mid configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtMid ( + IN OUT AMD_MID_PARAMS *MidParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c new file mode 100644 index 0000000000..6c5c7a1cfd --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c @@ -0,0 +1,150 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB POST init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbPostFeatureTable[]; +extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbInitDataStructAtPostDef ( + IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr, + IN AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +GnbInitAtPost ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +GnbInitAtPostAfterDram ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Env + * + * + * + * @param[in] GnbPostConfigPtr Pointer to GNB POST configuration params. + * @param[in] PostParamsPtr Pointer to POST configuration params. + */ +VOID +GnbInitDataStructAtPostDef ( + IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr, + IN AMD_POST_PARAMS *PostParamsPtr + ) +{ + GnbPostConfigPtr->IgpuEnableDisablePolicy = UserOptions.CfgIgpuEnableDisablePolicy; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Post + * + * + * + * @param[in] PostParamsPtr Pointer to post configuration parameters + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtPost ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Post after DRAM init + * + * + * + * @param[in] PostParamsPtr Pointer to post configuration parameters + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtPostAfterDram ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c new file mode 100644 index 0000000000..e60e18b245 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB reset init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c new file mode 100644 index 0000000000..2201ff6d64 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB late init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATS3SAVE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[]; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at S3 save + * + * + * + * @param[in,out] AmdS3SaveParams Pointer to AMD_S3SAVE_PARAMS. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbS3SaveFeatureTable[0], &AmdS3SaveParams->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h new file mode 100644 index 0000000000..af2ff525f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h @@ -0,0 +1,57 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBCOMMONLIB_H_ +#define _GNBCOMMONLIB_H_ + +#include "GnbLib.h" +#include "GnbLibCpuAcc.h" +#include "GnbLibHeap.h" +#include "GnbLibIoAcc.h" +#include "GnbLibMemAcc.h" +#include "GnbLibPci.h" +#include "GnbLibPciAcc.h" +#include "GnbTimerLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c new file mode 100644 index 0000000000..34990c51ed --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -0,0 +1,530 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbLibIoAcc.h" +#include "GnbLibPciAcc.h" +#include "GnbLibMemAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_SERVICE *ServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciRead (Address + IndexOffset, Width, Value, Config); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config); + Mask = (1 << FieldWidth) - 1; + *Value = (*Value >> FieldOffset) & Mask; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciWrite (Address + IndexOffset, Width, Value, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Value Pointer to value + * @param[in] S3Save Save for S3 (TRUE/FALSE) + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ) +{ + UINT32 Data; + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config); + Mask = (1 << FieldWidth) - 1; + Data &= (~(Mask << FieldOffset)); + Data |= ((Value & Mask) << FieldOffset); + GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Mask And Mask + * @param[in] Value Or Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciIndirectRead ( + Address, + IndirectAddress, + (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width, + &Data, + Config + ); + Data = (Data & Mask) | Value; + GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCI registers + * + * + * + * @param[in] Address PCI address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibPciWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write I/O registers + * + * + * + * @param[in] Address I/O Port + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Mask + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibIoRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibIoWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Indirect IO block read + * + * + * + * @param[in] IndexPort Index Port + * @param[in] DataPort Data Port + * @param[in] Width Access width + * @param[in] IndexAddress Index Address + * @param[in] Count Count + * @param[in] Buffer Buffer + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ) +{ + UINT32 Index; + Index = IndexAddress; + for (; Index < (IndexAddress + Count); Index++) { + GnbLibIoWrite (IndexPort, Width, &Index, Config); + GnbLibIoRead (DataPort, Width, Buffer, Config); + Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOAPIC ID + * + * + * + * @param[in] IoApicBaseAddress IO APIC base address + * @param[in] Config Pointer to standard header + */ +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ) +{ + UINT32 Value; + Value = 0x0; + GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config); + GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config); + return (UINT8) (Value >> 24); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write MMIO registers + * + * + * + * @param[in] Address Physical address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibMemRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibMemWrite (Address, Width, &Data, Config); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate power of number + * + * + * + * @param[in] Value Number + * @param[in] Power Power + */ + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ) +{ + UINT32 Result; + if (Power == 0) { + return 1; + } + Result = Value; + while ((--Power) > 0) { + Result *= Value; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Search buffer for pattern + * + * + * @param[in] Buf1 Pointer to source buffer which will be subject of search + * @param[in] Buf1Length Length of the source buffer + * @param[in] Buf2 Pointer to pattern buffer + * @param[in] Buf2Length Length of the pattern buffer + * @retval Pointer on first occurrence of Buf2 in Buf1 or NULL + */ + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ) +{ + UINT8 *CurrentBuf1Ptr; + CurrentBuf1Ptr = Buf1; + while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { + UINT8 *SourceBufPtr; + UINT8 *PatternBufPtr; + UINTN PatternBufLength; + SourceBufPtr = CurrentBuf1Ptr; + PatternBufPtr = Buf2; + PatternBufLength = Buf2Length; + while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); + if (PatternBufLength == 0) { + return CurrentBuf1Ptr; + } + CurrentBuf1Ptr++; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] Buffer Buffer pointer + * @param[in] Count Count of data elements + * @param[in] DataWidth DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD + * @param[in] LineWidth Number of data item per line + */ +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ) +{ + UINT32 Index; + UINT32 DataItemCount; + ASSERT (LineWidth != 0); + ASSERT (DataWidth >= 1 && DataWidth <= 4); + DataItemCount = 0; + for (Index = 0; Index < Count; ) { + switch (DataWidth) { + case 1: + IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index)); + Index += 1; + break; + case 2: + IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index)); + Index += 2; + break; + case 3: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index)); + Index += 4; + break; + case 4: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + Index += 8; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n"); + return; + } + if (++DataItemCount >= LineWidth) { + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + DataItemCount = 0; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] ServiceId Service ID + * @param[in] SocketId Socket ID + * @param[in] ServiceProtocol Service protocol + * @param[in] StdHeader Standard Configuration Header + */ +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_SERVICE *SeviceEntry; + CPU_LOGICAL_ID LogicalId; + SeviceEntry = ServiceTable; + GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); + while (SeviceEntry != NULL) { + if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) { + *ServiceProtocol = SeviceEntry->ServiceProtocol; + return AGESA_SUCCESS; + } + SeviceEntry = SeviceEntry->NextService; + } + return AGESA_UNSUPPORTED; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h new file mode 100644 index 0000000000..7e35615231 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h @@ -0,0 +1,156 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBLIB_H_ +#define _GNBLIB_H_ + +#define IOC_WRITE_ENABLE 0x80 + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ); + + +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ); + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ); + +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ); + +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ); + +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ); + +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c new file mode 100644 index 0000000000..0430fba359 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Read CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); + GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Write CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + OffsetRegisterValue = IndirectAddress | BIT30; + GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h new file mode 100644 index 0000000000..f560b7b12b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h @@ -0,0 +1,65 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _CPUACCLIB_H_ +#define _CPUACCLIB_H_ + +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c new file mode 100644 index 0000000000..91af4bbbe0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c @@ -0,0 +1,176 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "heapManager.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + AllocHeapParams.RequestedBufferSize = (UINT32) Length; + AllocHeapParams.BufferHandle = Handle; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return AllocHeapParams.BufferPtr; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap and clear it + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + VOID *Buffer; + Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader); + if (Buffer != NULL) { + LibAmdMemFill (Buffer, 0x00, Length, StdHeader); + } + return Buffer; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locates a previously allocated buffer on the heap. + * + * + * @param[in] Handle Buffer handle + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer handle not found + * + */ + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + LOCATE_HEAP_PTR LocHeapParams; + LocHeapParams.BufferHandle = Handle; + Status = HeapLocateBuffer (&LocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return LocHeapParams.BufferPtr; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h new file mode 100644 index 0000000000..a751eee938 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h @@ -0,0 +1,69 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBHEAPLIB_H_ +#define _GNBHEAPLIB_H_ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c new file mode 100644 index 0000000000..4e4fa7ac04 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * +* Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibIoAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------*/ +/** + * Write I/O Port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value); + } + LibAmdIoWrite (Width, Address, Value, StdHeader); +} +/** + * Read IO port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdIoRead (Width, Address, Value, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h new file mode 100644 index 0000000000..4521cfd616 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h @@ -0,0 +1,66 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _IOACCLIB_H_ +#define _IOACCLIB_H_ + + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c new file mode 100644 index 0000000000..ad6433bd93 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c @@ -0,0 +1,125 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibMemAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value); + } + LibAmdMemWrite (Width, Address, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdMemRead (Width, Address, Value, StdHeader); +} + + + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h new file mode 100644 index 0000000000..908b1ec724 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _MEMACCLIB_H_ +#define _MEMACCLIB_H_ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c new file mode 100644 index 0000000000..10ef0a3f6e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c @@ -0,0 +1,403 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#include "AGESA.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLibPciAcc.h" +#include "GnbLibPci.h" +#include "GnbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device present + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is present + * @retval FALSE Device is not present + */ + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceId; + GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader); + if (DeviceId == 0xffffffff) { + return FALSE; + } else { + return TRUE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is bridge + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a bridge + * @retval FALSE Device is not a bridge + */ + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x7f) == 1) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is multifunction + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a multifunction device. + * @retval FALSE Device is a single function device. + * + */ +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x80) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is PCIe device + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a PCIe device + * @retval FALSE Device is not a PCIe device + * + */ + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) { + return TRUE; + } else { + return FALSE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCI capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] CapabilityId PCI capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of capability pointer + * + */ + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 CapabilityPtr; + UINT8 CurrentCapabilityId; + CapabilityPtr = 0x34; + if (!GnbLibPciIsDevicePresent (Address, StdHeader)) { + return 0; + } + while (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader); + if (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader); + if (CurrentCapabilityId == CapabilityId) { + break; + } + CapabilityPtr++; + } + } + return CapabilityPtr; +} +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCIe extended capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] ExtendedCapabilityId Extended PCIe capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of extended capability pointer + * + */ + + +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 CapabilityPtr; + UINT32 ExtendedCapabilityIdBlock; + if (GnbLibPciIsPcieDevice (Address, StdHeader)) { + GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) { + do { + CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff); + if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) { + return CapabilityPtr; + } + GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0); + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Scan range of device on PCI bus. + * + * + * + * @param[in] Start Start address to start scan from + * @param[in] End End address of scan + * @param[in] ScanData Supporting data + * + */ +/*----------------------------------------------------------------------------------------*/ +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINTN Bus; + UINTN Device; + UINTN LastDevice; + UINTN Function; + UINTN LastFunction; + PCI_ADDR PciDevice; + SCAN_STATUS Status; + + for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) { + Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00; + LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F; + for ( ; Device <= LastDevice; Device++) { + if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) { + Function = Start.Address.Function; + } else { + Function = 0x0; + } + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + continue; + } + if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) { + if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) { + LastFunction = Start.Address.Function; + } else { + LastFunction = 0x7; + } + } else { + LastFunction = 0x0; + } + for ( ; Function <= LastFunction; Function++) { + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + Status = ScanData->GnbScanCallback (PciDevice, ScanData); + if ((Status & SCAN_SKIP_FUNCTIONS) != 0) { + Function = LastFunction + 1; + } + if ((Status & SCAN_SKIP_DEVICES) != 0) { + Device = LastDevice + 1; + } + if ((Status & SCAN_SKIP_BUSES) != 0) { + Bus = End.Address.Bus + 1; + } + } + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Scan all subordinate buses + * + * + * @param[in] Bridge PCI bridge address + * @param[in,out] ScanData Scan configuration data + * + */ +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + PCI_ADDR StartRange; + PCI_ADDR EndRange; + UINT8 SecondaryBus; + GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader); + if (SecondaryBus != 0) { + StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0); + EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0); + GnbLibPciScan (StartRange, EndRange, ScanData); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get PCIe device type + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Northbridge configuration structure pointer. + * + * @retval PCIE_DEVICE_TYPE + */ + /*----------------------------------------------------------------------------------------*/ + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT8 Value; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader); + return Value >> 4; + } + return PcieNotPcieDevice; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save config space area + * + * + * + * @param[in] Address PCI address of device. + * @param[in] StartRegisterAddress Start register address. + * @param[in] EndRegisterAddress End register address. + * @param[in] Width Access width. + * @param[in] StdHeader Standard header. + * + */ + /*----------------------------------------------------------------------------------------*/ + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + UINT16 Delta; + UINT16 Length; + Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress); + Delta = LibAmdAccessWidth (Width); + for (Index = 0; Index <= Length; Index = Index + Delta) { + GnbLibPciRMW ( + Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)), + Width, + 0xffffffff, + 0x0, + StdHeader + ); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h new file mode 100644 index 0000000000..d1cf252c95 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h @@ -0,0 +1,166 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBLIBPCI_H_ +#define _GNBLIBPCI_H_ + +#define PCIE_CAP_ID 0x10 +#define IOMMU_CAP_ID 0x0F + +/// PCIe device type +typedef enum { + PcieDeviceEndPoint, ///< Endpoint + PcieDeviceLegacyEndPoint, ///< Legacy endpoint + PcieDeviceRootComplex = 4, ///< Root complex + PcieDeviceUpstreamPort, ///< Upstream port + PcieDeviceDownstreamPort, ///< Downstream Port + PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge + PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge + PcieNotPcieDevice = 0xff ///< unknown device +} PCIE_DEVICE_TYPE; + +typedef UINT32 SCAN_STATUS; + +#define SCAN_SKIP_FUNCTIONS 0x1 +#define SCAN_SKIP_DEVICES 0x2 +#define SCAN_SKIP_BUSES 0x4 +#define SCAN_SUCCESS 0x0 + +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); + +typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +///Scan supporting data +struct _GNB_PCI_SCAN_DATA { + GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header +}; + +#define PCIE_CAP_ID 0x10 +#define PCIE_LINK_CAP_REGISTER 0x0C +#define PCIE_LINK_CTRL_REGISTER 0x10 +#define PCIE_DEVICE_CAP_REGISTER 0x04 +#define PCIE_DEVICE_CTRL_REGISTER 0x08 +#define PCIE_ASPM_L1_SUPPORT_CAP BIT11 + +#define MAX_PAYLOAD_128 0x0 ///< Max allowed payload size 128 bytes +#define MAX_PAYLOAD_256 0x1 ///< Max allowed payload size 256 bytes +#define MAX_PAYLOAD_512 0x2 ///< Max allowed payload size 512 bytes +#define MAX_PAYLOAD_1024 0x3 ///< Max allowed payload size 1024 bytes +#define MAX_PAYLOAD_2048 0x4 ///< Max allowed payload size 2048 bytes +#define MAX_PAYLOAD_4096 0x5 ///< Max allowed payload size 4096 bytes +#define MAX_PAYLOAD 0x5 ///< Max allowed payload size according to spec is 101b (4096 bytes) + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c new file mode 100644 index 0000000000..d9d708fa65 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c @@ -0,0 +1,156 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibPciAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value); + } + LibAmdPciWrite (Width, PciAddress, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + LibAmdPciRead (Width, PciAddress, Value, StdHeader); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll PCI reg + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff); + } + LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h new file mode 100644 index 0000000000..14808e07ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBPCIACC_H_ +#define _GNBLIBPCIACC_H_ + +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c new file mode 100644 index 0000000000..bbbede825d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various Timer services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#include "AGESA.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbTimerLib.h" +#include "GnbFamServices.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE + + + + +/*----------------------------------------------------------------------------------------*/ +/* + * Stall and save to script table + * + * + * + * @param[in] Microsecond Stall time + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibStallS3Save ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond); + GnbLibStall (Microsecond, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Stall + * + * + * + * @param[in] Microsecond Stall time + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibStall ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TimeStampStart; + UINT32 TimeStampDelta; + UINT32 TimeStampCurrent; + + TimeStampStart = GnbFmTimeStamp (StdHeader); + do { + TimeStampCurrent = GnbFmTimeStamp (StdHeader); + TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent)); + } while (TimeStampDelta < Microsecond); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Stall S3 script + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context pointer to UINT32 number of us + */ +VOID +GnbLibStallS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + GnbLibStall (* ((UINT32*) Context), StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family specific time stamp function + * + * + * @param[in] StdHeader Standard configuration header + * @retval Count + */ +UINT32 +GnbFmTimeStamp ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_TS_SERVICES *GnbFamTsFunc; + GNB_HANDLE *GnbHandle; + + GnbHandle = GnbGetHandle (StdHeader); + + Status = GnbLibLocateService (GnbFamTsService, GnbGetSocketId (GnbHandle), (VOID **)&GnbFamTsFunc, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbFamTsFunc->GnbFmTimeStamp (StdHeader); + } + return 0; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h new file mode 100644 index 0000000000..c7796d1202 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various Timer Services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBTIMERLIB_H_ +#define _GNBTIMERLIB_H_ + +VOID +GnbLibStallS3Save ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibStall ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GnbFmTimeStamp ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibStallS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c new file mode 100644 index 0000000000..f42e306396 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c @@ -0,0 +1,515 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED No more configuration available for given engine type + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); + } + return AGESA_ERROR; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); + } + return FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmMapPortPciAddress (Engine); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); + } + return Status; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); + } + return PcieGen1; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); + } + return 0x0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SB port info + * + * + * @param[out] SocketId Socket ID + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS SB configuration determined successfully + */ +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); + } + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c new file mode 100644 index 0000000000..1ae93d42a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c @@ -0,0 +1,245 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbFamServices.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbGfx.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if IOMMU unit present and enabled + * + * + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] StdHeader Standard configuration header + * + */ +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map graphics engine to display path + * + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPathList Display path list + * @param[in] Gfx Pointer to global GFX configuration + * + */ +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + GFX_FAM_SERVICES *GfxFamilyService; + GNB_HANDLE *GnbHandle; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GfxFamilyService->GfxMapEngineToDisplayPath (Engine, DisplayPathList, Gfx); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate COF for DFS out of Main PLL + * + * + * + * @param[in] Did Did + * @param[in] StdHeader Standard Configuration Header + * @retval COF in 10khz + */ + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GFX_FAM_SERVICES *GfxFamilyService; + GNB_HANDLE *GnbHandle; + GnbHandle = GnbGetHandle (StdHeader); + Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GfxFamilyService->GfxCalculateClock (Did, StdHeader); + } + return 200*100; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable GFX controller + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GFX_FAM_SERVICES *GfxFamilyService; + GNB_HANDLE *GnbHandle; + GnbHandle = GnbGetHandle (StdHeader); + Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + GfxFamilyService->GfxDisableController (StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + GFX_FAM_SERVICES *GfxFamilyService; + GNB_HANDLE *GnbHandle; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GfxFamilyService->GfxIsVbiosPosted (Gfx); + } + return TRUE; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c new file mode 100644 index 0000000000..96dc84121a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_ENV_PARAMS *EnvParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; + Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; + Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; + Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; + Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe; + Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl; + Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon; + Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe; + Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay; + Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon; + Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl; + Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq; + Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue; + Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode; + Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value; + Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; + Gfx->GnbRemoteDisplaySupport = EnvParamsPtr->GnbEnvConfiguration.GnbRemoteDisplaySupport; + Gfx->LVDSVoltAdjust = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscVoltAdjustment; + Gfx->DisplayMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.DisplayMiscControl.Value; + Gfx->DpFixedVoltSwingType = EnvParamsPtr->GnbEnvConfiguration.DpFixedVoltSwingType; + GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c new file mode 100644 index 0000000000..ae0128ab7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -0,0 +1,264 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86877 $ @e \$Date: 2013-01-28 10:59:42 -0600 (Mon, 28 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ); + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable GMM Access + * + * + * + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for GMM allocated + GnbLibPciIndirectRead (GNB_SBDFO | 0x60, 0x1C | IOC_WRITE_ENABLE, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + Gfx->GmmBase = 0; + + if ((Value & 0x4) != 0) { + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x1c, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); + Gfx->GmmBase = (UINT64) (Gfx->GmmBase << 32); + } + + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + Gfx->GmmBase |= (Value & 0xfffffff0); + if (Gfx->GmmBase == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for FB allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + if ((Value & 0xfffffff0) == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + //Push CPU MMIO pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + // Turn on memory decoding on APC to enable access to GMM register space + if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { + GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push APC pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + } + // Turn on memory decoding on GFX to enable access to GMM register space + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push iGPU pci config to S3 script + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get UMA info + * + * UMA info stored on heap by memory module + * + * @param[out] UmaInfo Pointer to UMA info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UMA_INFO *MemUmaInfo; + + MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); + if (MemUmaInfo == NULL) { + LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); + UmaInfo->UmaMode = UMA_NONE; + } else { + LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); + if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { + UmaInfo->UmaMode = UMA_NONE; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS Data located + * @retval AGESA_FATA Data not found + */ + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ) +{ + *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); + if (*Gfx == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Gfx)->StdHeader = (PVOID) StdHeader; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump + * + * + * + * @param[in] Gfx Pointer to GFX configuration + */ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n"); + IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate); + IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl); + IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n", + (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : ( + (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : ( + (Gfx->GmcPowerGating == GmcPowerGatingWithStutter) ? "GmcPowerGatingWithStutter" : "Unknown")) + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n", + (Gfx->UmaSteering == 0) ? "0" : ( + (Gfx->UmaSteering == SystemTrafficOnion) ? "SystemTrafficOnion" : ( + (Gfx->UmaSteering == Onion) ? "Onion" : ( + (Gfx->UmaSteering == 3) ? "Unknown" : "Unknown"))) + ); + IDS_HDT_CONSOLE (GFX_MISC, " iGpuVgaMode - %s\n", + (Gfx->iGpuVgaMode == iGpuVgaAdapter) ? "VGA" : ( + (Gfx->iGpuVgaMode == iGpuVgaNonAdapter) ? "Non VGA" : "Unknown") + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); + IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); + } + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n"); + +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h new file mode 100644 index 0000000000..6c16a88752 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h @@ -0,0 +1,71 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GFXCONFIGLIB_H_ +#define _GFXCONFIGLIB_H_ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ); + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c new file mode 100644 index 0000000000..9cc594ea06 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_MID_PARAMS *MidParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + MidParamsPtr = (AMD_MID_PARAMS *) StdHeader; + Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode; + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c new file mode 100644 index 0000000000..d7c22074a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86709 $ @e \$Date: 2013-01-24 17:39:09 -0600 (Thu, 24 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_PLATFORM_CONFIG *Gfx; + AMD_POST_PARAMS *PostParamsPtr; + AGESA_STATUS Status; + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n"); + Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + ASSERT (Gfx != NULL); + if (Gfx != NULL) { + LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + if (GnbBuildOptions.IgfxModeAsPcieEp) { + Gfx->GfxControllerMode = GfxControllerPcieEndpointMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); + } else { + Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); + } + Gfx->StdHeader = (PVOID) StdHeader; + Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; + Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; + Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; + Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl; + Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType; + Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGating; + Gfx->UmaSteering = GnbBuildOptions.CfgUmaSteering; + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + } else { + Status = AGESA_ERROR; + } + IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h new file mode 100644 index 0000000000..ac8535ebaf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h @@ -0,0 +1,51 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFXCONFIG_H_ +#define _GNBGFXCONFIG_H_ + +#include "GfxConfigLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c new file mode 100644 index 0000000000..1c281abf79 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c @@ -0,0 +1,184 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxCardInfo.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GFX_CARD_CARD_INFO *GfxCardInfo; + PCI_ADDR BaseBridge; + UINT8 BusNumber; +} GFX_SCAN_DATA; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get information about all discrete GFX card in system + * + * + * + * @param[out] GfxCardInfo Pointer to GFX card info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_SCAN_DATA GfxScanData; + PCI_ADDR Start; + PCI_ADDR End; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n"); + Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0); + End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0); + GfxScanData.BusNumber = 5; + GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice; + GfxScanData.ScanData.StdHeader = StdHeader; + GfxScanData.GfxCardInfo = GfxCardInfo; + GnbLibPciScan (Start, End, &GfxScanData.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINT8 ClassCode; + UINT32 VendorId; + + IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n", + Device.Address.Bus, Device.Address.Device, Device.Address.Function + ); + + if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) { + UINT32 SaveBusConfiguration; + UINT32 Value; + + if (Device.Address.Bus == 0) { + ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device; + } + GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader); + ((GFX_SCAN_DATA *) ScanData)->BusNumber++; + + GnbLibPciScanSecondaryBus (Device, ScanData); + + ((GFX_SCAN_DATA *) ScanData)->BusNumber--; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + return 0; + } + GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader); + if (ClassCode == 3) { + IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n" + ); + + GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader); + if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + return 0; + } + if ((UINT16) VendorId == 0x1002) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + return 0; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h new file mode 100644 index 0000000000..7718231c21 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h @@ -0,0 +1,56 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#ifndef _GFXCARDINFO_H_ +#define _GFXCARDINFO_H_ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c new file mode 100644 index 0000000000..c9c9166610 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -0,0 +1,609 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieConfig.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +typedef struct { + PCIE_CONNECTOR_TYPE ConnectorType; + UINT8 DisplayDeviceEnum; + UINT16 ConnectorEnum; + UINT16 EncoderEnum; + UINT8 ConnectorIndex; +} EXT_CONNECTOR_INFO; + +typedef struct { + UINT8 DisplayDeviceEnum; + UINT8 DeviceIndex; + UINT16 DeviceTag; + UINT16 DeviceAcpiEnum; +} EXT_DISPLAY_DEVICE_INFO; + +typedef struct { + AGESA_STATUS Status; + UINT8 DisplayDeviceEnum; + UINT8 RequestedPriorityIndex; + UINT8 CurrentPriorityIndex; + PCIe_ENGINE_CONFIG *Engine; +} CONNECTOR_ENUM_INFO; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +EXT_CONNECTOR_INFO ConnectorInfoTable[] = { + { + ConnectorTypeDP, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0, + }, + { + ConnectorTypeEDP, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeSingleLinkDVI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 2 + }, + { + ConnectorTypeDualLinkDVI, + DEVICE_DFP, + CONNECTOR_DUAL_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 3 + }, + { + ConnectorTypeHDMI, + DEVICE_DFP, + CONNECTOR_HDMI_TYPE_A_ENUM, + ENCODER_NOT_PRESENT, + 4 + }, + { + ConnectorTypeDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_DP2VGA_ENUM_ID1, + 5 + }, + { + ConnectorTypeDpToLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_DP2LVDS_ENUM_ID2, + 6 + }, + { + ConnectorTypeStub, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_ALMOND_ENUM_ID1, + 5 + }, + { + ConnectorTypeSingleLinkDviI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_I_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeCrt, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_NOT_PRESENT, + 6 + }, + { + ConnectorTypeEDPToLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeEDPToLvdsSwInit, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeAutoDetect, + DEVICE_LCD, + CONNECTOR_LVDS_eDP_ENUM, + ENCODER_DP2LVDS_ENUM_ID2, + 7 + }, +}; + +UINT8 ConnectorNumerArray[] = { +// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, DP-to-LVDS) + 6, 1, 6, 6, 6, 1, 1, 2 +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). + * @retval Pointer to EXT_CONNECTOR_INFO + * @retval NULL if connector type unknown. + */ +STATIC EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ) +{ + UINTN Index; + for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { + return &ConnectorInfoTable[Index]; + } + } + return NULL; +} + +EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { + { + DEVICE_CRT, + 1, + ATOM_DEVICE_CRT1_SUPPORT, + 0x100, + }, + { + DEVICE_LCD, + 1, + ATOM_DEVICE_LCD1_SUPPORT, + 0x110, + }, + { + DEVICE_DFP, + 1, + ATOM_DEVICE_DFP1_SUPPORT, + 0x210, + }, + { + DEVICE_DFP, + 2, + ATOM_DEVICE_DFP2_SUPPORT, + 0x220, + }, + { + DEVICE_DFP, + 3, + ATOM_DEVICE_DFP3_SUPPORT, + 0x230, + }, + { + DEVICE_DFP, + 4, + ATOM_DEVICE_DFP4_SUPPORT, + 0x240, + }, + { + DEVICE_DFP, + 5, + ATOM_DEVICE_DFP5_SUPPORT, + 0x250, + }, + { + DEVICE_DFP, + 6, + ATOM_DEVICE_DFP6_SUPPORT, + 0x260, + } +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device enum + * @param[in] DisplayDeviceIndex Display device index + * @retval Pointer to EXT_DISPLAY_DEVICE_INFO + * @retval NULL if can not get display device info + */ +STATIC EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ) +{ + UINT8 Index; + UINT8 LastIndex; + LastIndex = 0xff; + for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { + LastIndex = Index; + if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { + return &DisplayDeviceInfoTable[Index]; + } + } + } + if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { + return &DisplayDeviceInfoTable[LastIndex]; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors + * + * + * + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe platform configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n"); + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_DFP, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_CRT, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_LCD, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegratedDdiInterfaceCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + CONNECTOR_ENUM_INFO *ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + if (ExtConnectorInfo == NULL) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status); + PcieConfigDisableEngine (Engine); + return; + } + if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) { + //Not device type we are looking for + return; + } + if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex && + Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) { + ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex; + ConnectorEnumInfo->Engine = Engine; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device list + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 DisplayDeviceIndex; + CONNECTOR_ENUM_INFO ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + AGESA_STATUS Status; + UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)]; + ConnectorEnumInfo.Status = AGESA_SUCCESS; + DisplayDeviceIndex = 1; + ConnectorEnumInfo.RequestedPriorityIndex = 0; + ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum; + LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx)); + do { + ConnectorEnumInfo.Engine = NULL; + ConnectorEnumInfo.CurrentPriorityIndex = 0xff; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegratedDdiInterfaceCallback, + &ConnectorEnumInfo, + Pcie + ); + if (ConnectorEnumInfo.Engine == NULL) { + break; // No more connector support this + } + ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType); + ASSERT (ExtConnectorInfo != NULL); + ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray)); + if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) { + //Run out of supported connectors + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + continue; + } + ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1; + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex); + if (ExtDisplayDeviceInfo == NULL) { + //Run out of supported display device types + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex; + + Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx); + AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status); + if (Status != AGESA_SUCCESS) { + continue; + } + ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++; + DisplayDeviceIndex++; + } while (ConnectorEnumInfo.Engine != NULL); + return ConnectorEnumInfo.Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPath Display path list + * @param[out] SecondaryDisplayPath Secondary display path list + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId); + DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8); + DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; + DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; + DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex; + DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex; + DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask; + DisplayPath->usCaps = Engine->Type.Ddi.DdiData.Flags; + DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum; + if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) { + if (SecondaryDisplayPath != NULL) { + SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + + if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue; + } + } +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump display path settings + * + * + * + * @param[in] DisplayPath Display path + * @param[in] Gfx Gfx configuration + */ + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n", + DisplayPath->usDeviceConnector + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n", + DisplayPath->usDeviceTag + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n", + DisplayPath->usDeviceACPIEnum + ); + IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n", + DisplayPath->usExtEncoderObjId + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n", + DisplayPath->ChannelMapping.ucChannelMapping + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChPNInvert = 0x%x\n", + DisplayPath->ucChPNInvert + ); + IDS_HDT_CONSOLE (GFX_MISC, " usCaps = 0x%x\n", + DisplayPath->usCaps + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h new file mode 100644 index 0000000000..20cf17e6f3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h @@ -0,0 +1,64 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXENUMCONNECTORS_H_ +#define _GFXENUMCONNECTORS_H_ + + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c new file mode 100644 index 0000000000..f874e084a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c @@ -0,0 +1,217 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxCardInfo.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * @param[in] StdHeader Standard configuration header + * @retval TRUE Gfx controller present and available + */ +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init Gfx SSID Registers + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT32 TempData; + PCI_ADDR IgpuAddress; + PCI_ADDR HdaudioAddress; + + Status = AGESA_SUCCESS; + TempData = 0; + + IgpuAddress = Gfx->GfxPciAddress; + HdaudioAddress = Gfx->GfxPciAddress; + HdaudioAddress.Address.Function = 1; + + // Set SSID for internal GPU + if (UserOptions.CfgGnbIGPUSSID != 0) { + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + // Set SSID for internal HD Audio + if (UserOptions.CfgGnbHDAudioSSID != 0) { + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] Source Pointer to source + * @param[in] FbOffset FB offset + * @param[in] Length The length to copy + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx00_STRUCT GMMx00; + GMMx04_STRUCT GMMx04; + UINT32 Index; + for (Index = 0; Index < Length; Index = Index + 4 ) { + GMMx00.Value = 0x80000000 | (FbOffset + Index); + GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index); + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &GMMx00.Value, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, &GMMx04.Value, GnbLibGetHeader (Gfx)); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set iGpu VGA mode + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GnbLibPciIndirectRMW ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32) ~D0F0x64_x1D_VgaEn_MASK, + ((Gfx->iGpuVgaMode == iGpuVgaAdapter) ? 1 : 0) << D0F0x64_x1D_VgaEn_OFFSET, + GnbLibGetHeader (Gfx) + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h new file mode 100644 index 0000000000..cc1d782eaf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h @@ -0,0 +1,79 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gfx Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#ifndef _GNBGFXINITLIBV1_H_ +#define _GNBGFXINITLIBV1_H_ + +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GfxEnumConnectors.h" +#include "GfxCardInfo.h" + +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c new file mode 100644 index 0000000000..7b5f3ef9de --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c @@ -0,0 +1,504 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Integrated table info init + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbF1Table.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GfxConfigLib.h" +#include "GfxIntegratedInfoTable.h" +#include "GfxPwrPlayTable.h" +#include "OptionGnb.h" +#include "GfxLibV3.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init V3 Support for eDP to Lvds translators + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegrateducEDPToLVDSRxIdCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *uceDPToLVDSRxId; + uceDPToLVDSRxId = (UINT8*) Buffer; + // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc), + // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special + // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec + // to enable the LVDS panel through this chip. + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) { + *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n"); + } + // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization + // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ). + // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just + // follows the eDP spec. to control the panel. + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvdsSwInit) { + *uceDPToLVDSRxId = eDP_TO_LVDS_SWINIT_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found EDPToLvds Connector requiring SW init\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate V3 NCLK clock + * + * + * + * @param[in] NbFid NbFid + * @param[in] NbDid NbDid + * @retval Clock in 10KHz + */ + +STATIC UINT32 +GfxLibGetNclkV3 ( + IN UINT8 NbFid, + IN UINT8 NbDid + ) +{ + UINT32 Divider; + //i.e. NBCOF[0] = (100 * ([NbFid] + 4h) / (2^[NbDid])) Mhz + if (NbDid == 1) { + Divider = 2; + } else if (NbDid == 0) { + Divider = 1; + } else { + Divider = 1; + } + ASSERT (NbDid == 0 || NbDid == 1); + return ((10000 * (NbFid + 4)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init V3 Nb p-State MemclkFreq + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] PpF1Array pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPstateMemclkFreqV3 ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN PP_F1_ARRAY_V2 *PpF1Array, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 i; + UINT8 Channel; + ULONG memps0_freq; + ULONG memps1_freq; + + Channel = 0; + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT1) != 0) { + Channel = 1; + } else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT2) != 0) { + Channel = 2; + } else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT3) != 0) { + Channel = 3; + } + + + memps0_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) PpF1Array->MemClkFreq[Channel], GnbLibGetHeader (Gfx)); + memps1_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) PpF1Array->M1MemClkFreq[Channel], GnbLibGetHeader (Gfx)); + + for (i = 0; i < 4; i++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld26[i] == 1) { + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (PpF1Array->PP_FUSE_ARRAY_V2_fld29[i] == 0) ? memps0_freq : memps1_freq; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init V3 NbPstateVid + * + * + * @param[in] PpF1Array + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPStateVidV3 ( + IN PP_F1_ARRAY_V2 *PpF1Array, + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 i; + + for (i = 0; i < 4; i++) { + IntegratedInfoTable->usNBPStateVoltage[i] = (USHORT) ((PpF1Array->PP_FUSE_ARRAY_V2_fld28[i] << 7) | (PpF1Array->PP_FUSE_ARRAY_V2_fld27[i])); + IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkV3 ((UINT8) (PpF1Array->PP_FUSE_ARRAY_V2_fld30[i]), (UINT8) (PpF1Array->PP_FUSE_ARRAY_V2_fld31[i])); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] SystemInfoTableV3Ptr Pointer to integrated info table + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxIntInfoTablePostToFbV3 ( + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Index; + UINT32 TableOffset; + UINT32 FbAddress; + TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V3)) | 0x80000000; + for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V3); Index = Index + 4 ) { + FbAddress = TableOffset + Index; + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV3Ptr + Index, GnbLibGetHeader (Gfx)); + } +} + + +STATIC VOID +GfxIntegratedInfoTable289_fun ( + IN PP_F1_ARRAY_V2 *PpF1Array, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + for (Index = 0; Index < 4; Index++) { + if (PpF1Array->excel841_fld6[Index] != 0) { + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld4[Index].ulMaximumSupportedCLK = GfxFmCalculateClock ( + PpF1Array->excel841_fld6[Index], + GnbLibGetHeader (Gfx) + ); + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld4[Index].ulVoltageIndex = (ULONG) Index; + } + } +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC VOID +GfxIntegratedInfoTable318_fun ( + IN PP_F1_ARRAY_V2 *PpF1Array, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 Index; + UINTN v1; + GnbGfx275_STRUCT *pv2; + BOOLEAN Sorting; + pv2 = &IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8[0]; + + v1 = 0; + for (Index = 0; Index < 5; Index++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index] != 0) { + pv2[v1].GnbGfx275_STRUCT_fld0 = GfxFmCalculateClock (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index], GnbLibGetHeader (Gfx)); + pv2[v1].GnbGfx275_STRUCT_fld1 = Index; + pv2[v1].GnbGfx275_STRUCT_fld2 = PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index]; + v1++; + } + } + if (v1 > 1) { + do { + Sorting = FALSE; + for (Index = 0; Index < (v1 - 1); Index++) { + GnbGfx275_STRUCT Temp; + BOOLEAN Exchange; + Exchange = FALSE; + if (pv2[Index].GnbGfx275_STRUCT_fld1 > pv2[Index + 1].GnbGfx275_STRUCT_fld1) { + Exchange = TRUE; + } + if ((pv2[Index].GnbGfx275_STRUCT_fld1 == pv2[Index + 1].GnbGfx275_STRUCT_fld1) && + (pv2[Index].GnbGfx275_STRUCT_fld0 > pv2[Index + 1].GnbGfx275_STRUCT_fld0)) { + Exchange = TRUE; + } + if (Exchange) { + Sorting = TRUE; + LibAmdMemCopy (&Temp, &pv2[Index], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&pv2[Index], &pv2[Index + 1], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&pv2[Index + 1], &Temp, sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + } + } + } while (Sorting); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * + * + * + * @param[in] Gfx Gfx configuration info + * @param[in] SystemInfoTableV3 ATOM_FUSION_SYSTEM_INFO_V3 pointer + * @param[in] PpF1Array + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntInfoTableInitV3 ( + IN GFX_PLATFORM_CONFIG *Gfx, + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3, + IN PP_F1_ARRAY_V2 *PpF1Array + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + ATOM_PPLIB_POWERPLAYTABLE4 *PpTable; + UINT8 Channel; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Enter\n"); + + if (PpF1Array != NULL) { + + Channel = 0; + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT1) != 0) { + Channel = 1; + } else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT2) != 0) { + Channel = 2; + } else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT3) != 0) { + Channel = 3; + } + SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8); + ASSERT (SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize == 512); + SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableContentRevision = 8; + SystemInfoTableV3->sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ + SystemInfoTableV3->sIntegratedSysInfo.field2 = (PpF1Array->PP_FUSE_ARRAY_V2_fld21 + 0x10) * 10000; + SystemInfoTableV3->sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; + + SystemInfoTableV3->sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; + SystemInfoTableV3->sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; + SystemInfoTableV3->sIntegratedSysInfo.ucMemoryType = Gfx->UmaInfo.MemType; + SystemInfoTableV3->sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndexV5 (GnbLibGetHeader (Gfx)); + SystemInfoTableV3->sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; + SystemInfoTableV3->sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; + //Locate PCIe configuration data to get definitions of display connectors + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport; + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucFixDPVoltageSwing = (UINT8) Gfx->DpFixedVoltSwingType; + SystemInfoTableV3->sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8, sExtDispConnInfo); + + SystemInfoTableV3->sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; + + SystemInfoTableV3->sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value); + if (Gfx->LvdsMiscControl.Field.LvdsVoltOverwriteEn) { + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSVoltAdjust = Gfx->LVDSVoltAdjust; + IDS_HDT_CONSOLE (GNB_TRACE, "LVDSVoltAdjust : %x\n", Gfx->LVDSVoltAdjust); + } + + SystemInfoTableV3->sIntegratedSysInfo.ulVBIOSMisc = Gfx->DisplayMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value); + + // LVDS + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon; + SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl; + SystemInfoTableV3->sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue; + SystemInfoTableV3->sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq; + SystemInfoTableV3->sIntegratedSysInfo.ucMinAllowedBL_Level = Gfx->MinAllowedBLLevel; + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + Status = GfxIntegratedEnumerateAllConnectors ( + &SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sPath[0], + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegrateducEDPToLVDSRxIdCallback, + &SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId, + Pcie + ); + + // Build PP table + PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3->ulPowerplayTable; + // Build PP table + ///@todo + //Status = GfxPowerPlayBuildTable (PpTable, Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + // Assign usFormatID to 0x000B to represent V3 + ///@todo + PpTable->usFormatID = 0xB; + // Build Display clock info + GfxIntegratedInfoTable289_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx); + GfxIntegratedInfoTable318_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx); + ///@todo review if these parameters needed + // Fill in Nb P-state MemclkFreq Data + GfxFillNbPstateMemclkFreqV3 (&SystemInfoTableV3->sIntegratedSysInfo, PpF1Array, Gfx); + // Fill in HTC Data + if (PpF1Array->HtcEn == 1) { + SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = (UCHAR) (PpF1Array->HtcTmpLmt / 2 + 52); + SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = (UCHAR) (PpF1Array->PP_FUSE_ARRAY_V2_fld20 / 2); + } else { + SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = 0; + SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = 0; + } + // Fill in NB P states VID & NCLK info + GfxFillNbPStateVidV3 (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx); + + // Family specific data update - store default values to be updated by family specific code + //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + SystemInfoTableV3->sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; + SystemInfoTableV3->sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; + + if (PpF1Array->MemPhyPllPdMode[Channel] != 0) { + SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT2; + } + if (PpF1Array->DisDllShutdownSR[Channel] == 0) { + SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT1; + } + if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) { + SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT0; + } + SystemInfoTableV3->sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE; + + IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig); + + } else { + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump gfx integrated info table + * + * + * @param[in] SystemInfoTableV3Ptr Pointer to integrated info table + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxIntInfoTableDebugDumpV3 ( + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ATOM_PPLIB_POWERPLAYTABLE4 *PpTable; + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + + IDS_HDT_CONSOLE (GFX_MISC, "GfxIntInfoTableDebugDumpV3 Enter\n"); + + PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3Ptr->ulPowerplayTable; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) (PpTable) + PpTable->usExtendendedHeaderOffset); + IDS_HDT_CONSOLE (GFX_MISC, " ExtendedHeader usSize %d\n", ExtendedHeader->usSize); + IDS_HDT_CONSOLE (GFX_MISC, " SizeOf %d\n", sizeof(ATOM_PPLIB_EXTENDEDHEADER)); + + IDS_HDT_CONSOLE (GFX_MISC, " ucHtcTmpLmt 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ucHtcTmpLmt); + IDS_HDT_CONSOLE (GFX_MISC, " ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11); + IDS_HDT_CONSOLE (GFX_MISC, "GfxIntInfoTableDebugDumpV3 Exit\n"); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.h new file mode 100644 index 0000000000..562f815ea2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various GfxIntegratedInfoTable definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXINTEGRATEDINFOTABLE_H_ +#define _GFXINTEGRATEDINFOTABLE_H_ + +AGESA_STATUS +GfxIntInfoTableInitV3 ( + IN GFX_PLATFORM_CONFIG *Gfx, + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3, + IN PP_F1_ARRAY_V2 *PpF1Array + ); + +VOID +GfxIntInfoTablePostToFbV3 ( + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntInfoTableDebugDumpV3 ( + IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +// GMMx00/x04 are required for copying table to frame buffer +#ifndef GMMx00_ADDRESS + #define GMMx00_ADDRESS 0x0 + #define GMMx04_ADDRESS 0x4 +#endif + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c new file mode 100644 index 0000000000..1ad00c9c5f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c @@ -0,0 +1,257 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific GFX library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbGfx.h" +#include "GfxLibV3.h" +#include "GnbSmuInitLibV7.h" +#include "GnbCommonLib.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXLIBV3_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST UINT16 GfxMemClockFrequencyDefinitionTableV3 [][8] = { +{0, 0, 0, 0, 333, 0, 400, 0}, +{0, 0, 533, 0, 0, 0, 667, 0}, +{0, 0, 800, 0, 0, 0, 933, 0}, +{0, 1050, 1066, 0, 0, 0, 0, 0} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Extract DRAM frequency + * + * + * + * @param[in] Encoding Memory Clock Frequency Value Definition + * @param[in] StdHeader Standard configuration header + * @retval Dram frequency Mhz + */ +UINT32 +GfxLibExtractDramFrequencyV3 ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTableV3) / sizeof (UINT16))) { + ASSERT (FALSE); + return 0; + } + return GfxMemClockFrequencyDefinitionTableV3[Encoding / 8][Encoding % 8]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable GMM Access for gBIF BAR Arrangement + * + * + * + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxEnableGmmAccessV3 ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address + Gfx->GmmBase = 0; + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + Gfx->GmmBase |= (Value & 0xfffffff0); + if (Gfx->GmmBase == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for FB allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + if ((Value & 0xfffffff0) == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + //Push CPU MMIO pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + // Turn on memory decoding on GFX to enable access to GMM register space + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push iGPU pci config to S3 script + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power Up/Down iGPU + * + * + * + * @param[in,out] Gfx Pointer to GFX configuration + * @param[in,out] PowerControl Control power Up/Down iGPU, 0, power down iGPU, 1, power on iGPU + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxRequestGPUPowerV3 ( + IN OUT GFX_PLATFORM_CONFIG *Gfx, + IN UINT8 PowerControl + ) +{ + GNB_HANDLE *GnbHandle; + DEV_OBJECT DevObject; + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = GnbLibGetHeader (Gfx); + + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine number of audio ports for each connector + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntAudioEpEnumCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *AudioCount; + AudioCount = (UINT8*) Buffer; + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n"); + (*AudioCount)++; + } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) { + if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n"); + *AudioCount += 4; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n"); + (*AudioCount)++; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate audio endpoint in all display connectors. + * + * + * + * @param[in] Gfx Gfx configuration info + * @param[in, out] AudioEPCount Total Audio endpoint number + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntAudioEPEnumV3 ( + IN GFX_PLATFORM_CONFIG *Gfx, + IN OUT UINT8 *AudioEPCount + ) +{ + UINT8 NumAudioEp; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntAudioEPEnumV3 Enter\n"); + + NumAudioEp = 0; + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + GfxIntAudioEpEnumCallback, + &NumAudioEp, + Pcie + ); + + if (Gfx->GnbRemoteDisplaySupport) { + NumAudioEp++; + } + } + + *AudioEPCount = NumAudioEp; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntAudioEPEnumV3 Exit\n"); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h new file mode 100644 index 0000000000..1c7938d0e9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h @@ -0,0 +1,70 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various GFX service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXLIBV3_H_ +#define _GFXLIBV3_H_ + +UINT32 +GfxLibExtractDramFrequencyV3 ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxEnableGmmAccessV3 ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxRequestGPUPowerV3 ( + IN OUT GFX_PLATFORM_CONFIG *Gfx, + IN UINT8 PowerControl + ); + +AGESA_STATUS +GfxIntAudioEPEnumV3 ( + IN GFX_PLATFORM_CONFIG *Gfx, + IN OUT UINT8 *AudioEPCount + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c new file mode 100644 index 0000000000..4e83c44359 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c @@ -0,0 +1,1233 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 67269 $ @e \$Date: 2012-03-26 02:53:08 -0500 (Mon, 26 Mar 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbF1Table.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GfxPwrPlayTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/// Software state +typedef struct { + BOOLEAN Valid; ///< State valid + UINT16 Classification; ///< State classification + UINT32 CapsAndSettings; ///< State capability and settings + UINT16 Classification2; ///< State classification2 + UINT32 SW_STATE_fld4; + UINT32 SW_STATE_fld5; + UINT8 SW_STATE_fld6; + UINT8 SW_STATE_fld7[10]; +} SW_STATE; + +typedef struct { + BOOLEAN Valid; + UINT32 GfxPwrPlayTable120_STRUCT_fld1; + UINT8 Vid; + UINT16 Tdp; +} GfxPwrPlayTable120_STRUCT; + +typedef struct { + GFX_PLATFORM_CONFIG *Gfx; + ATOM_PPLIB_POWERPLAYTABLE4 *PpTable; + PP_F1_ARRAY_V2 *PpF1s; + SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES]; ///< SW state array + GfxPwrPlayTable120_STRUCT PP_WORKSPACE_V2_fld4[10]; + UINT8 NumOfClockVoltageLimitEnties; /// + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD VceClockVoltageLimitArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceClockEnties; + GfxPwrPlayTable204_STRUCT VceClockInfoArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceStateEntries; + ATOM_PPLIB_VCE_STATE_RECORD VceStateArray[MAX_NUM_OF_VCE_STATES]; ///< VCE state array + UINT8 NumOfUvdClkVoltLimitEntries; /// + ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD UvdClkVoltLimitArray[MAX_NUM_OF_UVD_CLK_STATES]; + UINT8 NumOfUvdClockEntries; + GfxPwrPlayTable261_STRUCT UvdClockInfoArray[MAX_NUM_OF_UVD_CLK_STATES]; + UINT8 PP_WORKSPACE_V2_fld15; /// + ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD PP_WORKSPACE_V2_fld16[MAX_NUM_OF_SAMCLK_STATES]; + UINT8 PP_WORKSPACE_V2_fld17; /// + GfxPwrPlayTable310_STRUCT PP_WORKSPACE_V2_fld18[5]; +} PP_WORKSPACE_V2; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GfxIntDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE4 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Create new software state + * + * + * @param[in, out] PpWorkspace PP workspace + * @retval Pointer to state entry in SW state array + */ + +STATIC SW_STATE * +GfxPwrPlayCreateSwState ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINTN Index; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid == FALSE) { + PpWorkspace->SwStateArray[Index].Valid = TRUE; + return &(PpWorkspace->SwStateArray[Index]); + } + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC UINT8 +GfxPwrPlayTable192_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT32 fv1, + IN UINT8 Vid + ) +{ + UINT8 Index; + + for (Index = 0; Index < 10; Index++) { + if (PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Valid == FALSE) { + PpWorkspace->PP_WORKSPACE_V2_fld4[Index].GfxPwrPlayTable120_STRUCT_fld1 = fv1; + PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Vid = Vid; + PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Valid = TRUE; + PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Tdp = 0; + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC UINT8 +GfxPwrPlayTable224_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT32 fv1, + IN UINT8 Vid + ) +{ + UINT8 Index; + + for (Index = 0; Index < 10; Index++) { + if (PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Valid && + fv1 == PpWorkspace->PP_WORKSPACE_V2_fld4[Index].GfxPwrPlayTable120_STRUCT_fld1 && + Vid == PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Vid) { + + return Index; + } + } + + Index = GfxPwrPlayTable192_fun (PpWorkspace, fv1, Vid); + + return Index; +} + + +STATIC VOID +GfxPwrPlayTable256_fun ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ) +{ + SwStateArray->SW_STATE_fld7[SwStateArray->SW_STATE_fld6++] = DpmStateIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy SW state info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ +STATIC VOID * +GfxPwrPlayAttachStateInfoBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 Index; + UINT8 SwStateIndex; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *States; + StateArray = (STATE_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + States = &StateArray->States[0]; + SwStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].SW_STATE_fld6 != 0) { + States->nonClockInfoIndex = SwStateIndex; + States->ATOM_PPLIB_STATE_V2_fld0 = PpWorkspace->SwStateArray[Index].SW_STATE_fld6; + LibAmdMemCopy ( + &States->ClockInfoIndex[0], + PpWorkspace->SwStateArray[Index].SW_STATE_fld7, + PpWorkspace->SwStateArray[Index].SW_STATE_fld6, + GnbLibGetHeader (PpWorkspace->Gfx) + ); + States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ATOM_PPLIB_STATE_V2_fld0 - 1)); + SwStateIndex++; + } + } + StateArray->ucNumEntries = SwStateIndex; + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray); + return StateArray; +} +/*----------------------------------------------------------------------------------------*/ +/** + * Copy clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachClockInfoBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + CLOCK_INFO_ARRAY *ClockInfoArray; + UINT8 Index; + UINT8 ClkStateIndex; + ClkStateIndex = 0; + ClockInfoArray = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + for (Index = 0; Index < 10; Index++) { + if (PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Valid == TRUE) { + ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (PpWorkspace->PP_WORKSPACE_V2_fld4[Index].GfxPwrPlayTable120_STRUCT_fld1 >> 16); + ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (PpWorkspace->PP_WORKSPACE_V2_fld4[Index].GfxPwrPlayTable120_STRUCT_fld1); + ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].ATOM_PPLIB_SUMO_CLOCK_INFO_fld3 = PpWorkspace->PP_WORKSPACE_V2_fld4[Index].Tdp; + ClkStateIndex++; + } + } + ClockInfoArray->ucNumEntries = ClkStateIndex; + ClockInfoArray->ucEntrySize = sizeof (GfxPwrPlayTable143_STRUCT); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (CLOCK_INFO_ARRAY) + sizeof (GfxPwrPlayTable143_STRUCT) * ClkStateIndex - sizeof (GfxPwrPlayTable143_STRUCT); + return ClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy non clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachNonClockInfoBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + NON_CLOCK_INFO_ARRAY *NonClockInfoArray; + UINT8 Index; + UINT8 NonClkStateIndex; + + NonClockInfoArray = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + NonClkStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].SW_STATE_fld6 != 0) { + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = PpWorkspace->SwStateArray[Index].Classification; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = PpWorkspace->SwStateArray[Index].CapsAndSettings; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = PpWorkspace->SwStateArray[Index].Classification2; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ATOM_PPLIB_NONCLOCK_INFO_fld7 = PpWorkspace->SwStateArray[Index].SW_STATE_fld5; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ATOM_PPLIB_NONCLOCK_INFO_fld6 = PpWorkspace->SwStateArray[Index].SW_STATE_fld4; + NonClkStateIndex++; + } + } + NonClockInfoArray->ucNumEntries = NonClkStateIndex; + NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO); + return NonClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if state valid + * + * + * @param[out] Index State index + * @param[in] PpF1s Pointer + * @param[in] Gfx Gfx configuration info + * @retval TRUE State is valid + */ +STATIC BOOLEAN +GfxPwrPlayIsF1dStateValid ( + IN UINT8 Index, + IN PP_F1_ARRAY_V2 *PpF1s, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + BOOLEAN Result; + Result = FALSE; + if ((PpF1s->PP_FUSE_ARRAY_V2_fld37 & (1 << Index)) || (PpF1s->PP_FUSE_ARRAY_V2_fld38 & (1 << Index))) { + Result = TRUE; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC VOID +GfxPwrPlayTable437_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 ClkStateIndex; + UINT8 DpmF1Index; + UINT32 fv2; + SW_STATE *State; + PP_F1_ARRAY_V2 *PpF1s; + + PpF1s = PpWorkspace->PpF1s; + + // Create Battery state + State = GfxPwrPlayCreateSwState (PpWorkspace); + + State->Classification = ATOM_PPLIB_CLASSIFICATION_UI_BATTERY; + State->Classification2 = 0; + State->SW_STATE_fld4 = 0; + State->SW_STATE_fld5 = 0; + if (PpWorkspace->Gfx->AbmSupport != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT; + } + if (PpWorkspace->Gfx->DynamicRefreshRate != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR; + } + + for (DpmF1Index = 0; DpmF1Index < 5; DpmF1Index++) { + + if (PpF1s->PP_FUSE_ARRAY_V2_fld38 & (1 << DpmF1Index)) { + + fv2 = (PpF1s->PP_FUSE_ARRAY_V2_fld33[DpmF1Index] != 0) ? + GfxFmCalculateClock (PpF1s->PP_FUSE_ARRAY_V2_fld33[DpmF1Index], + GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + + if (fv2 != 0) { + ClkStateIndex = GfxPwrPlayTable224_fun (PpWorkspace, fv2, PpF1s->PP_FUSE_ARRAY_V2_fld32[DpmF1Index]); + GfxPwrPlayTable256_fun (State, ClkStateIndex); + } + } + } + + // Create Performance state + State = GfxPwrPlayCreateSwState (PpWorkspace); + + State->Classification = ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE; + State->Classification2 = 0; + State->SW_STATE_fld4 = 0; + State->SW_STATE_fld5 = 0; + + // Loop through fused DPM states and find those that go with Performance + for (DpmF1Index = 0; DpmF1Index < 5; DpmF1Index++) { + + if (PpF1s->PP_FUSE_ARRAY_V2_fld37 & (1 << DpmF1Index)) { + + fv2 = (PpF1s->PP_FUSE_ARRAY_V2_fld33[DpmF1Index] != 0) ? + GfxFmCalculateClock (PpF1s->PP_FUSE_ARRAY_V2_fld33[DpmF1Index], + GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + + if (fv2 != 0) { + ClkStateIndex = GfxPwrPlayTable224_fun (PpWorkspace, fv2, PpF1s->PP_FUSE_ARRAY_V2_fld32[DpmF1Index]); + GfxPwrPlayTable256_fun (State, ClkStateIndex); + } + } + } + + // Create Boot State + State = GfxPwrPlayCreateSwState (PpWorkspace); + State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; + fv2 = 200 * 100; + ClkStateIndex = GfxPwrPlayTable224_fun (PpWorkspace, fv2, 0); + GfxPwrPlayTable256_fun (State, ClkStateIndex); + +} + + +/*----------------------------------------------------------------------------------------*/ + +STATIC UINT8 +GfxPwrPlayAddEclkState ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT32 Eclk + ) +{ + UINT8 Index; + USHORT EclkLow; + UCHAR EclkHigh; + EclkLow = (USHORT) (Eclk & 0xffff); + EclkHigh = (UCHAR) (Eclk >> 16); + for (Index = 0; Index < PpWorkspace->NumOfVceClockEnties; Index++) { + if (PpWorkspace->VceClockInfoArray[Index].ucECClkHigh == EclkHigh && PpWorkspace->VceClockInfoArray[Index].usECClkLow == EclkLow) { + return Index; + } + } + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucECClkHigh = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usECClkLow = EclkLow; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].GfxPwrPlayTable204_STRUCT_fld1 = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].GfxPwrPlayTable204_STRUCT_fld0 = EclkLow; + return PpWorkspace->NumOfVceClockEnties++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add ECLK state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] EclkIndex ECLK index + * @param[in] Vid Vid index + * @retval Index of state entry in Eclk Voltage record array + */ + +STATIC UINT8 +GfxPwrPlayAddEclkVoltageRecord ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT8 EclkIndex, + IN UINT8 Vid + ) +{ + UINT8 Index; + for (Index = 0; Index < PpWorkspace->NumOfClockVoltageLimitEnties; Index++) { + if (PpWorkspace->VceClockVoltageLimitArray[Index].ucVCEClockInfoIndex == EclkIndex) { + return Index; + } + } + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].ucVCEClockInfoIndex = EclkIndex; + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].usVoltage = Vid; + return PpWorkspace->NumOfClockVoltageLimitEnties++; +} + + +/*----------------------------------------------------------------------------------------*/ + +STATIC UINT8 +GfxPwrPlayTable588_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT32 fv1, + IN UINT32 fv2 + ) +{ + UINT8 Index; + USHORT v1; + UCHAR v2; + USHORT v3; + UCHAR v4; + v1 = (USHORT) (fv1 & 0xffff); + v2 = (UCHAR) (fv1 >> 16); + v3 = (USHORT) (fv2 & 0xffff); + v4 = (UCHAR) (fv2 >> 16); + for (Index = 0; Index < PpWorkspace->NumOfUvdClockEntries; Index++) { + if (PpWorkspace->UvdClockInfoArray[Index].GfxPwrPlayTable261_STRUCT_fld1 == v2 && + PpWorkspace->UvdClockInfoArray[Index].GfxPwrPlayTable261_STRUCT_fld0 == v1) { + return Index; + } + } + PpWorkspace->UvdClockInfoArray[PpWorkspace->NumOfUvdClockEntries].GfxPwrPlayTable261_STRUCT_fld1 = v2; + PpWorkspace->UvdClockInfoArray[PpWorkspace->NumOfUvdClockEntries].GfxPwrPlayTable261_STRUCT_fld0 = v1; + PpWorkspace->UvdClockInfoArray[PpWorkspace->NumOfUvdClockEntries].GfxPwrPlayTable261_STRUCT_fld3 = v4; + PpWorkspace->UvdClockInfoArray[PpWorkspace->NumOfUvdClockEntries].GfxPwrPlayTable261_STRUCT_fld2 = v3; + return PpWorkspace->NumOfUvdClockEntries++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add Uvd voltage record + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] ClkIndex CLK index + * @param[in] Vid Vid index + * @retval Index of state entry in Eclk Voltage record array + */ + +STATIC UINT8 +GfxPwrPlayAddUvdVoltageRecord ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT8 ClkIndex, + IN UINT8 Vid + ) +{ + UINT8 Index; + for (Index = 0; Index < PpWorkspace->NumOfUvdClkVoltLimitEntries; Index++) { + if (PpWorkspace->UvdClkVoltLimitArray[Index].ucUVDClockInfoIndex == ClkIndex) { + return Index; + } + } + PpWorkspace->UvdClkVoltLimitArray[PpWorkspace->NumOfUvdClkVoltLimitEntries].ucUVDClockInfoIndex = + ClkIndex; + PpWorkspace->UvdClkVoltLimitArray[PpWorkspace->NumOfUvdClkVoltLimitEntries].usVoltage = Vid; + return PpWorkspace->NumOfUvdClkVoltLimitEntries++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add Samu voltage record + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Vid Vid + * @param[in] Samclk CLK associated with the Vid + * @retval Index of state entry in Voltage record array + */ + +STATIC UINT8 +GfxPwrPlayAddSamuVoltageRecord ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace, + IN UINT8 Vid, + IN UINT32 Samclk + ) +{ + UINT8 Index; + USHORT SamclkLow; + UCHAR SamclkHigh; + SamclkLow = (USHORT) (Samclk & 0xffff); + SamclkHigh = (UCHAR) (Samclk >> 16); + for (Index = 0; Index < PpWorkspace->PP_WORKSPACE_V2_fld15; Index++) { + if ((PpWorkspace->PP_WORKSPACE_V2_fld16[Index].usSAMClockHigh == SamclkHigh) && + (PpWorkspace->PP_WORKSPACE_V2_fld16[Index].usSAMClockLow == SamclkLow) && + (PpWorkspace->PP_WORKSPACE_V2_fld16[Index].usVoltage == Vid) + ) { + return Index; + } + } + PpWorkspace->PP_WORKSPACE_V2_fld16[PpWorkspace->PP_WORKSPACE_V2_fld15].usSAMClockHigh = + SamclkHigh; + PpWorkspace->PP_WORKSPACE_V2_fld16[PpWorkspace->PP_WORKSPACE_V2_fld15].usSAMClockLow = + SamclkLow; + PpWorkspace->PP_WORKSPACE_V2_fld16[PpWorkspace->PP_WORKSPACE_V2_fld15].usVoltage = Vid; + return PpWorkspace->PP_WORKSPACE_V2_fld15++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach extended header + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachExtendedHeaderBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) + ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + ExtendedHeader->usSize = sizeof (ATOM_PPLIB_EXTENDEDHEADER); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_EXTENDEDHEADER); + return ExtendedHeader; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach Vce Rev Block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachVceTableRevBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_TABLE *VceTable; + VceTable = (ATOM_PPLIB_VCE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceTable->revid = 0; + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_VCE_TABLE); + return VceTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE clock info block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachVceClockInfoBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + VCECLOCKINFOARRAY *VceClockInfoArray; + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockInfoArray->ucNumEntries = PpWorkspace->NumOfVceClockEnties; + LibAmdMemCopy ( + &VceClockInfoArray->entries[0], + &PpWorkspace->VceClockInfoArray[0], + VceClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable204_STRUCT), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable204_STRUCT) - + sizeof (GfxPwrPlayTable204_STRUCT); + return VceClockInfoArray; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE voltage limit block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachVceVoltageLimitBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockVoltageLimitTable->numEntries = PpWorkspace->NumOfClockVoltageLimitEnties; + LibAmdMemCopy ( + &VceClockVoltageLimitTable->entries[0], + &PpWorkspace->VceClockVoltageLimitArray[0], + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = + PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD); + return VceClockVoltageLimitTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE state block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachVceStateTableBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceStateTable->numEntries = PpWorkspace->NumOfVceStateEntries; + LibAmdMemCopy ( + &VceStateTable->entries[0], + &PpWorkspace->VceStateArray[0], + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_STATE_TABLE) + + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD) - + sizeof (ATOM_PPLIB_VCE_STATE_RECORD); + return VceStateTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach Uvd Rev Block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachUvdTableRevBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_UVD_TABLE *UvdTable; + UvdTable = (ATOM_PPLIB_UVD_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + UvdTable->revid = 0; + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_UVD_TABLE); + return UvdTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach UVD clock info block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachUvdClockInfoBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + GfxPwrPlayTable267_STRUCT *UvdClockInfoArray; + UvdClockInfoArray = (GfxPwrPlayTable267_STRUCT *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + UvdClockInfoArray->ucNumEntries = PpWorkspace->NumOfUvdClockEntries; + LibAmdMemCopy ( + &UvdClockInfoArray->entries[0], + &PpWorkspace->UvdClockInfoArray[0], + UvdClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable261_STRUCT), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (GfxPwrPlayTable267_STRUCT) + + UvdClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable261_STRUCT) - + sizeof (GfxPwrPlayTable261_STRUCT); + return UvdClockInfoArray; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach UVD voltage limit block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachUvdVoltageLimitBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UVD_CLK_VOLT_LIMIT_TABLE *UvdClockVoltageLimitTable; + UvdClockVoltageLimitTable = (UVD_CLK_VOLT_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + UvdClockVoltageLimitTable->numEntries = PpWorkspace->NumOfUvdClkVoltLimitEntries; + LibAmdMemCopy ( + &UvdClockVoltageLimitTable->entries[0], + &PpWorkspace->UvdClkVoltLimitArray[0], + UvdClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = + PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (UVD_CLK_VOLT_LIMIT_TABLE) + + UvdClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD); + return UvdClockVoltageLimitTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach SAMU Rev Block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachSamuTableRevBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_SAMU_TABLE *VceTable; + VceTable = (ATOM_PPLIB_SAMU_TABLE *) ((UINT8 *) PpWorkspace->PpTable + + PpWorkspace->PpTable->sHeader.usStructureSize); + VceTable->revid = 0; + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_SAMU_TABLE); + return VceTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach SAMU voltage limit block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayAttachSamuVoltageLimitBlock ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *SamuClockVoltageLimitTable; + SamuClockVoltageLimitTable = (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *) + ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + SamuClockVoltageLimitTable->numEntries = PpWorkspace->PP_WORKSPACE_V2_fld15; + LibAmdMemCopy ( + &SamuClockVoltageLimitTable->entries[0], + &PpWorkspace->PP_WORKSPACE_V2_fld16[0], + SamuClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = + PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE) + + SamuClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD); + return SamuClockVoltageLimitTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach Sclk Volt Dep Block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPwrPlayTable956_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + GfxPwrPlayTable316_STRUCT *v0; + + v0 = (GfxPwrPlayTable316_STRUCT *) + ((UINT8 *) PpWorkspace->PpTable + + PpWorkspace->PpTable->sHeader.usStructureSize); + v0->numEntries = PpWorkspace->PP_WORKSPACE_V2_fld17; + LibAmdMemCopy ( + &v0->entries[0], + &PpWorkspace->PP_WORKSPACE_V2_fld18[0], + 5 * sizeof (GfxPwrPlayTable310_STRUCT), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = + PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (GfxPwrPlayTable316_STRUCT) + + v0->numEntries * sizeof (GfxPwrPlayTable310_STRUCT) - + sizeof (GfxPwrPlayTable310_STRUCT); + + + return v0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build VCE state info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPwrPlayBuildVceStateTable ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 Index; + UINT8 VceStateIndex; + UINT8 Vid; + UINT32 Eclk; + UINT32 v4; + UINT8 UsedStateBitmap; + UsedStateBitmap = 0; + // build used state + for (Index = 0; + Index < (sizeof (PpWorkspace->PpF1s->VceFlags) / + sizeof (PpWorkspace->PpF1s->VceFlags[0])) ; + Index++) { + UsedStateBitmap |= PpWorkspace->PpF1s->VceFlags[Index]; + for (VceStateIndex = 0; + VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / + sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex++) { + if ((PpWorkspace->PpF1s->VceFlags[Index] & (1 << VceStateIndex)) != 0) { + v4 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld33[PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld16[Index]], + GnbLibGetHeader (PpWorkspace->Gfx)); + Vid = PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld32[PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld16[Index]]; + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = + GfxPwrPlayTable224_fun (PpWorkspace, v4, Vid); + if (PpWorkspace->PpF1s->VceMclk) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex |= + (PpWorkspace->PpF1s->VceMclk << 6); + } + Eclk = GfxFmCalculateClock (PpWorkspace->PpF1s->EclkDid[Index], + GnbLibGetHeader (PpWorkspace->Gfx)); + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = + GfxPwrPlayAddEclkState (PpWorkspace, Eclk); + GfxPwrPlayAddEclkVoltageRecord (PpWorkspace, + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex, Vid); + PpWorkspace->NumOfVceStateEntries++; + } + } + } + //build unused states + for (VceStateIndex = 0; + VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); + VceStateIndex++) { + if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPwrPlayAddEclkState (PpWorkspace, 0); + PpWorkspace->NumOfVceStateEntries++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC VOID +GfxPwrPlayBuildUvdClockTable ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 Index; + UINT8 Vid; + UINT32 v2; + UINT32 v3; + UINT8 UsedStateBitmap; + UINT8 UvdIndex; + + UsedStateBitmap = 0; + // build used state + for (Index = 0; Index < MAX_NUM_OF_UVD_CLK_STATES ; Index++) { + if (GfxPwrPlayIsF1dStateValid (Index, PpWorkspace->PpF1s, PpWorkspace->Gfx)) { + Vid = PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld32[Index]; + v2 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld1[Index], + GnbLibGetHeader (PpWorkspace->Gfx)); + v3 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld2[Index], + GnbLibGetHeader (PpWorkspace->Gfx)); + UvdIndex = GfxPwrPlayTable588_fun (PpWorkspace, v2, v3); + GfxPwrPlayAddUvdVoltageRecord (PpWorkspace, + UvdIndex, Vid); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build SAMU info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPwrPlayBuildSamuTable ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 SamuIndex; + UINT8 Vid; + UINT32 Samuclk; + UINT8 UsedStateBitmap; + UsedStateBitmap = 0; + // build used state + for (SamuIndex = 0; SamuIndex < MAX_NUM_OF_SAMCLK_STATES; SamuIndex++) { + if (GfxPwrPlayIsF1dStateValid (SamuIndex, PpWorkspace->PpF1s, PpWorkspace->Gfx)) { + Vid = PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld32[SamuIndex]; + Samuclk = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld34[SamuIndex], + GnbLibGetHeader (PpWorkspace->Gfx)); + GfxPwrPlayAddSamuVoltageRecord (PpWorkspace, Vid, Samuclk); + } + } +} + +/*----------------------------------------------------------------------------------------*/ + +STATIC VOID +GfxPwrPlayTable1122_fun ( + IN OUT PP_WORKSPACE_V2 *PpWorkspace + ) +{ + UINT8 v0; + UINT8 Vid; + UINT32 v2; + USHORT v3; + UCHAR v4; + + // build the table + for (v0 = 0; v0 < 5; v0++) { + Vid = PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld32[v0]; + v2 = GfxFmCalculateClock (PpWorkspace->PpF1s->PP_FUSE_ARRAY_V2_fld33[v0], + GnbLibGetHeader (PpWorkspace->Gfx)); + ASSERT (Vid != 0) + ASSERT (v2 != 0) + v3 = (USHORT) (v2 & 0xffff); + v4 = (UCHAR) (v2 >> 16); + PpWorkspace->PP_WORKSPACE_V2_fld18[v0].GfxPwrPlayTable310_fld2 = Vid; + PpWorkspace->PP_WORKSPACE_V2_fld18[v0].GfxPwrPlayTable310_fld1 = v4; + PpWorkspace->PP_WORKSPACE_V2_fld18[v0].GfxPwrPlayTable310_fld0 = v3; + PpWorkspace->PP_WORKSPACE_V2_fld17++; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build PP table + * + * + * @param[out] Buffer Buffer to create PP table + * @param[in] Gfx Gfx configuration info + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GfxPwrPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + PP_WORKSPACE_V2 PpWorkspace; + VOID *BlockPtr; + + LibAmdMemFill (&PpWorkspace, 0x00, sizeof (PP_WORKSPACE_V2), GnbLibGetHeader (Gfx)); + PpWorkspace.PpF1s = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpWorkspace.PpF1s != NULL); + if (PpWorkspace.PpF1s == NULL) { + return AGESA_ERROR; + } + + PpWorkspace.PpTable = (ATOM_PPLIB_POWERPLAYTABLE4 *) Buffer; + PpWorkspace.Gfx = Gfx; + //Fill static info + PpWorkspace.PpTable->sHeader.ucTableFormatRevision = 6; + PpWorkspace.PpTable->sHeader.ucTableContentRevision = 1; + PpWorkspace.PpTable->ucDataRevision = PpWorkspace.PpF1s->PPlayTableRev; + PpWorkspace.PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_KV; + PpWorkspace.PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN; + PpWorkspace.PpTable->sHeader.usStructureSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE4); + PpWorkspace.PpTable->usTableSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE4); + PpWorkspace.PpTable->usFormatID = 0x13; + if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + PpWorkspace.PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY; + } + + + GfxPwrPlayTable437_fun (&PpWorkspace); + + // Fill Eclk state info + if (PpWorkspace.PpF1s->PP_FUSE_ARRAY_V2_fld13) { + GfxPwrPlayBuildVceStateTable (&PpWorkspace); + GfxPwrPlayBuildUvdClockTable (&PpWorkspace); + GfxPwrPlayBuildSamuTable (&PpWorkspace); + GfxPwrPlayTable1122_fun (&PpWorkspace); + } + + //Copy state info to actual PP table + BlockPtr = GfxPwrPlayAttachStateInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usStateArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPwrPlayAttachClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPwrPlayAttachNonClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usNonClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + + if (PpWorkspace.PpF1s->PP_FUSE_ARRAY_V2_fld13) { + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = + (ATOM_PPLIB_EXTENDEDHEADER *) GfxPwrPlayAttachExtendedHeaderBlock (&PpWorkspace); + PpWorkspace.PpTable->usExtendendedHeaderOffset = + (USHORT) ((UINT8 *) ExtendedHeader - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPwrPlayAttachVceTableRevBlock (&PpWorkspace); + ExtendedHeader->usVCETableOffset = + (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + GfxPwrPlayAttachVceClockInfoBlock (&PpWorkspace); + GfxPwrPlayAttachVceVoltageLimitBlock (&PpWorkspace); + GfxPwrPlayAttachVceStateTableBlock (&PpWorkspace); + + BlockPtr = GfxPwrPlayAttachUvdTableRevBlock (&PpWorkspace); + ExtendedHeader->usUVDTableOffset = + (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + GfxPwrPlayAttachUvdClockInfoBlock (&PpWorkspace); + GfxPwrPlayAttachUvdVoltageLimitBlock (&PpWorkspace); + + BlockPtr = GfxPwrPlayAttachSamuTableRevBlock (&PpWorkspace); + ExtendedHeader->usSAMUTableOffset = + (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + GfxPwrPlayAttachSamuVoltageLimitBlock (&PpWorkspace); + + BlockPtr = GfxPwrPlayTable956_fun (&PpWorkspace); + PpWorkspace.PpTable->ATOM_PPLIB_POWERPLAYTABLE4_fld17 = + (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + + IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader \n"); + IDS_HDT_CONSOLE (GNB_TRACE, " VceTableOffset = %04x\n", ExtendedHeader->usVCETableOffset); + IDS_HDT_CONSOLE (GNB_TRACE, " UvdTableOffset = %04x\n", ExtendedHeader->usUVDTableOffset); + IDS_HDT_CONSOLE (GNB_TRACE, " SamTableOffset = %04x\n", ExtendedHeader->usSAMUTableOffset); + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + + } + GNB_DEBUG_CODE ( + GfxIntDebugDumpPpTable (PpWorkspace.PpTable, Gfx); + ); + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump PP table + * + * + * + * @param[in] PpTable Power Play table + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE4 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *StatesPtr; + NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr; + CLOCK_INFO_ARRAY *ClockInfoArrayPtr; + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VCECLOCKINFOARRAY *VceClockInfoArray; + GfxPwrPlayTable267_STRUCT *UvdClockInfoArray; + UVD_CLK_VOLT_LIMIT_TABLE *UvdClockVoltLimitTable; + ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *SamuClockVoltLimitTable; + UINT8 EclkIndex; + + IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n"); + IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision); + StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset); + StatesPtr = StateArray->States; + NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset); + ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); + IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); + for (Index = 0; Index < StateArray->ucNumEntries; Index++) { + IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification2 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2 + ); + IDS_HDT_CONSOLE (GFX_MISC, "\n"); + StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ATOM_PPLIB_STATE_V2_fld0 - 1); + } + if (PpTable->usExtendendedHeaderOffset != 0) { + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + + PpTable->usExtendendedHeaderOffset); + + IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader = %08x\n", ExtendedHeader); + + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpTable + + ExtendedHeader->usVCETableOffset + sizeof (ATOM_PPLIB_VCE_TABLE)); + VceClockVoltageLimitTable = + (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) VceClockInfoArray + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable204_STRUCT) - + sizeof (GfxPwrPlayTable204_STRUCT)); + VceStateTable = + (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) VceClockVoltageLimitTable + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD)); + UvdClockInfoArray = + (GfxPwrPlayTable267_STRUCT *) ((UINT8 *) PpTable + ExtendedHeader->usUVDTableOffset + + sizeof (ATOM_PPLIB_UVD_TABLE)); + UvdClockVoltLimitTable = + (UVD_CLK_VOLT_LIMIT_TABLE *) ((UINT8 *) UvdClockInfoArray + sizeof (GfxPwrPlayTable267_STRUCT) + + UvdClockInfoArray->ucNumEntries * sizeof (GfxPwrPlayTable261_STRUCT) - + sizeof (GfxPwrPlayTable261_STRUCT)); + SamuClockVoltLimitTable = + (ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE *) + ((UINT8 *) PpTable + ExtendedHeader->usSAMUTableOffset + sizeof (ATOM_PPLIB_SAMU_TABLE)); + + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]--> \n", VceStateTable->numEntries); + + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); + for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { + EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + VceClockVoltageLimitTable->entries[Index].usVoltage + ); + } + + + IDS_HDT_CONSOLE (GFX_MISC, " < --- SAMU Voltage Record Table ---> \n"); + for (Index = 0; Index < SamuClockVoltLimitTable->numEntries; Index++) { + IDS_HDT_CONSOLE (GFX_MISC, " SAMU Voltage Record #%d\n", Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " SAMCLK = %d\n", + SamuClockVoltLimitTable->entries[Index].usSAMClockLow | + (SamuClockVoltLimitTable->entries[Index].usSAMClockHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + SamuClockVoltLimitTable->entries[Index].usVoltage + ); + } + } + + IDS_HDT_CONSOLE (GFX_MISC, " PplayDumpExit\n"); + +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h new file mode 100644 index 0000000000..05895ced55 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h @@ -0,0 +1,321 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Power Play Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 63366 $ @e \$Date: 2011-12-21 14:49:48 -0600 (Wed, 21 Dec 2011) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXPWRPLAYTABLE_H_ +#define _GFXPWRPLAYTABLE_H_ + +#pragma pack (push, 1) + +#define POLICY_LABEL_BATTERY 0x1 +#define POLICY_LABEL_PERFORMANCE 0x2 + +#define MAX_NUM_OF_SW_STATES 3 +#define MAX_NUM_OF_VCE_CLK_STATES 5 +#define MAX_NUM_OF_VCE_STATES 6 +#define MAX_NUM_OF_UVD_CLK_STATES 5 +#define MAX_NUM_OF_SAMCLK_STATES 5 +/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps +#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 +#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 +#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 +#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 +#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 +#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 +#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 +#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 +#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 +#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 +#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 +#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 +#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 +#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. +#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). +#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does +#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000ul // Enable the 'regulator hot' feature. +#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000ul // Does the driver supports BACO state. + + +#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 +#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 +#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 + +#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 +#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 +#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 +#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 +#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 +#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 +#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 +#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 +#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 +#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 +#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 +#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 +#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 +#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 + +#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View + +#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000ul +#define ATOM_PPLIB_ENABLE_DRR 0x00080000ul + +#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 +#define ATOM_PP_THERMALCONTROLLER_KV 0x13 + +typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { + USHORT usEngineClockLow; + UCHAR ucEngineClockHigh; + UCHAR vddcIndex; + USHORT ATOM_PPLIB_SUMO_CLOCK_INFO_fld3; + USHORT rsv1; + ULONG rsv2[2]; +} GfxPwrPlayTable143_STRUCT; + +/// Non clock info +typedef struct _ATOM_PPLIB_NONCLOCK_INFO { + USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* + UCHAR ucMinTemperature; ///< Reserved + UCHAR ucMaxTemperature; ///< Reserved + ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) + UCHAR ucRequiredPower; ///< Reserved + USHORT usClassification2; ///< Reserved + ULONG ATOM_PPLIB_NONCLOCK_INFO_fld6; + ULONG ATOM_PPLIB_NONCLOCK_INFO_fld7; + UCHAR ucUnused[5]; ///< Reserved +} ATOM_PPLIB_NONCLOCK_INFO; + +/// Thermal controller info stub +typedef struct _ATOM_PPLIB_THERMALCONTROLLER { + UCHAR ucType; ///< Reserved. Should be set 0xE + UCHAR ucI2cLine; ///< Reserved. Should be set 0 + UCHAR ucI2cAddress; ///< Reserved. Should be set 0 + UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 + UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 + UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 + UCHAR ucReserved; ///< Reserved. Should be set 0 + UCHAR ucFlags; ///< Reserved. Should be set 0 +} ATOM_PPLIB_THERMALCONTROLLER; + +/// SW state info +typedef struct _ATOM_PPLIB_STATE_V2 { + UCHAR ATOM_PPLIB_STATE_V2_fld0; + UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos + UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration +} ATOM_PPLIB_STATE_V2; + +/// SW state Array +typedef struct { + UCHAR ucNumEntries; ///< Number of SW states + ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration +} STATE_ARRAY; + +/// Clock info Array +typedef struct { + UCHAR ucNumEntries; ///< Number of ClockInfo entries + UCHAR ucEntrySize; + GfxPwrPlayTable143_STRUCT ClockInfo[1]; +} CLOCK_INFO_ARRAY; + +/// Non clock info Array +typedef struct { + + UCHAR ucNumEntries; ///< Number of Entries; + UCHAR ucEntrySize; ///< Size of NonClockInfo + ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array +} NON_CLOCK_INFO_ARRAY; + +/// VCE clock info +typedef struct { + USHORT GfxPwrPlayTable204_STRUCT_fld0; + UCHAR GfxPwrPlayTable204_STRUCT_fld1; + USHORT usECClkLow; + UCHAR ucECClkHigh; +} GfxPwrPlayTable204_STRUCT; + +/// VCE clock info array +typedef struct { + UCHAR ucNumEntries; + GfxPwrPlayTable204_STRUCT entries[1]; +} VCECLOCKINFOARRAY; + +/// VCE voltage limit record +typedef struct { + USHORT usVoltage; ///< Voltage index + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD; + +/// VCE voltage limit table +typedef struct { + UCHAR numEntries; ///< Number of entries + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1]; ///< Voltage limit state array +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE; + +/// VCE state record +typedef struct { + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state + UCHAR ucClockInfoIndex; +} ATOM_PPLIB_VCE_STATE_RECORD; + +/// VCE state table +typedef struct { + UCHAR numEntries; ///< Number of state entries + ATOM_PPLIB_VCE_STATE_RECORD entries[1]; ///< State entries +} ATOM_PPLIB_VCE_STATE_TABLE; + +/// Extended header +typedef struct { + USHORT usSize; ///< size of header + ULONG rsv15; ///< reserved + ULONG rsv16; ///< reserved + USHORT usVCETableOffset; ///< offset of ATOM_PPLIB_VCE_TABLE + USHORT usUVDTableOffset; ///< offset of ATOM_PPLIB_UVD_TABLE + USHORT usSAMUTableOffset; ///< offset of ATOM_PPLIB_SAMU_TABLE + USHORT usPPMTableOffset; ///< offset of ATOM_PPLIB_PPM_TABLE + USHORT usACPTableOffset; ///< offset of ATOM_PPLIB_ACP_TABLE + USHORT usCACTDPTableOffset; ///< offset of ATOM_PPLIB_CACTDP_TABLE +} ATOM_PPLIB_EXTENDEDHEADER; + +/// VCE table +typedef struct { + UCHAR revid; ///< revision ID +} ATOM_PPLIB_VCE_TABLE; + + +typedef struct { + USHORT GfxPwrPlayTable261_STRUCT_fld0; + UCHAR GfxPwrPlayTable261_STRUCT_fld1; + USHORT GfxPwrPlayTable261_STRUCT_fld2; + UCHAR GfxPwrPlayTable261_STRUCT_fld3; +} GfxPwrPlayTable261_STRUCT; + +/// UVD clock info array +typedef struct { + UCHAR ucNumEntries; + GfxPwrPlayTable261_STRUCT entries[1]; +} GfxPwrPlayTable267_STRUCT; + +/// VCE voltage limit record +typedef struct { + USHORT usVoltage; ///< Voltage index + UCHAR ucUVDClockInfoIndex; ///< Index of VCE clock state +} ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD; + +/// VCE voltage limit table +typedef struct { + UCHAR numEntries; ///< Number of entries + ATOM_PPLIB_UVD_CLK_VOLT_LIMIT_RECORD entries[1]; ///< Voltage limit state array +} UVD_CLK_VOLT_LIMIT_TABLE; + +/// UVD table +typedef struct { + UCHAR revid; ///< revision ID +} ATOM_PPLIB_UVD_TABLE; + +/// SAMU voltage limit record +typedef struct { + USHORT usVoltage; ///< voltage + USHORT usSAMClockLow; ///< SamClk low + UCHAR usSAMClockHigh; ///< SamClk high +} ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD; + +/// SAMU voltage limit table +typedef struct { + UCHAR numEntries; ///< number of entries + ATOM_PPLIB_SAMCLK_VOLT_LIMIT_RECORD entries[1]; ///< array of entries +} ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE; + +/// SAMU table +typedef struct { + UCHAR revid; ///< table revision id +// ATOM_PPLIB_SAMCLK_VOLT_LIMIT_TABLE limits; ///< offset of table +} ATOM_PPLIB_SAMU_TABLE; + +typedef struct { + USHORT GfxPwrPlayTable310_fld0; + UCHAR GfxPwrPlayTable310_fld1; + USHORT GfxPwrPlayTable310_fld2; +} GfxPwrPlayTable310_STRUCT; + +typedef struct { + UCHAR numEntries; + GfxPwrPlayTable310_STRUCT entries[1]; +} GfxPwrPlayTable316_STRUCT; + +#define ATOM_PPM_A_A 1 +#define ATOM_PPM_A_I 2 + +/// Power Play table +typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header + UCHAR ucDataRevision; ///< Revision of PP table + UCHAR Reserved1[4]; ///< Reserved + USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures + USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray + USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray + USHORT Reserved2[2]; ///< Reserved + USHORT usTableSize; ///< the size of this structure, or the extended structure + ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* + ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. + USHORT Reserved4[2]; ///< Reserved + UCHAR Reserved5; ///< Reserved + USHORT Reserved6; ///< Reserved + USHORT usFormatID; ///< Format ID + USHORT Reserved7[1]; ///< Reserved + USHORT usExtendendedHeaderOffset; ///< Extended header offset + ULONG Reserved8[2]; ///< Reserved + USHORT ATOM_PPLIB_POWERPLAYTABLE4_fld17; + USHORT Reserved9[5]; ///< Reserved +} ATOM_PPLIB_POWERPLAYTABLE4; + +#pragma pack (pop) + + +AGESA_STATUS +GfxPwrPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c new file mode 100644 index 0000000000..30ec1b368a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "AlibSsdtKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_ALIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtKB[0]; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h new file mode 100644 index 0000000000..eb3c21f80d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h @@ -0,0 +1,3230 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87932 $ @e \$Date: 2013-02-13 13:53:55 -0600 (Wed, 13 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _ALIBSSDTKB_H_ +#define _ALIBSSDTKB_H_ + +UINT8 AlibSsdtKB[] = { + 0x53, 0x53, 0x44, 0x54, 0x52, 0x63, 0x00, 0x00, + 0x02, 0x82, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x8D, 0x32, 0x06, + 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x47, + 0x52, 0x42, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x08, + 0x41, 0x44, 0x42, 0x47, 0x11, 0x04, 0x0B, 0x00, + 0x01, 0x08, 0x41, 0x44, 0x41, 0x54, 0x11, 0x45, + 0x20, 0x0B, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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"File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86586 $ @e \$Date: 2013-01-23 12:45:26 -0600 (Wed, 23 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbGfxFamServices.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbHandleLib.h" +#include "cpuFamilyTranslation.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxEnvInitTableKB[]; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxStrapsEnvInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D0F0xD4_x010914E1_STRUCT D0F0xD4_x10914E1; + D0F0xD4_x010914E2_STRUCT D0F0xD4_x10914E2; + D0F0xD4_x01091507_STRUCT D0F0xD4_x1091507; + D0F0x64_x1D_STRUCT D0F0x64_x1D; + UINT32 D0F0xD4_x010914C3; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEnvInitKB Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914E1_TYPE, D0F0xD4_x010914E1_ADDRESS, &D0F0xD4_x10914E1.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914E2_TYPE, D0F0xD4_x010914E2_ADDRESS, &D0F0xD4_x10914E2.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x01091507_TYPE, D0F0xD4_x01091507_ADDRESS, &D0F0xD4_x1091507.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914C3_TYPE, D0F0xD4_x010914C3_ADDRESS, &D0F0xD4_x010914C3, 0, GnbLibGetHeader (Gfx)); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1D.Field.VgaEn = 0x1; + + D0F0xD4_x10914E2.Field.bita = 0x0; + D0F0xD4_x10914E2.Field.bita = 0x0; + D0F0xD4_x1091507.Field.bit16 = Gfx->GnbHdAudio; + D0F0xD4_x10914E2.Field.bit13 = Gfx->GnbHdAudio; + + D0F0xD4_x10914E1.Field.StrapBifRegApSize = 0x2; + D0F0xD4_x10914E1.Field.StrapBifDoorbellBarDis = 0x0; + D0F0xD4_x10914E1.Field.Bitfield_13_13 = 0x0; + D0F0xD4_x10914E1.Field.Bitfield_15_14 = 0x3; + + if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x1; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x1; + } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x0; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x0; + } else { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x2; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x2; + } + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0xD4_x010914C3 |= BIT0; + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914E1_TYPE, D0F0xD4_x010914E1_ADDRESS, &D0F0xD4_x10914E1.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914E2_TYPE, D0F0xD4_x010914E2_ADDRESS, &D0F0xD4_x10914E2.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x01091507_TYPE, D0F0xD4_x01091507_ADDRESS, &D0F0xD4_x1091507.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914C3_TYPE, D0F0xD4_x010914C3_ADDRESS, &D0F0xD4_x010914C3, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEnvInitKB Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Env Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + GNB_HANDLE *GnbHandle; + UINT32 Property; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Property = TABLE_PROPERTY_DEFAULT; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + // Power up iGPU + GfxRequestGPUPowerV3 (Gfx, 1); + Status = GfxStrapsEnvInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GfxEnvInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceKB Exit [0x%x]\n", AgesaStatus); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c new file mode 100644 index 0000000000..234592bfb3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c @@ -0,0 +1,375 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87849 $ @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccKB.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersKB.h" +#include "GfxLibKB.h" +#include "GfxGmcInitKB.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXGMCINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_TABLE ROMDATA GfxGmcFeature1DisableKB []; +extern GNB_TABLE ROMDATA GfxGmcInitTableKB []; +extern GNB_TABLE ROMDATA GfxGmcFeature1EnableKB []; + + +#define GNB_GFX_DRAM_CH_0_PRESENT 1 +#define GNB_GFX_DRAM_CH_1_PRESENT 2 + +#define DRAMTYPE_DDR3 1 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize Fb location + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeFbLocationKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx2024; + UINT32 GMMx2068; + UINT32 GMMx2C04; + UINT32 GMMx5428; + UINT64 FBBase; + UINT64 FBTop; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitializeFbLocationKB Enter\n"); + + FBBase = 0x0F00000000; + FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; + GMMx2024 = 0; + GMMx2C04 = 0; + GMMx2024 |= (UINT16) (FBBase >> 24); + GMMx2024 |= (UINT32) ((FBTop >> 24) << 16); + GMMx2068 = (UINT32) (Gfx->UmaInfo.UmaBase >> 22); + GMMx2C04 = (UINT32) (FBBase >> 8); + GMMx5428 = Gfx->UmaInfo.UmaSize >> 20; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2024, &GMMx2024, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2068, &GMMx2068, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2C04, &GMMx2C04, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x5428, &GMMx5428, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitializeFbLocationKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize sequencer model + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeHubAndCitfSteeringKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx2004; + UINT32 GMMx2008; + + GMMx2004 = 0x2210; + GMMx2008 = 0; + + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2004, &GMMx2004, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2008, &GMMx2008, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Stutter Mode with/without power-gating + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcEnableStutterModePowerGatingKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx3508; + UINT32 GMMx350C; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcEnableStutterModePowerGatingKB Enter\n"); + + GnbRegisterReadKB (GnbHandle, 0x12, 0x3508, &GMMx3508, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x350C, &GMMx350C, 0, GnbLibGetHeader (Gfx)); + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + // Enabling power gating + if (Gfx->GmcPowerGating == GmcPowerGatingWithStutter) { + GMMx3508 |= 1; + GMMx350C |= 1 << 11; + GMMx350C &= ~(1 << 16); + } else { + GMMx3508 &= ~1; + GMMx350C &= ~(1 << 11); + GMMx350C |= 1 << 16; + } + GnbRegisterWriteKB (GnbHandle, 0x12, 0x3508, &GMMx3508, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x350C, &GMMx350C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } else { + // Disabling power gating + GMMx3508 &= ~1; + GMMx350C &= ~(1 << 11); + GMMx350C &= ~(1 << 16); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x3508, &GMMx3508, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x350C, &GMMx350C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcEnableStutterModePowerGatingKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcSecureGarlicAccessKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 v1; + UINT32 v2; + UINT32 v3; + + v1 = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2868, &v1, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + v2 = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x286C, &v2, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + // Area FB - 32K reserved by VBIOS for SBIOS to use + v3 = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2878, &v3, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize C6 aperture location + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeC6LocationKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x118_STRUCT D18F2x118; + D18F1x44_STRUCT D18F1x44; + UINT32 GMMx2870; + UINT32 GMMx2874; + + // Check C6 enable, D18F2x118[CC6SaveEn] + GnbRegisterReadKB (GnbHandle, D18F2x118_TYPE, D18F2x118_ADDRESS, &D18F2x118.Value, 0, GnbLibGetHeader (Gfx)); + + if (D18F2x118.Field.CC6SaveEn) { + // From D18F1x[144:140,44:40] DRAM Base/Limit, + // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}. + GnbRegisterReadKB (GnbHandle, D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx)); + // + // base 39:20, base = Dram Limit + 1 + // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1) + // Node DRAM D18F1x[144:140,44:40] CC6DRAMRange D18F4x128 D18F1x120 D18F1x124 + // 0 256MB 0MB ~ 240 MB - 1 240 MB ~ 256 MB - 1 0 0 MB, 256 MB - 1 + // + + // base 39:20 + GMMx2870 = ((D18F1x44.Field.DramLimit_39_24 + 1) << 4); + // top 39:20 + GMMx2874 = (((D18F1x44.Field.DramLimit_39_24 + 1) << 24) + (16 * 0x100000) - 1) >> 20; + + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2870, &GMMx2870, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2874, &GMMx2874, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxGmcInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 v1; + UINT32 GMMx25E8; + D18F3x44_STRUCT D18F3x44; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitKB Enter\n"); +//2.1 Disable clock-gating + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbProcessTable ( + GnbHandle, + GfxGmcFeature1DisableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); +//2.3 HUB & CITF channel steering + GfxGmcInitializeHubAndCitfSteeringKB (GnbHandle, Gfx); +//2.6 Frame buffer location + GfxGmcInitializeFbLocationKB (GnbHandle, Gfx); +//2.8 Securing GARLIC access +//2.8.1 GARLIC request disable + GfxGmcSecureGarlicAccessKB (GnbHandle, Gfx); +//2.8.2 C6 save aperture + GfxGmcInitializeC6LocationKB (GnbHandle, Gfx); +//2.2 System memory address translation +//2.4 Sequencer model programming +//2.5 Power Gating - PGFSM and RENG init +//2.7 Performance tuning +//2.10 Display latency +//2.11 Remove blackout + GnbProcessTable ( + GnbHandle, + GfxGmcInitTableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); +//4. Power management + GnbProcessTable ( + GnbHandle, + GfxGmcFeature1EnableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + +// SETUP or BLDCFG may override. + switch (Gfx->UmaSteering) { + case 0: + v1 = 0; + GnbRegisterReadKB (GnbHandle, D18F3x44_TYPE, D18F3x44_ADDRESS, &D18F3x44.Value, 0, GnbLibGetHeader (Gfx)); + if (D18F3x44.Field.DramEccEn == 1) { + v1 = SystemTrafficOnion; + } + break; + case SystemTrafficOnion: + v1 = SystemTrafficOnion; + break; + case Onion: + v1 = Onion; + break; + case 3: + v1 = 3; + break; + default: + v1 = 0; + ASSERT (FALSE); + break; + } + GnbRegisterWriteKB (GnbHandle, 0x12, 0x206C, &v1, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); + + GnbRegisterReadKB (GnbHandle, 0x12, 0x25E8, &GMMx25E8, 0, GnbLibGetHeader (Gfx)); + GMMx25E8 |= BIT14; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x25E8, &GMMx25E8, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + //4.2 Enabling stutter mode with or without power-gating + GfxGmcEnableStutterModePowerGatingKB (GnbHandle, Gfx); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitKB Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h new file mode 100644 index 0000000000..a6b63cafcf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXGMCINITKB_H_ +#define _GFXGMCINITKB_H_ + +#include "GnbRegistersKB.h" + +AGESA_STATUS +GfxGmcInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c new file mode 100644 index 0000000000..c81fd5ee3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c @@ -0,0 +1,526 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Integrated table info init + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87902 $ @e \$Date: 2013-02-12 15:59:48 -0600 (Tue, 12 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbF1Table.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbNbInitLibV1.h" +#include "GfxConfigLib.h" +#include "GfxIntegratedInfoTable.h" +#include "GfxPwrPlayTable.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXINTEGRATEDINFOTABLEKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define GFX_REFCLK 100 // (in MHz) Reference clock is 100 MHz + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxMapEngineToDisplayPathKB ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntInfoTableInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +CONST UINT8 DdiLaneConfigArrayKB [][4] = { + {8, 11, 0, 0}, + {12, 15, 1, 1}, + {11, 8, 0, 0}, + {15, 12, 1, 1}, + {16, 19, 6, 6}, + {19, 16, 6, 6} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPathList Display path list + * @param[in] Gfx Pointer to global GFX configuration + */ + +AGESA_STATUS +GfxMapEngineToDisplayPathKB ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT8 PrimaryDisplayPathId; + UINT8 SecondaryDisplayPathId; + UINTN DisplayPathIndex; + PrimaryDisplayPathId = 0xff; + SecondaryDisplayPathId = 0xff; + for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArrayKB) / 4); DisplayPathIndex++) { + if (DdiLaneConfigArrayKB[DisplayPathIndex][0] == Engine->EngineData.StartLane && + DdiLaneConfigArrayKB[DisplayPathIndex][1] == Engine->EngineData.EndLane) { + PrimaryDisplayPathId = DdiLaneConfigArrayKB[DisplayPathIndex][2]; + SecondaryDisplayPathId = DdiLaneConfigArrayKB[DisplayPathIndex][3]; + break; + } + } + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds && PrimaryDisplayPathId != 0)) { + // Display config invalid for KB + PrimaryDisplayPathId = 0xff; + } + + if (PrimaryDisplayPathId != 0xff) { + ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3); + IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); + Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; + GfxIntegratedCopyDisplayInfo ( + Engine, + &DisplayPathList[PrimaryDisplayPathId], + (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, + Gfx + ); + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) { + LibAmdMemCopy (&DisplayPathList[6], &DisplayPathList[PrimaryDisplayPathId], sizeof (EXT_DISPLAY_PATH), GnbLibGetHeader (Gfx)); + DisplayPathList[6].usDeviceACPIEnum = 0x100; + DisplayPathList[6].usDeviceTag = ATOM_DEVICE_CRT1_SUPPORT; + } + + Status = AGESA_SUCCESS; + } else { + IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", + Engine->EngineData.StartLane, + Engine->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, + Engine->EngineData.StartLane, + Engine->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Gfx) + ); + Status = AGESA_ERROR; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init KB Nb p-State MemclkFreq + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPstateMemclkFreqKB ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x94_dct0_STRUCT D18F2x94; + D18F2x2E0_dct0_STRUCT D18F2x2E0; + D18F5x160_STRUCT NbPstate; + UINT8 i; + ULONG memps0_freq; + ULONG memps1_freq; + UINT8 last_valid_pstate; + GNB_HANDLE *GnbHandle; + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + + GnbRegisterReadKB ( + GnbHandle, + D18F2x94_dct0_TYPE, + D18F2x94_dct0_ADDRESS, + &D18F2x94.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + GnbRegisterReadKB ( + GnbHandle, + D18F2x2E0_dct0_TYPE, + D18F2x2E0_dct0_ADDRESS, + &D18F2x2E0.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + memps0_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + + last_valid_pstate = 0; + for (i = 0; i < 4; i++) { + NbPstate.Value = 0; + GnbRegisterReadKB ( + GnbHandle, + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate.Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate.Field.NbPstateEn == 1) { + last_valid_pstate = i; + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq; + } else { + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = + IntegratedInfoTable->ulNbpStateMemclkFreq[last_valid_pstate]; + } + } + + for (i = 0; i < 4; i++) { + IDS_HDT_CONSOLE (GNB_TRACE, " Nclk[%d] = %08x\n", i, IntegratedInfoTable->ulNbpStateNClkFreq[i]); + IDS_HDT_CONSOLE (GNB_TRACE, " Mclk[%d] = %08x\n", i, IntegratedInfoTable->ulNbpStateMemclkFreq[i]); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Calculate ulGMCRestoreResetTime + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + * @param[in] PpF1Array + * @retval AGESA_STATUS + */ +///@todo - this is currently based on TN +STATIC AGESA_STATUS +GfxCalculateRestoreResetTimeKB ( + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx, + IN PP_F1_ARRAY_V2 *PpF1Array + ) +{ + UINT8 MaxDid; + ULONG FreqSclk; + UINTN Index; + UINT32 TSclk; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeKB Enter\n"); + MaxDid = PpF1Array->PP_FUSE_ARRAY_V2_fld3; + for (Index = 0; Index < 4; Index++) { + MaxDid = MAX (MaxDid, PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index]); + } + IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid); + FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx)); + // FreqSclk is in 10KHz units - need calculations in nS + // For accuracy, do calculations in .01nS, then convert at the end + TSclk = (100 * (1000000000 / 10000)) / FreqSclk; + + IntegratedInfoTable->ulGMCRestoreResetTime = ((TSclk * 662) + 99) / 100; + IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeKB Exit\n"); + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init KB HTC Data + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillHtcDataKB ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F3x64_STRUCT D18F3x64; + GNB_HANDLE *GnbHandle; + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + + GnbRegisterReadKB ( + GnbHandle, + D18F3x64_TYPE, + D18F3x64_ADDRESS, + &D18F3x64.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + if (D18F3x64.Field.HtcEn == 1) { + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); + } else { + IntegratedInfoTable->ucHtcTmpLmt = 0; + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = 0; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Sclk <-> VID table + * + * + * @param[in] PpF1Array + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitSclkTableKB ( + IN PP_F1_ARRAY_V2 *PpF1Array, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 Index; + UINTN AvailSclkIndex; + GnbGfx275_STRUCT *AvailSclkList; + BOOLEAN Sorting; + AvailSclkList = &IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8[0]; + + AvailSclkIndex = 0; + for (Index = 0; Index < 5; Index++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index] != 0) { + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld0 = GfxFmCalculateClock (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index], GnbLibGetHeader (Gfx)); + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld1 = Index; + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld2 = PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index]; + AvailSclkIndex++; + } + } + //Sort by VoltageIndex & GnbGfx275_STRUCT_fld0 + if (AvailSclkIndex > 1) { + do { + Sorting = FALSE; + for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { + GnbGfx275_STRUCT Temp; + BOOLEAN Exchange; + Exchange = FALSE; + if (AvailSclkList[Index].GnbGfx275_STRUCT_fld1 > AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld1) { + Exchange = TRUE; + } + if ((AvailSclkList[Index].GnbGfx275_STRUCT_fld1 == AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld1) && + (AvailSclkList[Index].GnbGfx275_STRUCT_fld0 > AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld0)) { + Exchange = TRUE; + } + if (Exchange) { + Sorting = TRUE; + LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + } + } + } while (Sorting); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * + * + * + * @param[in] Gfx Gfx configuration info + * @retval AGESA_STATUS + */ +AGESA_STATUS +STATIC +GfxIntInfoTableInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + ATOM_FUSION_SYSTEM_INFO_V3 SystemInfoTableV3; + PP_F1_ARRAY_V2 *PpF1Array; + ATOM_PPLIB_POWERPLAYTABLE4 *PpTable; + D18F5x170_STRUCT D18F5x170; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInitKB Enter\n"); + + AgesaStatus = AGESA_SUCCESS; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + if (PpF1Array != NULL) { + LibAmdMemFill (&SystemInfoTableV3, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V3), GnbLibGetHeader (Gfx)); + + // Use common initialization first + Status = GfxIntInfoTableInitV3 (Gfx, &SystemInfoTableV3, PpF1Array); + // Complete table with KB-specific fields + + // Build PP table + PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3.ulPowerplayTable; + Status = GfxPwrPlayBuildTable (PpTable, Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "KB Pplay done\n"); + + // Assign usFormatID to 0x0013 to represent Kabini + PpTable->usFormatID = 0x13; + + // Build Sclk info table + GfxIntInfoTableInitSclkTableKB (PpF1Array, &SystemInfoTableV3.sIntegratedSysInfo, Gfx); + + // Fill in Nb P-state MemclkFreq Data + GfxFillNbPstateMemclkFreqKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx); + // Fill in HTC Data + GfxFillHtcDataKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx); + + // Family specific data update + // Determine ulGMCRestoreResetTime + Status = GfxCalculateRestoreResetTimeKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx, PpF1Array); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + SystemInfoTableV3.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; + SystemInfoTableV3.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; + + SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo = + GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE | + GPUCAPINFO_DP_USE_SINGLE_PLL_MODE | + GPUCAPINFO_DFS_BYPASS_DISABLE; + + // GPUCAPINFO_DFS_BYPASS_ENABLE should be enabled by default for MOBILE systems + if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo |= GPUCAPINFO_DFS_BYPASS_ENABLE; + } + + // Check if NbPstate enable + GnbRegisterReadKB (GnbHandle, TYPE_D18F5, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx)); + if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) { + // If NbPstate enable, then enable NBDPM for driver + SystemInfoTableV3.sIntegratedSysInfo.ulSystemConfig |= BIT3; + } + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV3.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); + //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) + GfxIntInfoTablePostToFbV3 (&SystemInfoTableV3, Gfx); + + GNB_DEBUG_CODE ( + GfxIntInfoTableDebugDumpV3 (&SystemInfoTableV3, Gfx); + ); + } else { + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInitKB Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * GMC FB access requred + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntInfoTableInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (GfxLibIsControllerPresent (StdHeader)) { + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_FATAL) { + Status = GfxIntInfoTableInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInterfaceKB Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c new file mode 100644 index 0000000000..7523736eb3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c @@ -0,0 +1,192 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific GFX library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbGfx.h" +#include "GfxLibKB.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXLIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GfxDisableControllerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxCalculateClockKB ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxIsVbiosPostedKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable GFX controller + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxDisableControllerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS), + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0x7C_ForceIntGfxDisable_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get system PLL COF + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval System PLL COF + */ +UINT32 +GfxLibGetSystemPllCofKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 v0; + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0500000, &v0, 0, StdHeader); + return 100 * (((v0 >> 1) & 0x3F) + 0x10); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate COF for DFS out of Main PLL + * + * + * + * @param[in] Did Did + * @param[in] StdHeader Standard Configuration Header + * @retval COF in 10khz + */ + +UINT32 +GfxCalculateClockKB ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + SystemPllCof = GfxLibGetSystemPllCofKB (StdHeader) * 100; + if (Did >= 8 && Did <= 0x3F) { + Divider = Did * 25; + } else if (Did > 0x3F && Did <= 0x5F) { + Divider = (Did - 64) * 50 + 1600; + } else if (Did > 0x5F && Did <= 0x7E) { + Divider = (Did - 96) * 100 + 3200; + } else if (Did == 0x7f) { + Divider = 128 * 100; + } else { + ASSERT (FALSE); + return 200 * 100; + } + ASSERT (Divider != 0); + return (((SystemPllCof * 100) + (Divider - 1)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if Video BIOS has posted or not + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +BOOLEAN +GfxIsVbiosPostedKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 D0F0xBC_xC0200000; + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Gfx)), 0x4, 0xC0200000, &D0F0xBC_xC0200000, 0, GnbLibGetHeader (Gfx)); + + return (((D0F0xBC_xC0200000 >> 16) & 1) == 0) ? TRUE : FALSE; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h new file mode 100644 index 0000000000..117a794fef --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h @@ -0,0 +1,53 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various GFX service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXLIBKB_H_ +#define _GFXLIBKB_H_ + +UINT32 +GfxLibGetSystemPllCofKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c new file mode 100644 index 0000000000..b6cfe666a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c @@ -0,0 +1,161 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFX mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88282 $ @e \$Date: 2013-02-19 11:20:56 -0600 (Tue, 19 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbGfxFamServices.h" +#include "GfxGmcInitKB.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "cpuFamilyTranslation.h" +#include "GfxSamuInitKB.h" +#include "GnbHandleLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Mid Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + UINT8 AudioEPCount; + UINT32 GMMx5F50; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_FATAL) { + GfxFmDisableController (StdHeader); + } else { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnableGmmAccessV3 (Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_SUCCESS) { + // Can not initialize GMM registers going to disable GFX controller + IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); + Gfx->UmaInfo.UmaMode = UMA_NONE; + GfxFmDisableController (StdHeader); + } else { + Status = GfxGmcInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //Status = GfxSamuInit (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxInitSsid (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + AudioEPCount = 0; + Status = GfxIntAudioEPEnumV3 (Gfx, &AudioEPCount); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if (AudioEPCount > 2) { + AudioEPCount = 2; + } + + AudioEPCount = 7 - AudioEPCount; + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x12, 0x5F50, &GMMx5F50, 0, StdHeader); + GMMx5F50 &= ~7; GMMx5F50 |= AudioEPCount & 7; + GMMx5F50 |= 1 << 4; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x12, 0x5F50, &GMMx5F50, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c new file mode 100644 index 0000000000..fa70f375fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c @@ -0,0 +1,153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbF1Table.h" +#include "GnbGfxInitLibV1.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbHandleLib.h" +#include "GfxLibV3.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + UINT32 D0F0xBC_xC00C0000; + GnbRegistersKB7269_STRUCT var5; + GnbRegistersKB7314_STRUCT var6; + GNB_HANDLE *GnbHandle; + + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbRegisterReadKB (GnbHandle, 0x4, + 0xc00c0000, &D0F0xBC_xC00C0000, 0, StdHeader); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + if (((D0F0xBC_xC00C0000 >> 1) & 1) != 1) { + if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { + LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader); + GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader); + if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || + (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) || + ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE) && + ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n"); + } + } + + if (PostParamsPtr->MemConfig.UmaMode == UMA_NONE) { + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &var5.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &var6.Value, 0, StdHeader); + var5.Field.bit16 = FALSE; + var6.Field.bit13 = FALSE; + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &var5.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &var6.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + + // Power down iGPU + GfxRequestGPUPowerV3 (Gfx, 0); + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceKB Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c new file mode 100644 index 0000000000..66cf992243 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c @@ -0,0 +1,253 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86584 $ @e \$Date: 2013-01-23 12:34:28 -0600 (Wed, 23 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccKB.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersKB.h" +#include "GfxLibKB.h" +#include "GfxSamuInitKB.h" +#include "GnbSamuPatchKB.h" +#include "OptionGnb.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXSAMUINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LENGTH_1MBYTE 0x0100000ul +#define MASK_1MBYTE 0x0FFFFFul + +#define SAM_IND_INDEX 0x22000ul +#define SAM_IND_DATA 0x22004ul + +#define SAM_SAB_IND_INDEX 0x22008ul +#define SAM_SAB_IND_DATA 0x2200Cul + +#define SMU_TOOLS_INDEX 0x238ul +#define SMU_TOOLS_DATA 0x23Cul + +typedef struct { + UINT32 BootControl; ///< + UINT32 KeySelect; ///< + UINT32 KernelAddrLo; ///< + UINT32 KernelAddrHi; ///< + UINT32 TweakSelect; ///< +} SAMU_BOOT_CONTROL; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxSamuInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 D0F0xBC_xC00C0000; + GNB_HANDLE *GnbHandle; + VOID *ControlXBuffer; + VOID *AlignedControlXBuffer; + VOID *PatchYBuffer; + VOID *AlignedPatchYBuffer; + SAMU_BOOT_CONTROL *SamuBootControl; + + UINT32 D0F0xBC_x800000A4; + UINT32 GMMx22000; + UINT32 GMMx22004; + UINT32 GMMx22008; + UINT32 GMMx2200C; + UINT32 LoopCount; + BOOLEAN SamuUseF1dPatch; + BOOLEAN SamuPatchEnabled; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000, + &D0F0xBC_xC00C0000, 0, GnbLibGetHeader (Gfx)); + + SamuPatchEnabled = GnbBuildOptions.CfgSamuPatchEnabled; + IDS_OPTION_HOOK (IDS_GNB_LOAD_SAMU_PATCH, &SamuPatchEnabled, GnbLibGetHeader (Gfx)); + + if ((((D0F0xBC_xC00C0000) & BIT24) == 0) && + (SamuPatchEnabled == TRUE)) { + + // Decide which version of the patch to use + SamuUseF1dPatch = TRUE; + + GMMx22008 = 0x29; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, + &GMMx22008, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x2200C, + &GMMx2200C, 0, GnbLibGetHeader (Gfx)); + IDS_HDT_CONSOLE (GNB_TRACE, " SAMSAB:29=%08x\n", GMMx2200C); + + if (GMMx2200C == 0x80000001) { + SamuUseF1dPatch = FALSE; + } + + ControlXBuffer = GnbAllocateHeapBufferAndClear (AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + ASSERT (ControlXBuffer != NULL); + if (ControlXBuffer == NULL) { + return AGESA_ERROR; + } + AlignedControlXBuffer = (VOID *) (((UINTN)ControlXBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE)); + PatchYBuffer = GnbAllocateHeapBuffer (AMD_GNB_SAMU_PATCH_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + ASSERT (PatchYBuffer != NULL); + if (PatchYBuffer == NULL) { + return AGESA_ERROR; + } + AlignedPatchYBuffer = (VOID *) (((UINTN)PatchYBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE)); + + // Copy samu firmware patch to PatchYBuffer + if (SamuUseF1dPatch == TRUE) { + LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKB[0], + SamuPatchKBHeader[1], GnbLibGetHeader (Gfx)); + } else { + LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKBUnf1[0], + SamuPatchKBHeaderUnf1[1], GnbLibGetHeader (Gfx)); + } + + // WBINVD + LibAmdWriteBackInvalidateCache (); + + // Load boot control structure + SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer; + SamuBootControl->BootControl = 0x3; + SamuBootControl->KernelAddrLo = (UINT32) (AlignedPatchYBuffer); + SamuBootControl->KernelAddrHi = 0; //(UINT32) ((((UINT64) AlignedPatchYBuffer) >> 32) & 0xFF); + if (SamuUseF1dPatch == TRUE) { + SamuBootControl->TweakSelect = 0xBB027E1F; + SamuBootControl->KeySelect = 0x8E174F83; + } else { + SamuBootControl->TweakSelect = 0x0; + SamuBootControl->KeySelect = 0x0; + } + + + // Write 0x0 to SAM_CGC_HOST_CTRL to release the clock-gating of SAMU + GMMx22000 = 0x3; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x0; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8) + GMMx22008 = 0x4; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx)); + GMMx2200C = ((UINT32) ((UINT32) AlignedControlXBuffer)) >> 8; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx)); + + // Write 0x0 to SAM_RST_HOST_SOFT_RESET + GMMx22000 = 0x1; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x0; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Write 0x2 to SAM_SCRATCH_0 to start the firmware boot + GMMx22000 = 0x38; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x2; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Poll SAM_RST_HOST_SOFT_RST_RDY and wait for HOST_RDY + do { + // Write 0x2 to SAM_SCRATCH_0 to start the firmware boot + GMMx22000 = 0x51; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + } while ((GMMx22004 & BIT0) == 0); + + // Clear the allocated memory ranges, locations X and Y (write 0), issue WBINVD + LibAmdMemFill (ControlXBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + LibAmdMemFill (PatchYBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + LibAmdWriteBackInvalidateCache (); + + // Confirm read of SMC_DRAM_ACCESS_CNTL is 0x1 + D0F0xBC_x800000A4 = 0; + for (LoopCount = 0; LoopCount < 0x00FFFFFF; LoopCount++) { + GnbRegisterReadKB (GnbHandle, 0x4, 0x800000A4, &D0F0xBC_x800000A4, 0, GnbLibGetHeader (Gfx)); + if ((D0F0xBC_x800000A4 & BIT0) != 0) { + break; + } + } + ASSERT ((D0F0xBC_x800000A4 & BIT0) != 0); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h new file mode 100644 index 0000000000..44dd8935e0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h @@ -0,0 +1,53 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBSAMUINITKB_H_ +#define _GNBSAMUINITKB_H_ + +AGESA_STATUS +GfxSamuInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c new file mode 100644 index 0000000000..99e7f933a9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c @@ -0,0 +1,479 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFx tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87698 $ @e \$Date: 2013-02-07 12:40:51 -0600 (Thu, 07 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" +#include "cpuFamilyTranslation.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GfxGmcFeature1DisableKB [] = { + //2.1 Disable clock-gating + GNB_ENTRY_WR (0x12, 0x20C0, 0x00000C80), + GNB_ENTRY_WR (0x12, 0x2478, 0x00000400), + GNB_ENTRY_WR (0x12, 0x20B8, 0x00000400), + GNB_ENTRY_WR (0x12, 0x20BC, 0x00000400), + GNB_ENTRY_WR (0x12, 0x2648, 0x00000400), + GNB_ENTRY_WR (0x12, 0x264C, 0x00000400), + GNB_ENTRY_WR (0x12, 0x2650, 0x00000400), + GNB_ENTRY_WR (0x12, 0x15C0, 0x00000400), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcInitTableKB [] = { + GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET), + //2.2 System memory address translation + GNB_ENTRY_COPY (0x12, 0x2814, 0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x281C, 0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x2824, 0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x282C, 0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x2834, 0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x283C, 0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS, 0, 32), + // MC_FUS_DRAM0_BANK_ADDR_MAPPING + GNB_ENTRY_COPY (0x12, 0x2844, 0, 8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS, 0, 8), + GNB_ENTRY_COPY (0x12, 0x2844, 8, 1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22, 1), + GNB_ENTRY_COPY (0x12, 0x2844, 9, 1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20, 1), + // MC_FUS_DRAM0_CTL_BASE + GNB_ENTRY_COPY (0x12, 0x284C, 0, 3, D18F1x200_TYPE, D18F1x200_ADDRESS, 4, 3), + GNB_ENTRY_COPY (0x12, 0x284C, 3, 4, D18F1x204_TYPE, D18F1x204_ADDRESS, 0, 4), + GNB_ENTRY_COPY (0x12, 0x284C, 7, 21, D18F1x200_TYPE, D18F1x200_ADDRESS, 11, 21), + GNB_ENTRY_COPY (0x12, 0x284C, 28, 1, D18F1x200_TYPE, D18F1x200_ADDRESS, 3, 1), + GNB_ENTRY_COPY (0x12, 0x284C, 29, 1, D18F1x200_TYPE, D18F1x200_ADDRESS, 0, 1), + // MC_FUS_DRAM0_CTL_LIMIT + GNB_ENTRY_COPY (0x12, 0x2854, 0, 21, D18F1x204_TYPE, D18F1x204_ADDRESS, 11, 21), + GNB_ENTRY_COPY (0x12, 0x2854, 21, 1, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 1, 1), + // MC_FUS_DRAM_MODE + GNB_ENTRY_COPY (0x12, 0x2864, 3, 1, D18F2x78_dct0_TYPE, D18F2x78_dct0_ADDRESS, 8, 1), + GNB_ENTRY_COPY (0x12, 0x2864, 4, 9, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 7, 9), + GNB_ENTRY_COPY (0x12, 0x2864, 0, 2, D18F2x110_TYPE, D18F2x110_ADDRESS, 6, 2), + GNB_ENTRY_COPY (0x12, 0x2864, 2, 1, D18F2x114_TYPE, D18F2x114_ADDRESS, 9, 1), + // MC_FUS_DRAM_CTL_HIGH_01 + GNB_ENTRY_COPY (0x12, 0x285C, 0, 12, D18F1x240_TYPE, D18F1x240_ADDRESS, 11, 12), + + // 2.4 Sequencer model programming + GNB_ENTRY_WR (0x12, 0x276C, 0x000003ff), + + //--------------------------------------------------------------------------- + // 2.5 Power gating init + // Initializing PGFSMs + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0x200010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0x300010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x210000), + GNB_ENTRY_WR (0x12, 0x3538, 0xa00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x21003), + GNB_ENTRY_WR (0x12, 0x3538, 0xb00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x2b00), + GNB_ENTRY_WR (0x12, 0x3538, 0xc00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0xd00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x420000), + GNB_ENTRY_WR (0x12, 0x3538, 0x100010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x120202), + GNB_ENTRY_WR (0x12, 0x3538, 0x500010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x3e3e36), + GNB_ENTRY_WR (0x12, 0x3538, 0x600010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x373f3e), + GNB_ENTRY_WR (0x12, 0x3538, 0x700010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x3e1332), + GNB_ENTRY_WR (0x12, 0x3538, 0xe00010ff), +//--------------------------------------------------------------------------- +// Initializing register engine +// opcode=1, body_cnt=0, mask=0xf, const=0xf: MC_CONFIG (0x800) MC_CONFIG (0x800) + GNB_ENTRY_WR (0x12, 0x3500, 0x0), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000800), + GNB_ENTRY_WR (0x12, 0x3504, 0xf), + GNB_ENTRY_WR (0x12, 0x3504, 0xf), +// opcode=1, body_cnt=0, mask=0x3f, const=0x3f: MC_CONFIG_MCD (0x828) MC_CONFIG_MCD (0x828) + GNB_ENTRY_WR (0x12, 0x3500, 0x4), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000828), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), +// opcode=1, body_cnt=0, mask=0xffff, const=0xffff: VM_INVALIDATE_REQUEST (0x51e) VM_INVALIDATE_REQUEST (0x51e) + GNB_ENTRY_WR (0x12, 0x3500, 0x8), + GNB_ENTRY_WR (0x12, 0x3504, 0x1000051e), + GNB_ENTRY_WR (0x12, 0x3504, 0xffff), + GNB_ENTRY_WR (0x12, 0x3504, 0xffff), +// opcode=0, body_cnt=2: VM_L2_CNTL (0x500) VM_L2_CNTL3 (0x502) + GNB_ENTRY_WR (0x12, 0x3500, 0xc), + GNB_ENTRY_WR (0x12, 0x3504, 0x20500), +// opcode=0, body_cnt=4: VM_CONTEXT0_CNTL (0x504) VM_SECURE_FAULT_CNTL (0x508) + GNB_ENTRY_WR (0x12, 0x3500, 0x10), + GNB_ENTRY_WR (0x12, 0x3504, 0x40504), +// opcode=0, body_cnt=9: VM_CONTEXT0_CNTL2 (0x50c) VM_CONTEXT15_PAGE_TABLE_BASE_ADDR (0x515) + GNB_ENTRY_WR (0x12, 0x3500, 0x16), + GNB_ENTRY_WR (0x12, 0x3504, 0x9050c), +// opcode=0, body_cnt=9: VM_PRT_APERTURE0_LOW_ADDR (0x52c) VM_CONTEXTS_DISABLE (0x535) + GNB_ENTRY_WR (0x12, 0x3500, 0x21), + GNB_ENTRY_WR (0x12, 0x3504, 0x9052c), +// opcode=0, body_cnt=1: VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR (0x546) VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR (0x547) + GNB_ENTRY_WR (0x12, 0x3500, 0x2c), + GNB_ENTRY_WR (0x12, 0x3504, 0x10546), +// opcode=0, body_cnt=10: VM_FAULT_CLIENT_ID (0x54e) VM_CONTEXT1_PAGE_TABLE_START_ADDR (0x558) + GNB_ENTRY_WR (0x12, 0x3500, 0x2f), + GNB_ENTRY_WR (0x12, 0x3504, 0xa054e), +// opcode=0, body_cnt=1: VM_CONTEXT0_PAGE_TABLE_END_ADDR (0x55f) VM_CONTEXT1_PAGE_TABLE_END_ADDR (0x560) + GNB_ENTRY_WR (0x12, 0x3500, 0x3b), + GNB_ENTRY_WR (0x12, 0x3504, 0x1055f), +// opcode=0, body_cnt=1: VM_DEBUG (0x56f) VM_L2_CG (0x570) + GNB_ENTRY_WR (0x12, 0x3500, 0x3e), + GNB_ENTRY_WR (0x12, 0x3504, 0x1056f), +// opcode=0, body_cnt=1: VM_L2_BANK_SELECT_MASKA (0x572) VM_L2_BANK_SELECT_MASKB (0x573) + GNB_ENTRY_WR (0x12, 0x3500, 0x41), + GNB_ENTRY_WR (0x12, 0x3504, 0x10572), +// opcode=0, body_cnt=2: VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR (0x575) VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET (0x577) + GNB_ENTRY_WR (0x12, 0x3500, 0x44), + GNB_ENTRY_WR (0x12, 0x3504, 0x20575), +// opcode=0, body_cnt=53: MC_CITF_PERFCOUNTER_LO (0x7a0) ATC_PERFCOUNTER_RSLT_CNTL (0x7d5) + GNB_ENTRY_WR (0x12, 0x3500, 0x48), + GNB_ENTRY_WR (0x12, 0x3504, 0x3507a0), +// opcode=0, body_cnt=0: MC_ARB_PERF_MON_CNTL0_ECC (0x7db) MC_ARB_PERF_MON_CNTL0_ECC (0x7db) + GNB_ENTRY_WR (0x12, 0x3500, 0x7f), + GNB_ENTRY_WR (0x12, 0x3504, 0x7db), +// opcode=0, body_cnt=26: MC_SHARED_CHMAP (0x801) MC_VM_STEERING (0x81b) + GNB_ENTRY_WR (0x12, 0x3500, 0x81), + GNB_ENTRY_WR (0x12, 0x3504, 0x1a0801), +// opcode=0, body_cnt=2: MC_CG_CONFIG_MCD (0x829) MC_SHARED_BLACKOUT_CNTL (0x82b) + GNB_ENTRY_WR (0x12, 0x3500, 0x9d), + GNB_ENTRY_WR (0x12, 0x3504, 0x20829), +// opcode=0, body_cnt=4: MC_HUB_MISC_POWER (0x82d) MC_HUB_MISC_DBG (0x831) + GNB_ENTRY_WR (0x12, 0x3500, 0xa1), + GNB_ENTRY_WR (0x12, 0x3504, 0x4082d), +// opcode=0, body_cnt=4: MC_HUB_MISC_OVERRIDE (0x833) MC_HUB_WDP_BP (0x837) + GNB_ENTRY_WR (0x12, 0x3500, 0xa7), + GNB_ENTRY_WR (0x12, 0x3504, 0x40833), +// opcode=0, body_cnt=11: MC_HUB_RDREQ_CNTL (0x83b) MC_HUB_SHARED_DAGB_DLY (0x846) + GNB_ENTRY_WR (0x12, 0x3500, 0xad), + GNB_ENTRY_WR (0x12, 0x3504, 0xb083b), +// opcode=0, body_cnt=1: MC_HUB_RDREQ_DMIF_LIMIT (0x848) MC_HUB_RDREQ_ACPG_LIMIT (0x849) + GNB_ENTRY_WR (0x12, 0x3500, 0xba), + GNB_ENTRY_WR (0x12, 0x3504, 0x10848), +// opcode=0, body_cnt=63: MC_HUB_WDP_SH2 (0x84d) MC_HUB_WDP_SAM (0x88c) + GNB_ENTRY_WR (0x12, 0x3500, 0xbd), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f084d), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB0_DEBUG (0x891) MC_VM_MB_L1_TLB0_DEBUG (0x891) + GNB_ENTRY_WR (0x12, 0x3500, 0xfe), + GNB_ENTRY_WR (0x12, 0x3504, 0x891), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB2_DEBUG (0x893) MC_VM_MB_L1_TLB2_DEBUG (0x893) + GNB_ENTRY_WR (0x12, 0x3500, 0x100), + GNB_ENTRY_WR (0x12, 0x3504, 0x893), +// opcode=0, body_cnt=0: MC_VM_MB_L2ARBITER_L2_CREDITS (0x8a1) MC_VM_MB_L2ARBITER_L2_CREDITS (0x8a1) + GNB_ENTRY_WR (0x12, 0x3500, 0x102), + GNB_ENTRY_WR (0x12, 0x3504, 0x8a1), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB3_DEBUG (0x8a5) MC_VM_MB_L1_TLB3_DEBUG (0x8a5) + GNB_ENTRY_WR (0x12, 0x3500, 0x104), + GNB_ENTRY_WR (0x12, 0x3504, 0x8a5), +// opcode=0, body_cnt=51: MC_XPB_RTR_SRC_APRTR0 (0x8cd) MC_XPB_UNC_THRESH_SID (0x900) + GNB_ENTRY_WR (0x12, 0x3500, 0x106), + GNB_ENTRY_WR (0x12, 0x3504, 0x3308cd), +// opcode=0, body_cnt=1: MC_XPB_WCB_CFG (0x902) MC_XPB_P2P_BAR_CFG (0x903) + GNB_ENTRY_WR (0x12, 0x3500, 0x13b), + GNB_ENTRY_WR (0x12, 0x3504, 0x10902), +// opcode=0, body_cnt=19: MC_XPB_P2P_BAR_SETUP (0x90c) MC_XPB_INTF_CFG (0x91f) + GNB_ENTRY_WR (0x12, 0x3500, 0x13e), + GNB_ENTRY_WR (0x12, 0x3504, 0x13090c), +// opcode=0, body_cnt=0: MC_XPB_SUB_CTRL (0x922) MC_XPB_SUB_CTRL (0x922) + GNB_ENTRY_WR (0x12, 0x3500, 0x153), + GNB_ENTRY_WR (0x12, 0x3504, 0x922), +// opcode=0, body_cnt=0: MC_XPB_PERF_KNOBS (0x924) MC_XPB_PERF_KNOBS (0x924) + GNB_ENTRY_WR (0x12, 0x3500, 0x155), + GNB_ENTRY_WR (0x12, 0x3504, 0x924), +// opcode=0, body_cnt=20: MC_XPB_STICKY_W1C (0x926) MC_XPB_CLG_CFG36 (0x93a) + GNB_ENTRY_WR (0x12, 0x3500, 0x157), + GNB_ENTRY_WR (0x12, 0x3504, 0x140926), +// opcode=2, body_cnt=0: MC_RPB_CID_QUEUE_EX (0x95a) + GNB_ENTRY_WR (0x12, 0x3500, 0x16d), + GNB_ENTRY_WR (0x12, 0x3504, 0x2000095a), + GNB_ENTRY_WR (0x12, 0x3504, 0x1), +// opcode=3, body_cnt=31: MC_RPB_CID_QUEUE_EX_DATA (0x95b) + GNB_ENTRY_WR (0x12, 0x3500, 0x16f), + GNB_ENTRY_WR (0x12, 0x3504, 0x301f095b), +// opcode=0, body_cnt=12: MC_RPB_CONF (0x94d) MC_RPB_PERF_COUNTER_STATUS (0x959) + GNB_ENTRY_WR (0x12, 0x3500, 0x190), + GNB_ENTRY_WR (0x12, 0x3504, 0xc094d), +// opcode=0, body_cnt=16: MC_CITF_XTRA_ENABLE (0x96d) MC_CITF_INT_CREDITS_WR (0x97d) + GNB_ENTRY_WR (0x12, 0x3500, 0x19e), + GNB_ENTRY_WR (0x12, 0x3504, 0x10096d), +// opcode=0, body_cnt=12: MC_CITF_WTM_RD_CNTL (0x97f) MC_WR_GRP_LCL (0x98b) + GNB_ENTRY_WR (0x12, 0x3500, 0x1b0), + GNB_ENTRY_WR (0x12, 0x3504, 0xc097f), +// opcode=0, body_cnt=0: MC_CITF_PERF_MON_CNTL2 (0x98e) MC_CITF_PERF_MON_CNTL2 (0x98e) + GNB_ENTRY_WR (0x12, 0x3500, 0x1be), + GNB_ENTRY_WR (0x12, 0x3504, 0x98e), +// opcode=0, body_cnt=2: MC_CITF_MISC_RD_CG (0x992) MC_CITF_MISC_VM_CG (0x994) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c0), + GNB_ENTRY_WR (0x12, 0x3504, 0x20992), +// opcode=0, body_cnt=2: MC_VM_MD_L1_TLB0_DEBUG (0x998) MC_VM_MD_L1_TLB2_DEBUG (0x99a) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c4), + GNB_ENTRY_WR (0x12, 0x3504, 0x20998), +// opcode=0, body_cnt=0: MC_VM_MD_L2ARBITER_L2_CREDITS (0x9a4) MC_VM_MD_L2ARBITER_L2_CREDITS (0x9a4) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c8), + GNB_ENTRY_WR (0x12, 0x3504, 0x9a4), +// opcode=0, body_cnt=0: MC_VM_MD_L1_TLB3_DEBUG (0x9a7) MC_VM_MD_L1_TLB3_DEBUG (0x9a7) + GNB_ENTRY_WR (0x12, 0x3500, 0x1ca), + GNB_ENTRY_WR (0x12, 0x3504, 0x9a7), +// opcode=0, body_cnt=6: MC_ARB_AGE_CNTL (0x9bf) MC_ARB_GECC2_DEBUG2 (0x9c5) + GNB_ENTRY_WR (0x12, 0x3500, 0x1cc), + GNB_ENTRY_WR (0x12, 0x3504, 0x609bf), +// opcode=0, body_cnt=45: MC_ARB_GECC2 (0x9c9) MC_ARB_MAX_LAT_CID (0x9f6) + GNB_ENTRY_WR (0x12, 0x3500, 0x1d4), + GNB_ENTRY_WR (0x12, 0x3504, 0x2d09c9), +// opcode=0, body_cnt=3: MC_ARB_SSM (0x9f9) MC_ARB_DRAM_TIMING_1 (0x9fc) + GNB_ENTRY_WR (0x12, 0x3500, 0x203), + GNB_ENTRY_WR (0x12, 0x3504, 0x309f9), +// opcode=0, body_cnt=0: MC_ARB_DRAM_TIMING2_1 (0x9ff) MC_ARB_DRAM_TIMING2_1 (0x9ff) + GNB_ENTRY_WR (0x12, 0x3500, 0x208), + GNB_ENTRY_WR (0x12, 0x3504, 0x9ff), +// opcode=0, body_cnt=2: MC_ARB_BURST_TIME (0xa02) MC_ARB_SCRAMBLE_KEY1 (0xa04) + GNB_ENTRY_WR (0x12, 0x3500, 0x20a), + GNB_ENTRY_WR (0x12, 0x3504, 0x20a02), +// opcode=0, body_cnt=6: MC_FUS_DRAM0_CTL_BASE (0xa13) MC_FUS_DRAM_MODE (0xa19) + GNB_ENTRY_WR (0x12, 0x3500, 0x20e), + GNB_ENTRY_WR (0x12, 0x3504, 0x60a13), +// opcode=0, body_cnt=3: MC_FUS_ARB_GARLIC_ISOC_PRI (0xa1f) MC_FUS_ARB_GARLIC_WR_PRI2 (0xa22) + GNB_ENTRY_WR (0x12, 0x3500, 0x216), + GNB_ENTRY_WR (0x12, 0x3504, 0x30a1f), +// opcode=1, body_cnt=0, mask=0x3f, const=0x0: ATC_ATS_FAULT_CNTL (0xccd) ATC_ATS_FAULT_CNTL (0xccd) + GNB_ENTRY_WR (0x12, 0x3500, 0x21b), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000ccd), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), + GNB_ENTRY_WR (0x12, 0x3504, 0x0), +// opcode=0, body_cnt=7: ATC_VM_APERTURE0_LOW_ADDR (0xcc0) ATC_VM_APERTURE1_CNTL2 (0xcc7) + GNB_ENTRY_WR (0x12, 0x3500, 0x21f), + GNB_ENTRY_WR (0x12, 0x3504, 0x70cc0), +// opcode=0, body_cnt=2: ATC_ATS_CNTL (0xcc9) ATC_ATS_FAULT_DEBUG (0xccb) + GNB_ENTRY_WR (0x12, 0x3500, 0x228), + GNB_ENTRY_WR (0x12, 0x3504, 0x20cc9), +// opcode=0, body_cnt=1: ATC_ATS_DEFAULT_PAGE_LOW (0xcd0) ATC_ATS_DEFAULT_PAGE_CNTL (0xcd1) + GNB_ENTRY_WR (0x12, 0x3500, 0x22c), + GNB_ENTRY_WR (0x12, 0x3504, 0x10cd0), +// opcode=0, body_cnt=4: ATC_MISC_CG (0xcd4) ATC_L2_DEBUG2 (0xcd8) + GNB_ENTRY_WR (0x12, 0x3500, 0x22f), + GNB_ENTRY_WR (0x12, 0x3504, 0x40cd4), +// opcode=0, body_cnt=5: ATC_L1_CNTL (0xcdc) ATC_L1WR_STATUS (0xce1) + GNB_ENTRY_WR (0x12, 0x3500, 0x235), + GNB_ENTRY_WR (0x12, 0x3504, 0x50cdc), +// opcode=0, body_cnt=16: ATC_VMID_PASID_MAPPING_UPDATE_STATUS (0xce6) ATC_VMID15_PASID_MAPPING (0xcf6) + GNB_ENTRY_WR (0x12, 0x3500, 0x23c), + GNB_ENTRY_WR (0x12, 0x3504, 0x100ce6), +// opcode=0, body_cnt=0: ATC_ATS_FAULT_CNTL (0xccd) ATC_ATS_FAULT_CNTL (0xccd) + GNB_ENTRY_WR (0x12, 0x3500, 0x24e), + GNB_ENTRY_WR (0x12, 0x3504, 0xccd), +// opcode=0, body_cnt=23: MC_ARB_HARSH_EN_RD (0xdc0) MC_ARB_HARSH_CTL_WR (0xdd7) + GNB_ENTRY_WR (0x12, 0x3500, 0x250), + GNB_ENTRY_WR (0x12, 0x3504, 0x170dc0), +// opcode=0, body_cnt=0: MC_CONFIG (0x800) MC_CONFIG (0x800) + GNB_ENTRY_WR (0x12, 0x3500, 0x269), + GNB_ENTRY_WR (0x12, 0x3504, 0x800), +// opcode=0, body_cnt=0: MC_CONFIG_MCD (0x828) MC_CONFIG_MCD (0x828) + GNB_ENTRY_WR (0x12, 0x3500, 0x26b), + GNB_ENTRY_WR (0x12, 0x3504, 0x828), +//--------------------------------------------------------------------------- +// Setting up end pointers + GNB_ENTRY_RMW (0x12, 0x3508, 0xfffff000, 0x9b26c000), +//--------------------------------------------------------------------------- +// Enabling light sleep + GNB_ENTRY_RMW (0x12, 0x3544, 0x6000000, 0x2000000), + + // 2.7 Performance tuning + GNB_ENTRY_WR (0x12, 0x27D0, 0x10724847), + GNB_ENTRY_WR (0x12, 0x27C0, 0x00C32008), + GNB_ENTRY_WR (0x12, 0x27C4, 0x00C32006), + GNB_ENTRY_WR (0x12, 0x277C, 0x00000007), + GNB_ENTRY_WR (0x12, 0x218C, 0x000021b1), + GNB_ENTRY_WR (0x12, 0x201C, 0x47773337), + GNB_ENTRY_WR (0x12, 0x2020, 0x73773337), + GNB_ENTRY_WR (0x12, 0x2018, 0x66334303), + GNB_ENTRY_WR (0x12, 0x2014, 0x66300333), + GNB_ENTRY_WR (0x12, 0x2794, 0xfcfcfdfc), + GNB_ENTRY_WR (0x12, 0x2798, 0xfcfcfdfc), + GNB_ENTRY_WR (0x12, 0x27A4, 0x00ffffff), + GNB_ENTRY_WR (0x12, 0x27A8, 0x00ffffff), + GNB_ENTRY_WR (0x12, 0x278C, 0x00000008), + GNB_ENTRY_WR (0x12, 0x2790, 0x00000008), + GNB_ENTRY_WR (0x12, 0x2628, 0x55111000), + GNB_ENTRY_WR (0x12, 0x25E0, 0x00000025), + GNB_ENTRY_WR (0x12, 0x262C, 0x10555111), + GNB_ENTRY_WR (0x12, 0x25E4, 0x00000025), + GNB_ENTRY_WR (0x12, 0x25C8, 0x0080685F), + GNB_ENTRY_WR (0x12, 0x25CC, 0x0000807F), + GNB_ENTRY_WR (0x12, 0x2144, 0x50A1421D), + GNB_ENTRY_WR (0x12, 0x20EC, 0x0000001C), + GNB_ENTRY_WR (0x12, 0x2184, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x21E0, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x217C, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x21C0, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x2214, 0x000021B1), + GNB_ENTRY_WR (0x12, 0x2220, 0x000021B1), + GNB_ENTRY_WR (0x12, 0x3758, 0x00000800), + GNB_ENTRY_WR (0x12, 0x375C, 0x00000800), + GNB_ENTRY_WR (0x12, 0x3700, 0xD1000000), + GNB_ENTRY_WR (0x12, 0x3704, 0xD0000000), + GNB_ENTRY_WR (0x12, 0x3748, 0x0000007F), + GNB_ENTRY_WR (0x12, 0x3750, 0x18201015), + GNB_ENTRY_WR (0x12, 0x3754, 0x18201015), + GNB_ENTRY_WR (0x12, 0x253C, 0x000000B4), + GNB_ENTRY_WR (0x12, 0x2550, 0x000000A3), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002077), + GNB_ENTRY_WR (0x12, 0x2558, 0x000020B7), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002A3D), + + GNB_ENTRY_WR (0x12, 0x287C, 0x0c000911), + + //2.9 Display latency + GNB_ENTRY_WR (0x12, 0x2114, 0x00000015), + + GNB_ENTRY_WR (0x12, 0x2880, 0xFCFE8000), + + //2.12 Remove blackout + GNB_ENTRY_WR (0x12, 0x20AC, 0x00000000), + + // VCE Optimization + GNB_ENTRY_RMW (0x12, 0x2108, 0xff00, (1 << 8)), + GNB_ENTRY_WR (0x12, 0x21fc, 0xA1F1), + GNB_ENTRY_WR (0x12, 0x2198, 0xA1F1), + + // STCTRL_IGNORE_PROTECTION_FAULT + GNB_ENTRY_RMW (0x12, 0x350C, 0x01000000, (1 << 24)), + + GNB_ENTRY_RMW (0x12, 0x5490, 0x2 | 0x1, (1 << 0) | (1 << 1)), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcFeature1EnableKB [] = { + GNB_ENTRY_WR (0x12, 0x20C0, 0x000c0c80), + GNB_ENTRY_WR (0x12, 0x2478, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x20B8, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x20BC, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x2648, 0x00080400), + GNB_ENTRY_WR (0x12, 0x264C, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x2650, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x15C0, 0x000c0400), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxEnvInitTableKB [] = { + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c new file mode 100644 index 0000000000..288884b0cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c @@ -0,0 +1,459 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84838 $ @e \$Date: 2012-12-20 10:04:21 -0600 (Thu, 20 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbTable.h" +#include "GnbSmuInitLibV7.h" +#include "GnbSmuFirmwareKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "cpuF16PowerMgmt.h" +#include "excel925.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBEARLYINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB []; +extern GNB_TABLE ROMDATA GnbEarlyInitTableKB []; +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; + +#define CFG_DISP_PHY_TDP_LIMIT 0 +#define CFG_FCH_PWR_CREDIT 0 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEarlierInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbScsInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +OptionGnbInstall581 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +STATIC VOID +GnbEarlyInitKB129_fun ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParams; + UINT32 v0; + UINT32 v1; + D18F4x110_STRUCT D18F4x110; + D18F5xE0_STRUCT D18F5xE0; + UINT32 v4; + UINT32 Data; + + EarlyParams = (AMD_EARLY_PARAMS *) StdHeader; + + v0 = ((EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10) & 0xFFFF) | + (((EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10) & 0xFFFF) << 16); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3FA04, &v0, 0, StdHeader); + + v1 = ((EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10) & 0xFFFF) | + (((EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10) & 0xFFFF) << 16); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3f994, &v1, 0, StdHeader); + + GnbRegisterReadKB (GnbGetHandle (StdHeader), + D18F4x110_TYPE, D18F4x110_ADDRESS, &D18F4x110, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), + D18F5xE0_TYPE, D18F5xE0_ADDRESS, &D18F5xE0, 0, StdHeader); + + // Period = (2^(RunAvgRange + 1)*CSampleTimer*5.12)us - round down to nearest 10uS + Data = D18F5xE0.Field.RunAvgRange + 1; + Data = 1 << Data; + Data *= D18F4x110.Field.CSampleTimer; + Data = ((Data * 512) / 1000) * 10; + + IDS_HDT_CONSOLE (GNB_TRACE, "VPC period = %d\n", Data); + + v4 = Data; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), + 0x4, 0x3F830, &v4, 0, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +STATIC VOID +GnbEarlyInitKB180_fun ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F3xA8_STRUCT D18F3xA8; + UINT32 D0F0xBC_x3F9D8; + UINT64 MsrData; + + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3xA8_TYPE, D18F3xA8_ADDRESS, &D18F3xA8, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0x3F9D8, &D0F0xBC_x3F9D8, 0, StdHeader); + D0F0xBC_x3F9D8 &= ~(0xF << 24); + D0F0xBC_x3F9D8 |= (D18F3xA8.Field.PopDownPstate & 0x7) << 24; + LibAmdMsrRead ((PS_REG_BASE + D18F3xA8.Field.PopDownPstate), &MsrData, StdHeader); + D0F0xBC_x3F9D8 |= (((MsrData & (1 << 22)) == 0) ? (1 << 27) :0); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3F9D8, &D0F0xBC_x3F9D8, 0, StdHeader); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init Package Power Support + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbInitPkgPowerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 D0F0xBC_x3F834; + UINT32 D0F0xBC_x3F838; + UINT32 D0F0xBC_x3F844; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbInitPkgPowerKB Enter\n"); + + D0F0xBC_x3F834 = CFG_DISP_PHY_TDP_LIMIT; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), TYPE_D0F0xBC, 0x3F834, + &D0F0xBC_x3F834, 0, StdHeader); + + D0F0xBC_x3F838 = CFG_FCH_PWR_CREDIT; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), TYPE_D0F0xBC, 0x3F838, + &D0F0xBC_x3F838, 0, StdHeader); + + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0x3f844, + &D0F0xBC_x3F844, 0, StdHeader); + D0F0xBC_x3F844 &= 0xe0000000; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3f844, + &D0F0xBC_x3F844, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbInitPkgPowerKB Exit\n"); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request VDDB Pmin + * + * + * + * @param[in] GnbHandle GNB_HANDLE + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbRequestVddNbPminKB ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F5x170_STRUCT D18F5x170; + D18F5x160_STRUCT D18F5x160; + UINT32 Millivolt; + UINT32 NbVid; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminKB Enter\n"); + // 1) Read F5x170[NbPstateMaxVal] to find NB Pmin. + GnbRegisterReadKB (GnbHandle, D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170, 0, StdHeader); + // 2) Determine voltage associated with NB Pmin. Read F5x(160+4*NbPstateMaxVal)[NbVid]. (For example, NBP0 is F5x160, NBP1 is F5x164, etc) + GnbRegisterReadKB (GnbHandle, D18F5x160_TYPE, (D18F5x160_ADDRESS + (4 * D18F5x170.Field.NbPstateMaxVal)), &D18F5x160, 0, StdHeader); + NbVid = (D18F5x160.Field.NbVid_7_ << 7) | (D18F5x160.Field.NbVid_6_0_); + // 3) Make voltage request (via BIOSSMC_MSG_VDDNB_REQUEST) for voltage determined by Step 2. Note that message requires encoding in voltage, not VID. + // Use the following equation to decode SVI2 VIDs: + // Voltage = 1.55 - (0.00625*VID) + // Furthermore, VDDNB requests to SMU should be encoded in 0.25mV steps. + // Therefore, voltage should be translated into mV and then multiplied by 4, to be encoded as 0.25mV steps. + // Or... ( 1.55 * 1000 * 4) - (.00625 * 1000 * 4) * VID) = (1550 * 4) - (25 * VID) + Millivolt = (1550 * 4) - (25 * NbVid); + + IDS_HDT_CONSOLE (GNB_TRACE, " Set Voltage for NbPstateMaxVal = 0x%x, Vid code 0x%x = %d mV\n", D18F5x170.Field.NbPstateMaxVal, NbVid, Millivolt); + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbHandle; + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_VDDNB_REQUEST, + Millivolt, + 0 + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminKB Exit\n"); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GfxStrapsEarlyInitKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegistersKB7236_STRUCT v0; + GnbRegistersKB7269_STRUCT v1; + GnbRegistersKB7314_STRUCT v2; + GnbRegistersKB7341_STRUCT v3; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitKB Enter\n"); + + GnbHandle = GnbGetHandle (StdHeader); + + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AB, &v0.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &v1.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &v2.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x013014BE, &v3.Value, 0, StdHeader); + + v0.Field.bit17 = 1; + + v2.Field.bita = 0x0; + v2.Field.StrapBifF0LegacyDeviceTypeDis = 0x0; + + v1.Field.bit16 = UserOptions.CfgGnbHdAudio; + v2.Field.bit13 = UserOptions.CfgGnbHdAudio; + + // Enable PCI Vendor Specific Capabilities + v3.Field.bit_20 = 1; + + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AB, &v0.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &v1.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &v2.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x013014BE, &v3.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Gfx gBIF + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxGBifEnableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegistersKB7208_STRUCT var0; + GnbRegistersKB7514_STRUCT var1; + UINT32 D0F0xBC_xC00C0000; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000, &D0F0xBC_xC00C0000, 0, StdHeader); + if (((D0F0xBC_xC00C0000 >> 1) & 1 )!= 1) { + GfxStrapsEarlyInitKB (StdHeader); + } + + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x1301486, &var0.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x1091518, &var1.Value, 0, StdHeader); + var0.Field.bit2 = 0x1; + var1.Field.bit0 = 0x1; + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x1091518, &var1.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x1301486, &var0.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableKB Exit\n"); + + return AGESA_SUCCESS; +} +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at early post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + UINT32 Property; + + AgesaStatus = AGESA_SUCCESS; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + + Property = TABLE_PROPERTY_DEFAULT; + Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? 0x00000400ul : 0; + Property |= GnbBuildOptions.CfgSviRevision == 2 ? TABLE_PROPERTY_SVI2 : 0; + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + while (GnbHandle != NULL) { + GnbEarlyInitKB129_fun (StdHeader); + GnbEarlyInitKB180_fun (StdHeader); + GnbInitPkgPowerKB (StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlyInitTableKB, + Property, + 0, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbRequestVddNbPminKB (GnbHandle, StdHeader); + Status = GfxGBifEnableKB (StdHeader); + ASSERT (Status == AGESA_SUCCESS); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at earlier post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlierInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + + AgesaStatus = AGESA_SUCCESS; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableBeforeSmuKB, + 0, + 0, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GnbSmuFirmwareLoadV7 (GnbHandle, (FIRMWARE_HEADER_V7*) &FirmwareKB[0], StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceKB Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +OptionGnbInstall581 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + + AgesaStatus = AGESA_SUCCESS; + Status = AGESA_SUCCESS; + GnbHandle = GnbGetHandle (StdHeader); + + while (GnbHandle != NULL) { + Status = GnbSmuInitLibV7139_fun0 (GnbHandle, &excel925[0], StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c new file mode 100644 index 0000000000..e9f41de52e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c @@ -0,0 +1,302 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB env post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85506 $ @e \$Date: 2013-01-08 15:38:33 -0600 (Tue, 08 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbSmuInitLibV7.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV5.h" +#include "GnbF1TableKB.h" +#include "GnbF1Table.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbEnvInitTableKB []; +extern GNB_TABLE ROMDATA GnbIommuInitTableKB []; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * NB Dynamic Wake + * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller + * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbOrbDynamicWakeKB ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + D0F0x98_x2C_STRUCT D0F0x98_x2C; + + GnbLibPciIndirectRead ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x2C_ADDRESS, + AccessWidth32, + &D0F0x98_x2C.Value, + StdHeader + ); + + // Enable Dynamic wake + // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. + if (GnbBuildOptions.CfgOrbDynWakeEnable) { + D0F0x98_x2C.Field.DynWakeEn = 1; + } else { + D0F0x98_x2C.Field.DynWakeEn = 0; + } + D0F0x98_x2C.Field.WakeHysteresis = 0x19; + + IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &D0F0x98_x2C, StdHeader); + + GnbLibPciIndirectWrite ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x2C_ADDRESS, + AccessS3SaveWidth32, + &D0F0x98_x2C.Value, + StdHeader + ); +} +/*----------------------------------------------------------------------------------------*/ +/** + * HTC Data + * + * @param[in] GnbHandle Gnb Header + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbFillHtcData ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT32 D0F0xBC_x3FDD4; + D18F3x64_STRUCT D18F3x64; + UINT16 *p = (UINT16 *)&D0F0xBC_x3FDD4; + GnbRegisterReadKB (GnbHandle, D18F3x64_TYPE, D18F3x64_ADDRESS, + &D18F3x64.Value, 0, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, 0x3fdd4, + &D0F0xBC_x3FDD4, 0, StdHeader); + + if (D18F3x64.Field.HtcEn == 1) { + + p[1] = D18F3x64.Field.HtcTmpLmt / 2 + 52; + p[0] = + p[1] - (D18F3x64.Field.HtcHystLmt / 2); + + p[1] = + (p[1] + 49) << 3; + p[0] = + (p[0] + 49) << 3; + + } else { + + p[0] = 0; + p[1] = 0; + + } + + + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdd4, &D0F0xBC_x3FDD4, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * LHTC Data + * + * @param[in] GnbHandle Gnb Header + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbUpdateLhtcData ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_ENV_PARAMS *EnvParams; + UINT32 LhtcParameter; + D18F3x64_STRUCT D18F3x64; + UINT32 D0F0xBC_xC0104090; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbUpdateLhtcData Enter\n"); + EnvParams = (AMD_ENV_PARAMS *) StdHeader; + + // Make sure both config values are valid + if ((EnvParams->PlatformConfig.LhtcTemperatureLimit >= 520) && (EnvParams->PlatformConfig.HtcTemperatureLimit >= 520)) { + // Platform config value is in .1 degrees + LhtcParameter = (EnvParams->PlatformConfig.LhtcTemperatureLimit - 520) / 5; + // Read HtcTmpLmt field from D18F3 + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0104090, &D0F0xBC_xC0104090, 0, StdHeader); + if ((D18F3x64.Field.HtcEn == 1) && (LhtcParameter < D18F3x64.Field.HtcTmpLmt) && (LhtcParameter < ((D0F0xBC_xC0104090 >> 23) & 0xFF))) { + // All values are valid, so we can send the service to the SMU + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_LHTC_LIMIT_SetLimit, + LhtcParameter, + GNB_REG_ACC_FLAG_S3SAVE + ); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbUpdateLhtcData Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at env + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINT32 Property; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceKB Enter\n"); + Property = TABLE_PROPERTY_DEFAULT; + Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0; + Property |= GnbBuildOptions.CfgLhtcSupport ? TABLE_PROPERTY_LHTC : 0; + Property |= GnbBuildOptions.CfgTdcSupport ? 0x00040000ul : 0; + Property |= 0x00080000ul; + AgesaStatus = AGESA_SUCCESS; + GnbLoadF1TableKB (StdHeader); + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Status = GnbSetTomV5 (GnbPciAddress, StdHeader); + GnbOrbDynamicWakeKB (GnbPciAddress, StdHeader); + GnbFillHtcData (GnbHandle, StdHeader); + if (GnbIsGnbConnectedToSb (GnbHandle)) { + GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader); + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + Status = GnbProcessTable ( + GnbHandle, + GnbEnvInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if ((Property & TABLE_PROPERTY_LHTC) != 0) { + GnbUpdateLhtcData (GnbHandle, StdHeader); + } + + Status = GnbProcessTable ( + GnbHandle, + GnbIommuInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c new file mode 100644 index 0000000000..41b7b176f2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c @@ -0,0 +1,1022 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gnb f1 table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84159 $ @e \$Date: 2011-12-21 14:49:48 -0600 (Wed, 21 Dec 2011) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbF1Table.h" +#include "GnbF1TableKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbHandleLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +//#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBFUSETABLEKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +PP_F1_ARRAY_V2 DefaultPpF1ArrayKB = { + 0, + {0x40, 0, 0, 0, 0}, + {0x40, 0, 0, 0, 0}, + 8, + {0, 0, 0, 0, 0, 0}, + {0x40, 0x40, 0x40, 0, 0}, + {0, 0, 0, 0, 0}, + 3, + 0x10, + 0, + 0, + 0, + 0, + TRUE, + {0x3, 0xC, 0x30, 0xC0}, + 0, + {0, 0, 0, 0}, + {0x40, 0x40, 0x40, 0x40, 0}, + 0, + 0, + 0, + 0, + { 1, 1, 1, 1}, + { 0, 0, 0, 0}, + { 2, 2, 2, 2}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 1, 1, 1, 1}, + { 0x24, 0x24, 0x24, 0x24, 0x24 }, + { 0x17, 0x18, 0x20, 0x22, 0x24 }, + { 0x17, 0x18, 0x20, 0x22, 0x24 }, + { 0x1, 0x2, 0x3, 0x4, 0x5 }, + 0x1E, + 0x3 +}; + + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104007_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104008_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[1]) + }, + { + 13, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[2]) + }, + { + 21, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[3]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010400C_TABLE [] = { + { + 25, + 6, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld21) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010407C_TABLE [] = { + { + 20, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104080_TABLE [] = { + { + 21, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104083_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104084_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[2]) + }, + { + 13, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[3]) + }, + { + 29, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104088_TABLE [] = { + { + 0, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[1]) + }, + { + 3, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[2]) + }, + { + 6, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[3]) + }, + { + 12, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceMclk) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC01040A8_TABLE [] = { + { + 16, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[0]) + }, + { + 24, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC01040AC_TABLE [] = { + { + 0, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[2]) + }, + { + 8, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[3]) + }, + { + 16, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107044_TABLE [] = { + { + 16, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld36) + }, +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107064_TABLE [] = { + { + 0, + 4, + (UINT16) offsetof (PP_F1_ARRAY_V2, PPlayTableRev) + }, + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld3) + }, + { + 11, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PcieGen2Vid) + }, + { + 17, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[0]) + }, + { + 24, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107067_TABLE [] = { + { + 7, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[2]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107068_TABLE [] = { + { + 6, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[3]) + }, + { + 13, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[4]) + }, + { + 20, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706B_TABLE [] = { + { + 3, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706C_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[2]) + }, + { + 9, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[3]) + }, + { + 16, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[4]) + }, + { + 23, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706F_TABLE [] = { + { + 6, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107070_TABLE [] = { + { + 5, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[2]) + }, + { + 12, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[3]) + }, + { + 19, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107073_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107074_TABLE [] = { + { + 1, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[1]) + }, + { + 8, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[2]) + }, + { + 15, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[3]) + }, + { + 22, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107077_TABLE [] = { + { + 5, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107078_TABLE [] = { + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[1]) + }, + { + 11, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[2]) + }, + { + 18, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[3]) + }, + { + 25, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010707C_TABLE [] = { + { + 0, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[0]) + }, + { + 7, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[1]) + }, + { + 14, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[2]) + }, + { + 21, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[3]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010707F_TABLE [] = { + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107080_TABLE [] = { + { + 3, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld37) + }, + { + 8, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld38) + }, + { + 13, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[0]) + }, + { + 20, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107083_TABLE [] = { + { + 3, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[2]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107084_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[3]) + }, + { + 9, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[4]) + } +}; + +F1_REGISTER_ENTRY_KB D18F3x64_TABLE [] = { + { + D18F3x64_HtcEn_OFFSET, + D18F3x64_HtcEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, HtcEn) + }, + { + D18F3x64_HtcTmpLmt_OFFSET, + D18F3x64_HtcTmpLmt_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, HtcTmpLmt) + }, + { + D18F3x64_HtcHystLmt_OFFSET, + D18F3x64_HtcHystLmt_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld20) + } +}; + +F1_REGISTER_ENTRY_KB GnbFuseTableKB565_TABLE [] = { + { + 1, + 6, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld21) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x90_dct0_TABLE [] = { + { + D18F2x90_dct0_DisDllShutdownSR_OFFSET, + D18F2x90_dct0_DisDllShutdownSR_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, DisDllShutdownSR[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x94_dct0_TABLE [] = { + { + D18F2x94_dct0_MemClkFreq_OFFSET, + D18F2x94_dct0_MemClkFreq_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, MemClkFreq[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2xA8_dct0_TABLE [] = { + { + D18F2xA8_dct0_MemPhyPllPdMode_OFFSET, + D18F2xA8_dct0_MemPhyPllPdMode_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, MemPhyPllPdMode[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x2E0_dct0_TABLE [] = { + { + D18F2x2E0_dct0_M1MemClkFreq_OFFSET, + D18F2x2E0_dct0_M1MemClkFreq_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, M1MemClkFreq[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x160_TABLE [] = { + { + D18F5x160_NbPstateEn_OFFSET, + D18F5x160_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[0]) + }, + { + D18F5x160_MemPstate_OFFSET, + D18F5x160_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[0]) + }, + { + D18F5x160_NbFid_OFFSET, + D18F5x160_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[0]) + }, + { + D18F5x160_NbDid_OFFSET, + D18F5x160_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[0]) + }, + { + D18F5x160_NbVid_6_0_OFFSET, + D18F5x160_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[0]) + }, + { + D18F5x160_NbVid_7_OFFSET, + D18F5x160_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x164_TABLE [] = { + { + D18F5x164_NbPstateEn_OFFSET, + D18F5x164_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[1]) + }, + { + D18F5x164_MemPstate_OFFSET, + D18F5x164_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[1]) + }, + { + D18F5x164_NbFid_OFFSET, + D18F5x164_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[1]) + }, + { + D18F5x164_NbDid_OFFSET, + D18F5x164_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[1]) + }, + { + D18F5x164_NbVid_6_0_OFFSET, + D18F5x164_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[1]) + }, + { + D18F5x164_NbVid_7_OFFSET, + D18F5x164_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[1]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x168_TABLE [] = { + { + D18F5x168_NbPstateEn_OFFSET, + D18F5x168_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[2]) + }, + { + D18F5x168_MemPstate_OFFSET, + D18F5x168_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[2]) + }, + { + D18F5x168_NbFid_OFFSET, + D18F5x168_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[2]) + }, + { + D18F5x168_NbDid_OFFSET, + D18F5x168_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[2]) + }, + { + D18F5x168_NbVid_6_0_OFFSET, + D18F5x168_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[2]) + }, + { + D18F5x168_NbVid_7_OFFSET, + D18F5x168_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[2]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x16C_TABLE [] = { + { + D18F5x16C_NbPstateEn_OFFSET, + D18F5x16C_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[3]) + }, + { + D18F5x16C_MemPstate_OFFSET, + D18F5x16C_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[3]) + }, + { + D18F5x16C_NbFid_OFFSET, + D18F5x16C_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[3]) + }, + { + D18F5x16C_NbDid_OFFSET, + D18F5x16C_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[3]) + }, + { + D18F5x16C_NbVid_6_0_OFFSET, + D18F5x16C_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[3]) + }, + { + D18F5x16C_NbVid_7_OFFSET, + D18F5x16C_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[3]) + } +}; + + +F1_TABLE_ENTRY_KB F1RegisterTableKB [] = { + + { + 0x4, + 0xC0104007, + sizeof (D0F0xBC_xC0104007_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104007_TABLE + }, + { + 0x4, + 0xC0104008, + sizeof (D0F0xBC_xC0104008_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104008_TABLE + }, + { + 0x4, + 0xC010400c, + sizeof (D0F0xBC_xC010400C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010400C_TABLE + }, + { + 0x4, + 0xC010407c, + sizeof (D0F0xBC_xC010407C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010407C_TABLE + }, + { + 0x4, + 0xC0104080, + sizeof (D0F0xBC_xC0104080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104080_TABLE + }, + { + 0x4, + 0xC0104083, + sizeof (D0F0xBC_xC0104083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104083_TABLE + }, + { + 0x4, + 0xC0104084, + sizeof (D0F0xBC_xC0104084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104084_TABLE + }, + { + 0x4, + 0xC0104088, + sizeof (D0F0xBC_xC0104088_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104088_TABLE + }, + { + 0x4, + 0xC01040a8, + sizeof (D0F0xBC_xC01040A8_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC01040A8_TABLE + }, + { + 0x4, + 0xC01040ac, + sizeof (D0F0xBC_xC01040AC_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC01040AC_TABLE + }, + { + 0x4, + 0xC0107044, + sizeof (D0F0xBC_xC0107044_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107044_TABLE + }, + { + 0x4, + 0xC0107064, + sizeof (D0F0xBC_xC0107064_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107064_TABLE + }, + { + 0x4, + 0xC0107067, + sizeof (D0F0xBC_xC0107067_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107067_TABLE + }, + { + 0x4, + 0xC0107068, + sizeof (D0F0xBC_xC0107068_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107068_TABLE + }, + { + 0x4, + 0xC010706b, + sizeof (D0F0xBC_xC010706B_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706B_TABLE + }, + { + 0x4, + 0xC010706c, + sizeof (D0F0xBC_xC010706C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706C_TABLE + }, + { + 0x4, + 0xC010706f, + sizeof (D0F0xBC_xC010706F_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706F_TABLE + }, + { + 0x4, + 0xC0107070, + sizeof (D0F0xBC_xC0107070_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107070_TABLE + }, + { + 0x4, + 0xC0107073, + sizeof (D0F0xBC_xC0107073_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107073_TABLE + }, + { + 0x4, + 0xC0107074, + sizeof (D0F0xBC_xC0107074_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107074_TABLE + }, + { + 0x4, + 0xC0107077, + sizeof (D0F0xBC_xC0107077_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107077_TABLE + }, + { + 0x4, + 0xC0107078, + sizeof (D0F0xBC_xC0107078_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107078_TABLE + }, + { + 0x4, + 0xC010707c, + sizeof (D0F0xBC_xC010707C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010707C_TABLE + }, + { + 0x4, + 0xC0107080, + sizeof (D0F0xBC_xC0107080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107080_TABLE + }, + { + 0x4, + 0xC0107083, + sizeof (D0F0xBC_xC0107083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107083_TABLE + }, + { + 0x4, + 0xC0107084, + sizeof (D0F0xBC_xC0107084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107084_TABLE + } +}; + +F1_TABLE_ENTRY_KB PPRegisterTableKB [] = { + { + D18F3x64_TYPE, + D18F3x64_ADDRESS, + sizeof (D18F3x64_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F3x64_TABLE + }, + { + 0x4, + 0xC0500000, + sizeof (GnbFuseTableKB565_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + GnbFuseTableKB565_TABLE + }, + { + D18F2x90_dct0_TYPE, + D18F2x90_dct0_ADDRESS, + sizeof (D18F2x90_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2x90_dct0_TABLE + }, + { + D18F2x94_dct0_TYPE, + D18F2x94_dct0_ADDRESS, + sizeof (D18F2x94_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2x94_dct0_TABLE + }, + { + D18F2xA8_dct0_TYPE, + D18F2xA8_dct0_ADDRESS, + sizeof (D18F2xA8_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2xA8_dct0_TABLE + }, + { + D18F5x160_TYPE, + D18F5x160_ADDRESS, + sizeof (D18F5x160_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x160_TABLE + }, + { + D18F5x164_TYPE, + D18F5x164_ADDRESS, + sizeof (D18F5x164_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x164_TABLE + }, + { + D18F5x168_TYPE, + D18F5x168_ADDRESS, + sizeof (D18F5x168_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x168_TABLE + }, + { + D18F5x16C_TYPE, + D18F5x16C_ADDRESS, + sizeof (D18F5x16C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x16C_TABLE + } +}; + + +F1_TABLE_KB F1TableKB = { + sizeof (F1RegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + F1RegisterTableKB +}; + +F1_TABLE_KB PPTableKB = { + sizeof (PPRegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + PPRegisterTableKB +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Load F1 Table KB + * + * + * param[out] PpF1Array Pointer to save f1 table + * param[in] StdHeader Pointer to Standard configuration + * retval AGESA_STATUS + */ + +STATIC VOID +NbF1LoadF1TableKB ( + IN F1_TABLE_KB *F1Table, + OUT PP_F1_ARRAY_V2 *PpF1Array, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN RegisterIndex; + + for (RegisterIndex = 0; RegisterIndex < F1Table->F1TableLength; RegisterIndex++ ) { + UINTN FieldIndex; + UINTN F1RegisterTableLength; + UINT32 F1Value; + F1RegisterTableLength = F1Table->F1Table[RegisterIndex].F1RegisterTableLength; + + GnbRegisterReadKB ( + GnbGetHandle (StdHeader), + F1Table->F1Table[RegisterIndex].RegisterSpaceType, + F1Table->F1Table[RegisterIndex].Register, + &F1Value, + 0, + StdHeader + ); + for (FieldIndex = 0; FieldIndex < F1RegisterTableLength; FieldIndex++) { + F1_REGISTER_ENTRY_KB RegisterEntry; + RegisterEntry = F1Table->F1Table[RegisterIndex].F1RegisterTable[FieldIndex]; + *((UINT8 *) PpF1Array + RegisterEntry.F1Offset) = (UINT8) ((F1Value >> RegisterEntry.FieldOffset) & + ((1 << RegisterEntry.FieldWidth) - 1)); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb load f1 table + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbLoadF1TableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_F1_ARRAY_V2 *PpF1Array; + AGESA_STATUS Status; + D18F3xA0_STRUCT D18F3xA0; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadF1TableKB Enter\n"); + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbAllocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, sizeof (PP_F1_ARRAY_V2), StdHeader); + ASSERT (PpF1Array != NULL); + if (PpF1Array != NULL) { + //Support for real f1 table + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader); + + if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealF1Table)) { + NbF1LoadF1TableKB (&F1TableKB, PpF1Array, StdHeader); + PpF1Array->PP_FUSE_ARRAY_V2_fld13 = TRUE; + IDS_HDT_CONSOLE (NB_MISC, " Processor F1d\n"); + } else { + LibAmdMemCopy (PpF1Array, &DefaultPpF1ArrayKB, sizeof (PP_F1_ARRAY_V2), StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Processor Unf1d\n"); + } + NbF1LoadF1TableKB (&PPTableKB, PpF1Array, StdHeader); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPF1_OVERRIDE, PpF1Array, StdHeader); + } else { + Status = AGESA_ERROR; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadF1TableKB Exit [0x%x]\n", Status); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h new file mode 100644 index 0000000000..8ea51d0c0d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * F1 table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBF1TABLEKB_H_ +#define _GNBF1TABLEKB_H_ + +#pragma pack (push, 1) + +/// F1 field entry +typedef struct { + UINT8 FieldOffset; ///< Field offset in f1 register + UINT8 FieldWidth; ///< Width of field + UINT16 F1Offset; ///< destination offset in translation table +} F1_REGISTER_ENTRY_KB; + +/// F1 register entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Register; ///< FCR register address + UINT8 F1RegisterTableLength; ///< Length of field table for this register + F1_REGISTER_ENTRY_KB *F1RegisterTable; ///< Pointer to field table +} F1_TABLE_ENTRY_KB; + +/// F1 translation table +typedef struct { + UINT8 F1TableLength; ///< Length of translation table + F1_TABLE_ENTRY_KB *F1Table; ///< Pointer to register table +} F1_TABLE_KB; + +#pragma pack (pop) + +AGESA_STATUS +GnbLoadF1TableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h new file mode 100644 index 0000000000..47b8fd51a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h @@ -0,0 +1,234 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB service installation file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNB_INIT_KB_INSTALL_H_ +#define _GNB_INIT_KB_INSTALL_H_ + +//----------------------------------------------------------------------- +// Specify definition used by module services +//----------------------------------------------------------------------- + +#include "GnbPcie.h" +#include "GnbUraServices.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" +#include "GnbGfxFamServices.h" + +//----------------------------------------------------------------------- +// Export services +//----------------------------------------------------------------------- + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + + extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoKB; + extern F_PCIEFMGETCOMPLEXDATALENGTH PcieGetComplexDataLengthKB; + extern F_PCIEFMBUILDCOMPLEXCONFIGURATION PcieBuildComplexConfigurationKB; + extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION PcieConfigureEnginesLaneAllocationKB; + extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING PcieCheckPortPciDeviceMappingKB; + extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressKB; + extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedKB; + + + PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolKB = { + PcieGetComplexDataLengthKB, + PcieBuildComplexConfigurationKB, + PcieConfigureEnginesLaneAllocationKB, + PcieCheckPortPciDeviceMappingKB, + PcieMapPortPciAddressKB, + PcieCheckPortPcieLaneCanBeMuxedKB, + PcieGetSbConfigInfoKB + }; + + GNB_SERVICE GnbPcieCongigServicesKB = { + GnbPcieFamConfigService, + AMD_FAMILY_KB, + &GnbPcieConfigProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieCongigServicesKB +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + extern F_PCIEFMGETCORECONFIGURATIONVALUE PcieGetCoreConfigurationValueKB; + extern F_PCIEFMGETLINKSPEEDCAP PcieGetLinkSpeedCapKB; + extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapKB; + extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; + + PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolKB = { + PcieGetCoreConfigurationValueKB, + PcieGetLinkSpeedCapKB, + PcieGetNativePhyLaneBitmapKB, + PcieSetLinkSpeedCapV4 + }; + + GNB_SERVICE GnbPcieInitServicesKB = { + GnbPcieFamInitService, + AMD_FAMILY_KB, + &GnbPcieInitProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieInitServicesKB +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING PcieDebugGetHostRegAddressSpaceStringKB; + extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringKB; + extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringKB; + + PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolKB = { + PcieDebugGetHostRegAddressSpaceStringKB, + PcieDebugGetWrapperNameStringKB, + PcieDebugGetCoreConfigurationStringKB + }; + + GNB_SERVICE GnbPcieDebugServicesKB = { + GnbPcieFamDebugService, + AMD_FAMILY_KB, + &GnbPcieDebugProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieDebugServicesKB + #endif + #endif +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + extern F_GNB_REGISTER_ACCESS GnbRegisterReadKB; + extern F_GNB_REGISTER_ACCESS GnbRegisterWriteKB; + + GNB_REGISTER_SERVICE GnbRegisterAccessProtocolKB = { + GnbRegisterReadKB, + GnbRegisterWriteKB + }; + + GNB_SERVICE GnbRegisterAccessServicesKB = { + GnbRegisterAccessService, + AMD_FAMILY_KB, + &GnbRegisterAccessProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbRegisterAccessServicesKB + + extern F_GNBURASERVICELOCATEREGTBL GnbUraLocateRegTblKB; + extern F_GNBURASERVICEGET GnbUraGetKB; + extern F_GNBURASERVICESET GnbUraSetKB; + extern F_GNBURASERVICESTREAMSET GnbUraStreamSetKB; + + GNB_URA_SERVICE GnbUraProtocolKB = { + GnbUraLocateRegTblKB, + GnbUraGetKB, + GnbUraSetKB, + GnbUraStreamSetKB + }; + + GNB_SERVICE GnbUraServicesKB = { + GnbUraService, + AMD_FAMILY_KB, + &GnbUraProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbUraServicesKB + + extern F_GFXMAPENGINETODISPLAYPATH GfxMapEngineToDisplayPathKB; + extern F_GFXDISABLECONTROLLER GfxDisableControllerKB; + extern F_GFXCALCULATECLOCK GfxCalculateClockKB; + extern F_GFXISVBIOSPOSTED GfxIsVbiosPostedKB; + + GFX_FAM_SERVICES GfxFamilyServiceProtocolKB = { + GfxMapEngineToDisplayPathKB, + GfxDisableControllerKB, + GfxCalculateClockKB, + GfxIsVbiosPostedKB + }; + + GNB_SERVICE GfxFamilyServicesKB = { + GfxFamService, + AMD_FAMILY_KB, + &GfxFamilyServiceProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GfxFamilyServicesKB + + extern F_GNBTIMESTAMP GnbTimeStampKB; + + GNB_FAM_TS_SERVICES GnbFamTsProtocolKB = { + GnbTimeStampKB, + }; + + GNB_SERVICE GnbFamTsServicesKB = { + GnbFamTsService, + AMD_FAMILY_KB, + &GnbFamTsProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbFamTsServicesKB + + + extern F_PCIE_MAXPAYLOAD_SETTING PcieMaxPayloadKB; + + PCIE_MAXPAYLOAD_SERVICE PcieMaxPayloadProtocolKB = { + PcieMaxPayloadKB + }; + + GNB_SERVICE PcieMaxPayloadServicesKB = { + GnbPcieMaxPayloadService, + AMD_FAMILY_KB, + &PcieMaxPayloadProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &PcieMaxPayloadServicesKB + +#endif +#endif // _GNB_INIT_KB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c new file mode 100644 index 0000000000..82f32dd62e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c @@ -0,0 +1,165 @@ +/** + * @file + * + * GNB init tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GnbIommuInitTableKB [] = { + + // 1. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 1h + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET) + ), + // 2. Program credits for the BIF client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_BIF << 16) | 0x32), + 0x10000 | 0x3F0 | 0xFC00, + (0x1 << 16) | (0x8 << 4) | (0x8 << 10) + ), + // 3. Program credits for the PPD client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_PPD << 16) | 0x32), + 0x3F0 | 0xFC00, + (0x8 << 4) | (0x7 << 10) + ), + // 4. Program credits for the INTGEN client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_INTGEN << 16) | 0x32), + 0x3F0 | 0xFC00, + (0x4 << 4) | (0x4 << 10) + ), + // 5. Program clock gating as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_PPD << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_BIF << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_INTGEN << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + // 6. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 0h + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + 0 + ), + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c new file mode 100644 index 0000000000..b9ba10de20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c @@ -0,0 +1,429 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbPcieConfig.h" +#include "GnbF1Table.h" +#include "heapManager.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbGfxInitLibV1.h" +#include "GnbSmuInitLibV7.h" +#include "GnbTable.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbFamServices.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbMidInitTableKB[]; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * @param[out] Index State index + * @param[in] PpF1s + * @retval TRUE State is valid + */ +STATIC BOOLEAN +GnbIsF1dStateValid ( + IN UINT8 Index, + IN PP_F1_ARRAY_V2 *PpF1s + ) +{ + BOOLEAN Result; + Result = FALSE; + + if (Index >= 5) { + Result = FALSE; + } else if ((PpF1s->PP_FUSE_ARRAY_V2_fld37 & (1 << Index)) || + (PpF1s->PP_FUSE_ARRAY_V2_fld38 & (1 << Index))) { + Result = TRUE; + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * LCLK DPM Initialization + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbLclkDpmInitKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PP_F1_ARRAY_V2 *PpF1Array; + PCI_ADDR GnbPciAddress; + UINT8 Index; + UINT8 LclkDpmMode; + + UINT32 D0F0xBC_x3FD00[8]; + UINT32 D0F0xBC_x3FD04[8]; + UINT32 D0F0xBC_x3FD08[8]; + UINT32 D0F0xBC_x3FD0C[8]; + UINT32 D0F0xBC_x3FD10[8]; + UINT32 D0F0xBC_x3FDC8; + UINT32 D0F0xBC_x3F820; + UINT32 D0F0xBC_x3FDC4; + UINT32 D0F0xBC_xC0200110; + + GNB_HANDLE *GnbHandle; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitKB Enter\n"); + Status = AGESA_SUCCESS; + + GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = StdHeader; + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, 0, StdHeader); + D0F0xBC_x3F820 &= ~0xFF; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; + IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); + if (LclkDpmMode == LclkDpmRcActivity) { + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + if (PpF1Array != NULL) { + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + //Clear DPM_EN bit in LCLK_DPM_CNTL register + //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, 0, StdHeader); + D0F0xBC_x3FDC8 &= 0x00FFFFFF; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + //Initialize LCLK states + LibAmdMemFill (D0F0xBC_x3FD00, 0x00, sizeof (D0F0xBC_x3FD00), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD04, 0x00, sizeof (D0F0xBC_x3FD04), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD08, 0x00, sizeof (D0F0xBC_x3FD08), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD0C, 0x00, sizeof (D0F0xBC_x3FD0C), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD10, 0x00, sizeof (D0F0xBC_x3FD10), StdHeader); + + for (Index = 0; Index < 8; ++Index) { + + if (GnbIsF1dStateValid (Index, PpF1Array)) { + + ASSERT (Index < 5); + IDS_HDT_CONSOLE (GNB_TRACE, " Valid Lclk state: %d\n", Index); + + // CNTL0 + D0F0xBC_x3FD00[Index] = 0; + D0F0xBC_x3FD00[Index] |= (PpF1Array->PP_FUSE_ARRAY_V2_fld5[Index] & 0xFF) << 16; + D0F0xBC_x3FD00[Index] |= 1 << 24; + + // CNTL1 + D0F0xBC_x3FD04[Index] = GnbTranslateVidCodeToMillivoltV5 ( + PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index], StdHeader + ) * 4 / 100; + + // CNTL2 + // D0F0xBC_x3FD08 defined as zero and is already zeroed above + D0F0xBC_x3FD08[Index] = 0; + + // CNTL3 + D0F0xBC_x3FD0C[Index] = + GfxFmCalculateClock (PpF1Array->PP_FUSE_ARRAY_V2_fld5[Index], StdHeader); + D0F0xBC_x3FD10[Index] &= ~(0xFF << 8); + switch (D0F0xBC_x3FD0C[Index]) { + case 20000: + D0F0xBC_x3FD10[Index] |= 0x7 << 8; + break; + case 30000: + D0F0xBC_x3FD10[Index] |= 0x2 << 8; + break; + case 40000: + D0F0xBC_x3FD10[Index] |= 0x3 << 8; + break; + case 15000: + D0F0xBC_x3FD10[Index] |= 0x6 << 8; + break; + case 10000: + D0F0xBC_x3FD10[Index] |= 0x8 << 8; + break; + default: + break; + } + + // Activity Threshold + D0F0xBC_x3FD10[Index] &= ~0xFFFF0000; + D0F0xBC_x3FD10[Index] |= 50 << 24; + } else { + + IDS_HDT_CONSOLE (GNB_TRACE, " Invalid Lclk state: %d\n", Index); + + // CNTL0 + D0F0xBC_x3FD00[Index] = 0xF800; + + // CNTL1 + D0F0xBC_x3FD04[Index] = 0x0; + + // CNTL2 + // D0F0xBC_x3FD08 defined as zero and is already zeroed above + D0F0xBC_x3FD08[Index] = 0; + + // CNTL3 + D0F0xBC_x3FD0C[Index] = 0; + + // Activity Threshold + D0F0xBC_x3FD10[Index] &= ~0xFFFF0000; + D0F0xBC_x3FD10[Index] |= 50 << 24; + } + + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd00 + Index * 0x14, + &D0F0xBC_x3FD00[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd04 + Index * 0x14, + &D0F0xBC_x3FD04[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd08 + Index * 0x14, + &D0F0xBC_x3FD08[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd0c + Index * 0x14, + &D0F0xBC_x3FD0C[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd10 + Index * 0x14, + &D0F0xBC_x3FD10[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + //Enable LCLK DPM Voltage Scaling + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, 0, StdHeader); + D0F0xBC_x3FDC8 &= 0xFF; + D0F0xBC_x3FDC8 |= 1 << 16 | 1 << 24; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc4, &D0F0xBC_x3FDC4, 0, StdHeader); + D0F0xBC_x3FDC4 = 5; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc4, &D0F0xBC_x3FDC4, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, 0, StdHeader); + D0F0xBC_x3F820 &= ~0xFF; D0F0xBC_x3F820 |= 1; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0xc0200110, &D0F0xBC_xC0200110, 0, StdHeader); + D0F0xBC_xC0200110 &= ~(1 << 2 | 7 << 5 | 0xfffff800); + D0F0xBC_xC0200110 &= ~(1 << 0 | 1 << 1 | 1 << 8); + D0F0xBC_xC0200110 |= 3<<3 | 1 << 9 | 1 << 10; //.Field.BusyCntSel = 3; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0xc0200110, &D0F0xBC_xC0200110, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_LCLK_DPM_ENABLE, + 0, + GNB_REG_ACC_FLAG_S3SAVE + ); + + } + } else { + Status = AGESA_ERROR; + } + + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_ENABLE_ALLCLK_MONITOR, + 0, + GNB_REG_ACC_FLAG_S3SAVE + ); + + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitKB Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT32 Property; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceKB Enter\n"); + + Property = TABLE_PROPERTY_DEFAULT; + Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED; + Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0; + Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? 0x00000008ul : 0; + Property |= 0x00000010ul; + Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? 0x00000020ul : 0; + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbMidInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + GnbPciAddress = GnbGetHostPciAddress (GnbGetHandle (StdHeader)); + GnbLibPciIndirectWriteField ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x0F_ADDRESS, + D0F0xFC_x0F_GBIFExtIntrGrp_OFFSET, + D0F0xFC_x0F_GBIFExtIntrGrp_WIDTH, + 5, + AccessS3SaveWidth32, + StdHeader + ); + + GnbLibPciIndirectWriteField ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x0F_ADDRESS, + D0F0xFC_x0F_GBIFExtIntrSwz_OFFSET, + D0F0xFC_x0F_GBIFExtIntrSwz_WIDTH, + 0, + AccessS3SaveWidth32, + StdHeader + ); + + Status = GnbLclkDpmInitKB (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c new file mode 100644 index 0000000000..ce6eda2b09 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c @@ -0,0 +1,120 @@ +/** + * @file + * + * GNB post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbPcieConfig.h" +#include "GfxLibV3.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + GFX_PLATFORM_CONFIG *Gfx; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Status = GnbSetTomV5 (GnbPciAddress, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c new file mode 100644 index 0000000000..499275bb00 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c @@ -0,0 +1,585 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbSmuInitLibV7.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBREGISTERACCKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define GNB_IGNORED_PARAM 0xFF +#define ORB_WRITE_ENABLE 0x100 +#define IOMMU_L1_WRITE_ENABLE 0x80000000ul +#define IOMMU_L2_WRITE_ENABLE 0x100 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbRegisterWriteKBDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ); + + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR GnbPciAddress; + + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + + switch (RegisterSpaceType) { + case 0x1: + GnbLibPciRead ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x8: + GnbPciAddress.Address.Function = 2; + GnbLibPciRead ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x6: ///@todo has to be DxFx + GnbLibPciRead ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + case TYPE_D18F2_dct0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case 0x2: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x3: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x4: + { + UINT64 TempData; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + (Address & (~0x3ull)), + Width, + &TempData, + StdHeader + ); + if ((Address & 0x3) != 0) { + //Non aligned access allowed to fuse block + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + (Address & (~0x3ull)) + 4, + Width, + ((UINT32 *) &TempData) + 1, + StdHeader + ); + } + * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8)); + break; + } + case 0x22: + // D0F0xD0 Link Index Address, access D0F0xD4_x[0130_14BF:0109_0000] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xD0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x5: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xE0_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x9: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xF0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0xa: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xF8, + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrRead (Address, Value, StdHeader); + break; + + case 0x12: + ASSERT (Address < 0x40000); + // SRBM + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + break; + + default: + ASSERT (FALSE); + break; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * @param[in] GnbHandle GnbHandle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR GnbPciAddress; + DEV_OBJECT DevObject; + + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + GNB_DEBUG_CODE ( + GnbRegisterWriteKBDump (RegisterSpaceType, Address, Value); + ); + + switch (RegisterSpaceType) { + case 0x1: + GnbLibPciWrite ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x8: + GnbPciAddress.Address.Function = 2; + GnbLibPciWrite ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x6: /// @todo needs to be DxFx + GnbLibPciWrite ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + case TYPE_D18F2_dct0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case 0x2: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + Address | IOC_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0x3: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + Address | ORB_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0x4: + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x22: + // D0F0xD0 Link Index Address, access D0F0xD4_x[0130_14BF:0109_0000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xD0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x5: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xE0_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x9: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xF0, + Address | IOMMU_L2_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0xa: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xF8, + Address | IOMMU_L1_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrWrite (Address, Value, StdHeader); + break; + + case 0x12: + ASSERT (Address < 0x40000); + // SRBM + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + break; + + case TYPE_SMU_MSG: + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 (&DevObject, (UINT8) Address, *((UINT32 *)Value), Flags); + break; + + default: + ASSERT (FALSE); + break; + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to dump all write register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset + * @param[in] Value The value to write + */ +VOID +GnbRegisterWriteKBDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ) +{ + IDS_HDT_CONSOLE (NB_MISC, " R WRITE Space %s Address 0x%04x, Value 0x%04x\n", + (RegisterSpaceType == 0x1) ? "0x1" : ( + (RegisterSpaceType == 0x2) ? "0x2" : ( + (RegisterSpaceType == 0x3) ? "0x3" : ( + (RegisterSpaceType == 0x4) ? "0x4" : ( + (RegisterSpaceType == 0x22) ? "0x22" : ( + (RegisterSpaceType == 0x5) ? "0x5" : ( + (RegisterSpaceType == 0x6) ? "0x6" : ( + (RegisterSpaceType == TYPE_D18F0) ? "TYPE_D18F0" : ( + (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : ( + (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : ( + (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : ( + (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : ( + (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : ( + (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : ( + (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : ( + (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : ( + (RegisterSpaceType == 0x12) ? "0x12" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : ( + (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))), + Address, + *((UINT32*)Value) + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h new file mode 100644 index 0000000000..326c0b32f5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h @@ -0,0 +1,68 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various register access service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBREGISTERACCKB_H_ +#define _GNBREGISTERACCKB_H_ + +AGESA_STATUS +GnbRegisterWriteKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterReadKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h new file mode 100644 index 0000000000..bed59c0d32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h @@ -0,0 +1,2103 @@ +/** + * @file + * + * SAMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBSAMUPATCHKB_H_ +#define _GNBSAMUPATCHKB_H_ + +UINT8 SamuPatchKB[] = { + 0x9d, + 0xaf, + 0x50, + 0x9, + 0x10, + 0x3, + 0xf6, + 0x5f, + 0x7b, + 0x29, + 0x2d, + 0xe0, + 0x33, + 0xbd, + 0x76, + 0x53, + 0x0, + 0x4, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x83, + 0x4f, + 0x17, + 0x8e, + 0x1f, + 0x7e, + 0x2, + 0xbb, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x4, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x80, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 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0xfe, + 0x81, + 0xb5, + 0x6a, + 0x97, + 0xd0, + 0x3e, + 0x4e, + 0x7c, + 0x20, + 0xac, + 0xb, + 0x28, + 0xde, + 0x5e, + 0x73, + 0x9c, + 0xb3, + 0x28, + 0xd6, + 0xa0, + 0xd, + 0x6e, + 0x41, + 0x2b, + 0x82, + 0xa8, + 0xb9, + 0x45, + 0x3d, + 0x5d, + 0xd7, + 0xa, + 0xa6, + 0x16, + 0xcd, + 0xfb, + 0x6a, + 0x63, + 0xab, + 0x50, + 0x4c, + 0x2, + 0xce, + 0x4b, + 0xbf, + 0xac, + 0x68, + 0x24, + 0x5b, + 0x56, + 0xc0, + 0x72, + 0xe6, + 0x63, + 0x0, + 0xff, + 0x71, + 0xbd, + 0x4a, + 0x0, + 0x8b, + 0xff, + 0xff, + 0x2b, + 0xe1, + 0x89, + 0xb0, + 0xd1, + 0x8c, + 0x15, + 0x74, + 0xe9, + 0xef, + 0x5b, + 0x88, + 0xe4, + 0x6e, + 0x94, + 0x52, + 0x66, + 0xcb, + 0xcf, + 0x77, + 0x7f, + 0xb, + 0xc0, + 0x88, + 0x99, + 0x9f, + 0xce, + 0xbe, + 0xf3, + 0xf0, + 0x9d, + 0x42, + 0xe, + 0x8f, + 0x63, + 0x7c, + 0x2, + 0x6f, + 0x7, + 0x2, + 0xb1, + 0x91, + 0xbe, + 0xdc, + 0x28, + 0xc8, + 0x1d, + 0x1c, + 0xfb, + 0xb, + 0xcf, + 0x96, + 0x73, + 0x56, + 0x70, + 0x10, + 0xdc, + 0x41, + 0xad, + 0x15, + 0x70, + 0xab, + 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+ 0x95, + 0x6a, + 0x69, + 0x48, + 0x47, + 0xf8, + 0x5e, + 0x2f, + 0x9f, + 0xcd, + 0x1f, + 0xcb, + 0x35, + 0xbf, + 0x90, + 0x70, + 0x75, + 0xff, + 0x7d, + 0x4e, + 0xa8, + 0x0, + 0xed, + 0x3, + 0xee, + 0xce, + 0x83, + 0x2d, + 0xca, + 0x75, + 0xad, + 0x82, + 0x94, + 0x86, + 0xec, + 0x58, + 0x4, + 0x8f, + 0x6c, + 0x34, + 0x89, + 0x8, + 0xac, + 0x53, + 0x74, + 0x8c, + 0xf1, + 0x8a, + 0xf9, + 0x55, + 0x31, + 0xaf, + 0xb7, + 0x9, + 0xd8, + 0x66, + 0x5, + 0xa0, + 0xe2, + 0x84, + 0x8e, + 0x21, + 0x35, + 0xb0, + 0x66, + 0x87, + 0x40, + 0xd0, + 0xbd, + 0xf3, + 0x6e, + 0x57, + 0xf5, + 0x7e, + 0x3a, + 0xe4, + 0x6f, + 0x8d, + 0x8c, + 0xfb, + 0x45, + 0x36, + 0x53, + 0xd3, + 0xf7, + 0x32, + 0xd5, + 0x21, + 0xb, + 0x81, + 0xe0, + 0x7, + 0xc9, + 0x68, + 0xc4, + 0x93, + 0x59, + 0x7a, + 0xcb, + 0xad, + 0x65, + 0xb7, + 0x66, + 0x84, + 0x2f, + 0x3b, + 0x9f, + 0xe7, + 0x43, + 0x11, + 0x36, + 0xa5, + 0x36, + 0x77, + 0x32, + 0xbd, + 0x1d, + 0x7d, + 0x49, + 0x61, + 0x79, + 0x88, + 0x2d, + 0x8e, + 0x41, + 0xec, + 0x14, + 0x31, + 0xf9, + 0xaa, + 0x97, + 0x1a, + 0x39, + 0x6a, + 0xb3, + 0xe8, + 0xdb, + 0x57, + 0xd4, + 0x6d, + 0xed, + 0xa6, + 0x2a, + 0x3c, + 0xba, + 0x7, + 0x8a, + 0x22, + 0x5f, + 0xa7, + 0xc3, + 0xa1, + 0x3, + 0x86, + 0xa8, + 0xa, + 0x12, + 0x0, + 0x1f, + 0xd0, + 0x1a, + 0xc7, + 0x5d, + 0xdf, + 0x51, + 0xad, + 0x2e, + 0xf6, + 0x1e, + 0xb7, + 0xb2, + 0x1f, + 0x40, + 0x76, + 0x72, + 0xf0, + 0x6, + 0x4a, + 0x1f, + 0x69, + 0x3, + 0xc5, + 0x7f, + 0x93, + 0x5c, + 0x31, + 0x6e, + 0x8b, + 0x3a, + 0xc7, + 0x46, + 0xc5, + 0xe3, + 0x8b, + 0x9d, + 0xf4, + 0x79, + 0x6d, + 0x2e, + 0x7f, + 0x45, + 0x5c, + 0x9e, + 0x2d, + 0xec, + 0xe8, + 0x91, + 0xd0, + 0x37, + 0xc7, + 0xba, + 0x73, + 0x87, + 0x79, + 0x8a, +}; + +UINT32 SamuPatchKBHeader[] = { + 0x53414d55, + 0x410 +}; + +UINT8 SamuPatchKBUnf1[] = { + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0xe8, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 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0x0, + 0x65, + 0x28, + 0x0, + 0x40, + 0x23, + 0x34, + 0x0, + 0x0, + 0x65, + 0x28, + 0x0, + 0x0, + 0x23, + 0x28, + 0x10, + 0x0, + 0x21, + 0x34, + 0x1, + 0x0, + 0x84, + 0x34, + 0x2, + 0x0, + 0x82, + 0x54, + 0xf8, + 0xff, + 0xff, + 0xe3, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x0, + 0x4, + 0x34, + 0x9, + 0x0, + 0x83, + 0x50, + 0x1, + 0x0, + 0x5, + 0x78, + 0x0, + 0x0, + 0xa5, + 0x38, + 0x8, + 0x5, + 0x22, + 0xa8, + 0x0, + 0x8, + 0x25, + 0xb4, + 0x10, + 0x0, + 0x42, + 0x34, + 0x1, + 0x0, + 0x84, + 0x34, + 0x2, + 0x0, + 0x83, + 0x50, + 0xfb, + 0xff, + 0xff, + 0xe3, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x0, + 0x4, + 0x34, + 0x9, + 0x0, + 0x83, + 0x50, + 0x1, + 0x0, + 0x5, + 0x78, + 0x0, + 0x0, + 0xa5, + 0x38, + 0x8, + 0x15, + 0x20, + 0xa8, + 0x0, + 0x8, + 0x25, + 0xb4, + 0x10, + 0x0, + 0x42, + 0x34, + 0x1, + 0x0, + 0x84, + 0x34, + 0x2, + 0x0, + 0x83, + 0x50, + 0xfb, + 0xff, + 0xff, + 0xe3, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x20, + 0x20, + 0xb8, + 0xb0, + 0x0, + 0xa0, + 0x90, + 0x0, + 0x0, + 0x1, + 0x34, + 0xb0, + 0x0, + 0x20, + 0xd0, + 0x3, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x58, + 0xbc, + 0xff, + 0x0, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xf0, + 0x2, + 0x60, + 0xd0, + 0x18, + 0x0, + 0x0, + 0xe0, + 0x2, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x50, + 0xbc, + 0x0, + 0xff, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xd0, + 0x2, + 0x60, + 0xd0, + 0xf, + 0x0, + 0x0, + 0xe0, + 0x1, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x48, + 0xbc, + 0xff, + 0xff, + 0x1, + 0x78, + 0xff, + 0x0, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xb0, + 0x2, + 0x60, + 0xd0, + 0x6, + 0x0, + 0x0, + 0xe0, + 0x5, + 0x0, + 0x80, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x34, + 0x80, + 0x29, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0xa2, + 0xb8, + 0x90, + 0x2, + 0x60, + 0xd0, + 0xb0, + 0x0, + 0xa0, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0x3, + 0x0, + 0x21, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xf0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x41, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xd0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x1, + 0x0, + 0x41, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xb0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x40, + 0x5c, + 0x90, + 0x2, + 0x40, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0xb0, + 0x0, + 0x60, + 0x90, + 0x3, + 0x0, + 0x21, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0xff, + 0x0, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x41, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x1, + 0x0, + 0x41, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0xff, + 0xff, + 0x1, + 0x78, + 0xff, + 0x0, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x4, + 0x0, + 0x40, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x34, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x8, + 0xa0, + 0xbb, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0xff, + 0xff, + 0x42, + 0x34, + 0xff, + 0xff, + 0x41, + 0x64, + 0xfe, + 0xff, + 0x20, + 0x44, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x41, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0xd8, + 0x20, + 0x21, + 0x38, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0xd8, + 0x20, + 0x21, + 0x38, + 0x2, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x74, + 0x20, + 0x21, + 0x38, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x38, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x0, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x41, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x0, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0xff, + 0x1, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x25, + 0x1, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x0, + 0x0, + 0x0, + 0xe0, +}; + +UINT32 SamuPatchKBHeaderUnf1[] = { + 0x53414d55, + 0x3e8 +}; +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h new file mode 100644 index 0000000000..62736a3a20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h @@ -0,0 +1,32414 @@ +/** + * @file + * + * SMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87932 $ @e \$Date: 2013-02-13 13:53:55 -0600 (Wed, 13 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBSMUFIRMWAREKB_H_ +#define _GNBSMUFIRMWAREKB_H_ + +UINT32 FirmwareKBHeader [] = { + 0x554D535F, + 0x554D535F, + 0x0001F984, + 0x00002000, + 0x00010000, + 0xECE28940, + 0x0000424B, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +UINT32 FirmwareKB[] = { + 0x63c00f17, + 0xb9cfd803, + 0x196410db, + 0x8c378d8b, + 0xa8f232ce, + 0x000c0d00, + 0x00000100, + 0x00000000, + 0x00020100, + 0x00019900, + 0x0001f954, + 0x000398d8, + 0x0003f900, + 0x0003f000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00038c00, + 0x00038fa8, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xaa55aa55, + 0x98000000, + 0xd0000000, + 0x78010002, + 0x38210100, + 0xd0e10000, + 0xd1210000, + 0xe00000c4, + 0x34000000, + 0x379cff80, + 0x5b9d0074, + 0xf8000059, + 0x34010001, + 0xf8002e56, + 0xe000009a, + 0x34000000, + 0x34000000, + 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0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00002710, + 0x000003e8, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K +}; +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c new file mode 100644 index 0000000000..5c1fef2c20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c @@ -0,0 +1,499 @@ +/** + * @file + * + * GNB init tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86714 $ @e \$Date: 2013-01-24 17:51:46 -0600 (Thu, 24 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB [] = { + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_SMUCsrIsocEn_MASK, + (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x1E_TYPE, + D0F0x98_x1E_ADDRESS, + D0F0x98_x1E_HiPriEn_MASK, + (1 << D0F0x98_x1E_HiPriEn_OFFSET) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlyInitTableKB [] = { + // Set SVI2 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_SVI2, + 0x4, + 0x3F9D8, + 0x20000000, + (1 << 29) + ), + GNB_ENTRY_WR ( + D0F0x04_TYPE, + D0F0x04_ADDRESS, + (0x1 << D0F0x04_MemAccessEn_WIDTH) + ), + GNB_ENTRY_RMW ( + D0F0x64_x16_TYPE, + D0F0x64_x16_ADDRESS, + D0F0x64_x16_AerUrMsgEn_MASK, + 0x0 << D0F0x64_x16_AerUrMsgEn_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + + GNB_ENTRY_RMW ( + D0F0x98_x0C_TYPE, + D0F0x98_x0C_ADDRESS, + D0F0x98_x0C_GcmWrrLenA_MASK | D0F0x98_x0C_GcmWrrLenB_MASK, + (0x8 << D0F0x98_x0C_GcmWrrLenA_OFFSET) | (0x8 << D0F0x98_x0C_GcmWrrLenB_OFFSET) + ), + + // Enable voltage controller + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_VOLTAGE_CNTL_ENABLE, + 0 + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_COPY ( + 0x9, + 0x49, + 0, + 32, + D0F0x64_x1F_TYPE, + D0F0x64_x1F_ADDRESS, + 0, + 32 + ), + // Enable VPC + // CSR_GNB_1.SviTrimValueVdd = Vdd Trim + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F4, + 16, 8, + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH + ), + // CSR_GNB_1.SviTrimValueVddNB = VddNB Trim + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F4, + 24, 8, + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH + ), + // CSR_GNB_3.SviLoadLineOffsetVdd = Vdd Offset + + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F8, + 0, 8, + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH + ), + // CSR_GNB_3.SviLoadLineOffsetVddNB = VddNB Offset + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F8, + 8, 8, + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH + ), + + // Set SRBM time out + GNB_ENTRY_RMW ( + 0x12, + 0xE40, + 0x1FFF, + (0x1FFF << 0) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEnvInitTableKB [] = { + //--------------------------------------------------------------------------- + + // SMU Enable Thermal Controller + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + 56, + 0 + ), + // Enable VPC + GNB_ENTRY_PROPERTY_RMW ( + 0x00040000ul, + 0x4, + 0x3F9D8, + 0x1, + (1 << 0) + ), + // Enable LHTC + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_LHTC, + SMU_MSG_TYPE, + 70, + 0 + ), + GNB_ENTRY_PROPERTY_WR ( + 0x00040000ul, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VPC_ACCUMULATOR, + 0 + ), + + // PM_CONFIG.f.enable_tdc_limit = 1; + GNB_ENTRY_PROPERTY_RMW ( + 0x00040000ul, + 0x4, + 0x3F9D8, + 0x4, + (1 << 2) + ), + GNB_ENTRY_PROPERTY_WR ( + 0x00040000ul, + SMU_MSG_TYPE, + 46, + 0 + ), + + // Enable Package Power Limit + GNB_ENTRY_PROPERTY_WR ( + 0x00080000ul, + SMU_MSG_TYPE, + SMC_MSG_ENABLE_PKGPWRLIMIT, + 0 + ), + + // Enable BAPM + // PM_CONFIG.f.enable_bapm = 1; + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + 0x4, + 0x3F9D8, + 0x2, + (1 << 1) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + 48, + 0 + ), +//--------------------------------------------------------------------------- +// ORB Init + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK | D0F0x98_x07_DmaReqRespPassPWMode_MASK, + (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) | (0 << D0F0x98_x07_DmaReqRespPassPWMode_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x08_TYPE, + D0F0x98_x08_ADDRESS, + D0F0x98_x08_NpWrrLenC_MASK, + 0x1 << D0F0x98_x08_NpWrrLenC_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x28_TYPE, + D0F0x98_x28_ADDRESS, + D0F0x98_x28_ForceCoherentIntr_MASK, + 0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_SBDmaActiveMask_MASK | D0F0x98_x2C_CgttLclkOverride_MASK, + (1 << D0F0x98_x2C_SBDmaActiveMask_OFFSET) | (1 << D0F0x98_x2C_CgttLclkOverride_OFFSET) + ), + // Enable gBIF UID Clumping [BIT 23:21 = 011b] + GNB_ENTRY_RMW ( + D0F0x98_x3A_TYPE, + D0F0x98_x3A_ADDRESS, + 0x00E00000, + 0x00600000 + ), + GNB_ENTRY_RMW ( + D18F0x110_TYPE, + D18F0x110_ADDRESS, + 0x00E00000, + 0x00600000 + ), + //NB P-state Configuration for Runtime + GNB_ENTRY_RMW ( + 0x4, + 0x3F9E8, + 0xFF | 0xFF00 | + 0xFF0000 | 0xFF000000, + (3 << 0) | (0 << 8) | + (2 << 16) | (1 << 24) + ), + // Programming a conservative watermark for NBP states + GNB_ENTRY_RMW ( + 0x12, + 0x6cd8, + 0x10 | + 0x100 | + 0xffff0000, + (1 << 4) | + (1 << 8) | + (0x7FFF << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cc8, + 0x3 | + 0x30000, + (0x3 << 0) | + (0x3 << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd4, + 0xffff0000, + (0x7FFF << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd4, + 0x1, + (1 << 0) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd8, + 0x1, + (1 << 0) + ), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbMidInitTableKB [] = { +//--------------------------------------------------------------------------- +// ORB clock gating + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x49_TYPE, + D0F0x98_x49_ADDRESS, + D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x4A_TYPE, + D0F0x98_x4A_ADDRESS, + D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_CgttLclkOverride_MASK, + 0x0 + ), +//--------------------------------------------------------------------------- +// IOC clock gating + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x22_TYPE, + D0F0x64_x22_ADDRESS, + 0x4000000 | 0x8000000 | 0x10000000 | 0x20000000 | 0x40000000, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x23_TYPE, + D0F0x64_x23_ADDRESS, + 0x4000000 | 0x8000000 | 0x10000000 | 0x20000000 | 0x40000000, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x46_TYPE, + D0F0x64_x46_ADDRESS, + 0x10000, + 0x0 + ), + //--------------------------------------------------------------------------- + GNB_ENTRY_RMW ( + 0x4, + 0xc0200110, + 0x18 | 0x1 | + 0x2 | 0x200 | + 0x400, + (0x3 << 3) | + (0 << 0) | + (0x0 << 1) | + (0x1 << 9) | + (0x1 << 10) + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc0200310, + 0x20 | + 0x40 | + 0x80 | + 0x100 | + 0x200 | + 0x400 | + 0x800 | + 0x1000 | + 0x2000 | + 0x4000 | + 0x8000 | + 0x10000 | + 0x20000 | + 0x40000 | + 0x80000 | + 0x100000 | + 0x1 | + 0x2 | + 0x4, + ( 1 << 5) | + ( 0 << 6) | + ( 0 << 7) | + ( 0 << 8) | + ( 0 << 9) | + ( 1 << 10) | + ( 1 << 11) | + ( 1 << 12) | + ( 1 << 13) | + ( 1 << 14) | + ( 1 << 15) | + ( 1 << 16) | + ( 1 << 17) | + ( 1 << 18) | + ( 1 << 19) | + ( 1 << 20) | + ( 1 << 0) | + ( 1 << 1) | + ( 1 << 2) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc020008c, + 0x7 | + 0x8 | + 0xfff0, + ( 5 << 0) | + ( 0 << 3) | + ( 0xF << 4) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + 0x4, + 0xc0200310, + 0x200000, + 0x0 + ), +// Reset : 0, Enable : 1 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc020008c, + 0x80000000, + (0x1 << 31) + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c new file mode 100644 index 0000000000..c5eb8a1dc0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbUra.h" +#include "GnbUraToken.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBURAKB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbUraGetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +VOID +GnbUraSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +VOID +GnbUraStreamSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to Device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] Value Pointer to Context + */ +VOID +GnbUraGetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 FieldMask; + UINT32 TargetAddress; + + RegValue = 0; + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + TargetAddress = Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType; + GnbLibPciIndirectRead ( TargetAddress, UraTokenInfo->RegAddress, Width, &RegValue, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura GET: RegDomainType = 0x%x IndirectAddress = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, RegValue); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + TargetAddress = UraTokenInfo->RegDomainType; + GnbRegisterReadKB (Device->GnbHandle, (UINT8)TargetAddress, UraTokenInfo->RegAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura GET: RegDomainType = %d, Address = 0x%08x, Value = 0x%08x\n", TargetAddress, UraTokenInfo->RegAddress, RegValue); + break; + + default: + ASSERT (FALSE); + return; + } + + if (UraTokenInfo->WholeRegAccess == TRUE) { + *(UINT32 *)Value = RegValue; + } else { + RegValue = RegValue >> UraTokenInfo->BfOffset; + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + *(UINT32 *)Value = RegValue & FieldMask; + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to Device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] Value Pointer to Context + */ +VOID +GnbUraSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 TargetValue; + UINT32 FieldMask; + UINT32 TempValue; + + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + FieldMask = 0; + TempValue = *(UINT32 *)Value; + + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + if (UraTokenInfo->WholeRegAccess == TRUE) { + TargetValue = TempValue; + } else { + GnbLibPciIndirectRead ( Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, Width, &RegValue, Device->StdHeader); + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + TargetValue = RegValue & (~(FieldMask << UraTokenInfo->BfOffset)); + TargetValue |= (TempValue & FieldMask) << UraTokenInfo->BfOffset; + } + GnbLibPciIndirectWrite ( Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, Width, &TargetValue, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura SET: RegDomainType = 0x%x IndirectAddress = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, TargetValue); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + if (UraTokenInfo->WholeRegAccess == TRUE) { + TargetValue = TempValue; + } else { + GnbRegisterReadKB (Device->GnbHandle, UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + TargetValue = RegValue & (~(FieldMask << UraTokenInfo->BfOffset)); + TargetValue |= (TempValue & FieldMask) << UraTokenInfo->BfOffset; + } + GnbRegisterWriteKB (Device->GnbHandle, UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, &TargetValue, UraTokenInfo->Flags, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura SET: RegDomainType = %d, Address = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, TargetValue); + break; + + default: + ASSERT (FALSE); + break; + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] UraTuple Pointer to structure URA_TUPLE + * @param[in] CombinedCount Token count + */ +VOID +GnbUraStreamSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 Index; + UINT32 StreamSetAddress; + UINT32 StepLength; + UINT32 TargetAddress; + + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + StreamSetAddress = UraTokenInfo->RegAddress; + StepLength = UraTuple->StepLength; + for (Index = 0; Index < CombinedCount; Index++) { + RegValue = *(((UINT32 *) ((UINTN)UraTuple->Value)) + Index); + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + TargetAddress = Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType; + //IDS_HDT_CONSOLE (NB_MISC, "0x%08x:0x%08x, \n", StreamSetAddress, RegValue); + GnbLibPciIndirectWrite (TargetAddress, StreamSetAddress, Width, &RegValue, Device->StdHeader); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + TargetAddress = UraTokenInfo->RegDomainType; + GnbRegisterWriteKB (Device->GnbHandle, (UINT8)TargetAddress, StreamSetAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + break; + + default: + ASSERT (FALSE); + return; + } + StreamSetAddress += StepLength; + } +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c new file mode 100644 index 0000000000..2d75fcee51 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbUra.h" +#include "GnbUraToken.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBURATOKENMAPKB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbUraLocateRegTblKB ( + IN DEV_OBJECT *Device, + IN OUT UINT32 *UraTableAddress + ); +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +REG_FIELD_TABLE_STRUCT UraTableKB = { + {0xC2100000, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuIntReq ,BfxSmuIntToggle)}, + {1, 16, FIELD_OFFSET(RxSmuIntReq ,BfxSmuServiceIndex)}, + {0xC2100004, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuIntSts ,BfxSmuIntAck)}, + {1, 1, FIELD_OFFSET(RxSmuIntSts ,BfxSmuIntDone)}, + {0xE0003088, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuAuthSts ,BfxSmuAuthDone)}, + {1, 1, FIELD_OFFSET(RxSmuAuthSts ,BfxSmuAuthPass)}, + {0xE00030A4, 0x4, 0}, + {16, 1, FIELD_OFFSET(RxSmuFwAuth ,BfxSmuProtectedMode)}, + {0xC0000004, 0x4, 0}, + {7, 1, FIELD_OFFSET(REG_FIELD_TABLE_STRUCT_fld11 ,BfxSmuBootSeqDone)}, + {0x3F800, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuFwFlags ,BfxSmuInterruptsEnabled)}, + {0x80000000, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuResetCntl ,BfxSmuRstReg)}, + {0x80000004, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuClkCntl ,BfxSmuCkDisable)}, + {0x80008000, 0x4, 0}, + {D0F0xBC_x20000_ADDRESS, D0F0xBC_x20000_TYPE, 0}, + {D0F0xBC_x0_ADDRESS, D0F0xBC_x0_TYPE, 0}, + {D0F0xBC_xC210003C_ADDRESS, D0F0xBC_xC210003C_TYPE, 0}, + +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method to locate register table. + * + * + * @param[in] Device Standard configuration header + * @param[in, out] UraTableAddress Ura register table address + */ +VOID +GnbUraLocateRegTblKB ( + IN DEV_OBJECT *Device, + IN OUT UINT32 *UraTableAddress + ) +{ + *UraTableAddress = (UINT32)((UINTN)(&UraTableKB)); + return; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c new file mode 100644 index 0000000000..5fd3cca0eb --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c @@ -0,0 +1,447 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieComplexDataKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIECOMPLEXDATAKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieGetComplexDataLengthKB ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieBuildComplexConfigurationKB ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +PcieGetNativePhyLaneBitmapKB ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); +// +// Complex configuration +// + +KB_COMPLEX_CONFIG ComplexDataKB = { + //Silicon + { + { + DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + 0, + 0, + offsetof (KB_COMPLEX_CONFIG, GppWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon) + }, + 0, + 0xFF, + 0xFF + }, + //Gpp Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER, + offsetof (KB_COMPLEX_CONFIG, GppWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon), + offsetof (KB_COMPLEX_CONFIG, DdiWrapper) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR4) - offsetof (KB_COMPLEX_CONFIG, GppWrapper) + }, + GPP_WRAP_ID, + GPP_NUMBER_OF_PIFs, + GPP_START_PHY_LANE, + GPP_END_PHY_LANE, + GPP_CORE_ID, + GPP_CORE_ID, + GPP_END_PHY_LANE - GPP_START_PHY_LANE + 1, + { + 1, + 1, + 1, + 1, + 1, + 1, + 1 + }, + }, + //Virtual DDI Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (KB_COMPLEX_CONFIG, DdiWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon), + 0, + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper) + }, + DDI_WRAP_ID, + 0, + DDI_START_PHY_LANE, + DDI_END_PHY_LANE, + -1, + 0, + 0, + { + 1, + 1, + 1, + 1, + 1, + 0, + 1 + }, + }, +//------------------------------ GPP WRAPPER START------------------------------------- + //Port PBR4 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR4) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR3) - offsetof (KB_COMPLEX_CONFIG, PortPBR4), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 7, + 7, + PBR4_NATIVE_PCI_DEV, + PBR4_NATIVE_PCI_FUN, + PBR4_CORE_ID, + PBR4_PORT_ID, + {(UINT32)PBR4_PCI_ADDRESS}, + LinkStateResetExit, + PBR4, + PBR4_UNIT_ID, + PBR4_NUM_UNIT_IDs + }, + }, + }, + //Port PBR3 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR3) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR2) - offsetof (KB_COMPLEX_CONFIG, PortPBR3), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 6, + 6, + PBR3_NATIVE_PCI_DEV, + PBR3_NATIVE_PCI_FUN, + PBR3_CORE_ID, + PBR3_PORT_ID, + {(UINT32)PBR3_PCI_ADDRESS}, + LinkStateResetExit, + PBR3, + PBR3_UNIT_ID, + PBR3_NUM_UNIT_IDs + }, + }, + }, + //Port PBR2 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR2) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR1) - offsetof (KB_COMPLEX_CONFIG, PortPBR2), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 5, + 5, + PBR2_NATIVE_PCI_DEV, + PBR2_NATIVE_PCI_FUN, + PBR2_CORE_ID, + PBR2_PORT_ID, + {(UINT32)PBR2_PCI_ADDRESS}, + LinkStateResetExit, + PBR2, + PBR2_UNIT_ID, + PBR2_NUM_UNIT_IDs + }, + }, + }, + //Port PBR1 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR1) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR0) - offsetof (KB_COMPLEX_CONFIG, PortPBR1), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 4, + 4, + PBR1_NATIVE_PCI_DEV, + PBR1_NATIVE_PCI_FUN, + PBR1_CORE_ID, + PBR1_PORT_ID, + {(UINT32)PBR1_PCI_ADDRESS}, + LinkStateResetExit, + PBR1, + PBR1_UNIT_ID, + PBR1_NUM_UNIT_IDs + }, + }, + }, + //Port PBR0 + { + { + DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (KB_COMPLEX_CONFIG, PortPBR0) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, PortPBR0), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 0, + 3, + PBR0_NATIVE_PCI_DEV, + PBR0_NATIVE_PCI_FUN, + PBR0_CORE_ID, + PBR0_PORT_ID, + {(UINT32)PBR0_PCI_ADDRESS}, + LinkStateResetExit, + PBR0, + PBR0_UNIT_ID, + PBR0_NUM_UNIT_IDs + }, + }, + }, +//------------------------------ GPP WRAPPER END ------------------------------------- +//------------------------------ DDI WRAPPER START---------------------------------- + //Ddi1 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + offsetof (KB_COMPLEX_CONFIG, Ddi2) - offsetof (KB_COMPLEX_CONFIG, Ddi1), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //Ddi2 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (KB_COMPLEX_CONFIG, Ddi2) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + offsetof (KB_COMPLEX_CONFIG, Vga) - offsetof (KB_COMPLEX_CONFIG, Ddi2), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //Vga + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (KB_COMPLEX_CONFIG, Vga) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + 0, + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + { + {0, 0, 0, 0, 0} + } +}; + +// +// PCIe lane allocation GPP +// +UINT8 ROMDATA GppPortLaneConfigurationTableKB [] = { + UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 4, 7, 0, 3, + UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, 4, 5, 0, 3, + UNUSED_LANE_ID, UNUSED_LANE_ID, 7, 7, 6, 6, 4, 5, 0, 3, + 7, 7, 6, 6, 5, 5, 4, 4, 0, 3 +}; + +// +// DDI lane allocation DDI +// +UINT8 ROMDATA DdiLaneConfigurationTableKB [] = { + 0, 3, 4, 7, 8, 11 +}; + +// +// PCIe lane allocation desfriptors +// +PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[] = { + { + 0, + GPP_WRAP_ID, + PciePortEngine, + NUMBER_OF_GPP_PORTS, + sizeof (GppPortLaneConfigurationTableKB) / (NUMBER_OF_GPP_PORTS * 2), + &GppPortLaneConfigurationTableKB[0] + }, + { + DESCRIPTOR_TERMINATE_LIST, + DDI_WRAP_ID, + PcieDdiEngine, + NUMBER_OF_DDI_DDIS, + sizeof (DdiLaneConfigurationTableKB) / (NUMBER_OF_DDI_DDIS * 2), + &DdiLaneConfigurationTableKB[0] + } +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get length of data block for complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieGetComplexDataLengthKB ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Length = sizeof (KB_COMPLEX_CONFIG); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieBuildComplexConfigurationKB ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (Buffer, &ComplexDataKB, sizeof (KB_COMPLEX_CONFIG), StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieGetNativePhyLaneBitmapKB ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + + return PhyLaneBitmap; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h new file mode 100644 index 0000000000..6663031ec4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIECOMPLEXDATAKB_H_ +#define _PCIECOMPLEXDATAKB_H_ + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + +#define NUMBER_OF_GPP_PORTS 5 +#define NUMBER_OF_DDI_DDIS 3 + +#define NON_INITIALIZED_PCI_ADDRESS 0 + +#define GPP_WRAP_ID 0 +#define GPP_START_PHY_LANE 0 +#define GPP_END_PHY_LANE 7 +#define GPP_CORE_ID 0 +#define GPP_NUMBER_OF_PIFs 1 + +#define DDI_WRAP_ID 3 +#define DDI_START_PHY_LANE 8 +#define DDI_END_PHY_LANE 19 +#define DDI_NUMBER_OF_PIFs 1 + +// PBR0 +#define PBR0 0 +#define PBR0_NATIVE_PCI_DEV 2 +#define PBR0_NATIVE_PCI_FUN 1 +#define PBR0_CORE_ID GPP_CORE_ID +#define PBR0_PORT_ID 0 +#define PBR0_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR0_UNIT_ID 0x4 +#define PBR0_NUM_UNIT_IDs 0x1 + +// PBR1 +#define PBR1 1 +#define PBR1_NATIVE_PCI_DEV 2 +#define PBR1_NATIVE_PCI_FUN 2 +#define PBR1_CORE_ID GPP_CORE_ID +#define PBR1_PORT_ID 1 +#define PBR1_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR1_UNIT_ID 0x5 +#define PBR1_NUM_UNIT_IDs 0x1 + +// PBR2 +#define PBR2 2 +#define PBR2_NATIVE_PCI_DEV 2 +#define PBR2_NATIVE_PCI_FUN 3 +#define PBR2_CORE_ID GPP_CORE_ID +#define PBR2_PORT_ID 2 +#define PBR2_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR2_UNIT_ID 0x6 +#define PBR2_NUM_UNIT_IDs 0x1 + +// PBR3 +#define PBR3 3 +#define PBR3_NATIVE_PCI_DEV 2 +#define PBR3_NATIVE_PCI_FUN 4 +#define PBR3_CORE_ID GPP_CORE_ID +#define PBR3_PORT_ID 3 +#define PBR3_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR3_UNIT_ID 0x7 +#define PBR3_NUM_UNIT_IDs 0x1 + +// PBR4 +#define PBR4 4 +#define PBR4_NATIVE_PCI_DEV 2 +#define PBR4_NATIVE_PCI_FUN 5 +#define PBR4_CORE_ID GPP_CORE_ID +#define PBR4_PORT_ID 4 +#define PBR4_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR4_UNIT_ID 0x8 +#define PBR4_NUM_UNIT_IDs 0x1 + +#define MaxDevNum 4 +#define MaxDevFunc 5 + +#define GPP_CORE_x4x4 ((4ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2 ((2ull << 16) | (2ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1 ((1ull << 24) | (1ull << 16) | (2ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) + +///Family specific silicon configuration +typedef struct { + UINT8 PortDevMap [5]; ///< Device number that has beed allocated already +} KB_PCIe_SILICON_CONFIG; + + +/// Complex Configuration for silicon module +typedef struct { + PCIe_SILICON_CONFIG Silicon; ///< Silicon + + PCIe_WRAPPER_CONFIG GppWrapper; ///< GPP Wrapper + PCIe_WRAPPER_CONFIG DdiWrapper; ///< DDI Wrapper + + // GPP + PCIe_ENGINE_CONFIG PortPBR4; ///< Port PBR6 + PCIe_ENGINE_CONFIG PortPBR3; ///< Port PBR5 + PCIe_ENGINE_CONFIG PortPBR2; ///< Port PBR4 + PCIe_ENGINE_CONFIG PortPBR1; ///< Port PBR3 + PCIe_ENGINE_CONFIG PortPBR0; ///< Port PBR2 + + // DDI + PCIe_ENGINE_CONFIG Ddi1; ///< Ddi1 + PCIe_ENGINE_CONFIG Ddi2; ///< Ddi2 + PCIe_ENGINE_CONFIG Vga; ///< Vga + KB_PCIe_SILICON_CONFIG FmSilicon; ///< Fm silicon config +} KB_COMPLEX_CONFIG; + + +VOID +PcieSetPortPciAddressMapKB ( + IN PCIe_SILICON_CONFIG *Silicon + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c new file mode 100644 index 0000000000..bc87ddef3d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c @@ -0,0 +1,626 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe wrapper configuration services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "PcieComplexDataKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIECONFIGKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define DEVFUNC(d, f) ((((UINT8) d) << 3) | ((UINT8) f)) + +extern PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8* +PcieDebugGetCoreConfigurationStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringKB ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieMapPortPciAddressKB ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8* +PcieDebugGetWrapperNameStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +AGESA_STATUS +PcieConfigureEnginesLaneAllocationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieGetCoreConfigurationValueKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieCheckPortPciDeviceMappingKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieGetSbConfigInfoKB ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// +// Default port dev map +// +UINT8 ROMDATA DefaultPortDevMap [] = { + DEVFUNC (2, 1), + DEVFUNC (2, 2), + DEVFUNC (2, 3), + DEVFUNC (2, 4), + DEVFUNC (2, 5) +}; + +// +// Default apic config +// +APIC_DEVICE_INFO ROMDATA DefaultIoapicConfig [] = { + {0, 0, 0x18}, + {1, 0, 0x19}, + {2, 0, 0x1A}, + {3, 0, 0x1B}, + {4, 0, 0x18} +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] PcieLaneConfig Lane configuration descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +STATIC AGESA_STATUS +PcieConfigurePcieEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_LANE_ALLOC_DESCRIPTOR *PcieLaneConfig, + IN UINT8 ConfigurationId + ) +{ + UINT8 CoreLaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + + if (ConfigurationId >= PcieLaneConfig->NumberOfConfigurations) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = ConfigurationId * PcieLaneConfig->NumberOfEngines * 2; + + while (EnginesList != NULL) { + if (PcieLibIsPcieEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = PcieLaneConfig->ConfigTable[CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = PcieLaneConfig->ConfigTable[CoreLaneIndex++]; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] DdiLaneConfig Lane configuration descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +STATIC AGESA_STATUS +PcieConfigureDdiEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_LANE_ALLOC_DESCRIPTOR *DdiLaneConfig, + IN UINT8 ConfigurationId + ) +{ + UINTN LaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId >= DdiLaneConfig->NumberOfConfigurations) { + return AGESA_ERROR; + } + LaneIndex = ConfigurationId * DdiLaneConfig->NumberOfEngines * 2; + EnginesList = PcieConfigGetChildEngine (Wrapper); + while (EnginesList != NULL) { + if (PcieLibIsDdiEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieConfigureEnginesLaneAllocationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + PCIe_LANE_ALLOC_DESCRIPTOR *LaneConfigDescriptor; + + Status = AGESA_ERROR; + LaneConfigDescriptor = PcieLaneAllocConfigurationKB; + while (LaneConfigDescriptor != NULL) { + if (LaneConfigDescriptor->WrapId == Wrapper->WrapId && LaneConfigDescriptor->EngineType == EngineType) { + switch (EngineType) { + case PciePortEngine: + Status = PcieConfigurePcieEnginesLaneAllocation (Wrapper, LaneConfigDescriptor, ConfigurationId); + break; + case PcieDdiEngine: + Status = PcieConfigureDdiEnginesLaneAllocation (Wrapper, LaneConfigDescriptor, ConfigurationId); + break; + default: + ASSERT (FALSE); + } + break; + } + LaneConfigDescriptor = PcieConfigGetNextDataDescriptor (LaneConfigDescriptor); + } + return Status; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieGetCoreConfigurationValueKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + switch (ConfigurationSignature) { + case GPP_CORE_x4x1x1x1x1: + *ConfigurationValue = 0x4; + break; + case GPP_CORE_x4x2x1x1: + *ConfigurationValue = 0x3; + break; + case GPP_CORE_x4x2x2: + *ConfigurationValue = 0x2; + break; + case GPP_CORE_x4x4: + *ConfigurationValue = 0x1; + break; + default: + IDS_HDT_CONSOLE (PCIE_MISC, "ERROR!!![%s Wrapper] Unknown core config signature 0x%08x%08x\n", + PcieDebugGetWrapperNameStringKB (Wrapper), + ((UINT32 *) &ConfigurationSignature)[1], + ((UINT32 *) &ConfigurationSignature)[0] + ); + ASSERT (FALSE); + Status = AGESA_ERROR; + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMappingKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 DevFunc; + UINT8 Index; + DevFunc = DEVFUNC (PortDescriptor->Port.DeviceNumber, PortDescriptor->Port.FunctionNumber); + if (DevFunc == 0) { + return TRUE; + } + for (Index = 0; Index < (sizeof (DefaultPortDevMap) / sizeof (DefaultPortDevMap[0])); Index++) { + if (DefaultPortDevMap[Index] == DevFunc) { + return TRUE; + } + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieDebugGetCoreConfigurationStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + switch (ConfigurationValue) { + case 0x4: + return "4:1:1:1:1"; + case 0x3: + return "4:2:1:1"; + case 0x2: + return "4:2:2"; + case 0x1: + return "4:4"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieDebugGetWrapperNameStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + return "GPP"; + case DDI_WRAP_ID: + return "Virtual DDI"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringKB ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + switch (AddressFrame) { + case 0x130: + return "GPP WRAP"; + case 0x110: + return "GPP PIF0"; + case 0x120: + return "GPP PHY0"; + case 0x140: + return "GPP CORE"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 NormalizedLoPhyLane; + BOOLEAN Result; + + Result = FALSE; + Wrapper = PcieConfigGetParentWrapper (Engine); + DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; + + if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { + Result = TRUE; + } else { + if (NormalizedLoPhyLane == 0) { + Result = TRUE; + } else { + if ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0) { + Result = TRUE; + } + } + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieMapPortPciAddressKB ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + KB_COMPLEX_CONFIG *ComplexConfig; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + UINT8 DevFunc; + UINT8 Index; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressKB Enter\n"); + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { + Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; + Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; + } + ComplexConfig = (KB_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Engine); + IDS_OPTION_HOOK (IDS_GNB_PCIE_PORT_REMAP, &Engine->Type.Port, GnbLibGetHeader (Pcie)); + DevFunc = (Engine->Type.Port.PortData.DeviceNumber << 3) | Engine->Type.Port.PortData.FunctionNumber; + for (Index = 0; Index < sizeof (ComplexConfig->FmSilicon.PortDevMap); ++Index) { + if (ComplexConfig->FmSilicon.PortDevMap[Index] == DevFunc) { + Status = AGESA_ERROR; + break; + } + } + if (Status == AGESA_SUCCESS) { + ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.PcieBridgeId] = DevFunc; + } + for (Index = 0; Index < sizeof (DefaultPortDevMap); ++Index) { + if (DevFunc == DefaultPortDevMap[Index]) { + Engine->Type.Port.LogicalBridgeId = Index; + // Get the configuration from the table or from "auto settings" + if (Engine->Type.Port.PortData.ApicDeviceInfo.GroupMap == 0x00) { + // If Group is 0, use "Auto" settings + Engine->Type.Port.PortData.ApicDeviceInfo = DefaultIoapicConfig[Index]; + } + break; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressKB Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * @param[in] Silicon Silicon config descriptor + */ + +VOID +PcieSetPortPciAddressMapKB ( + IN PCIe_SILICON_CONFIG *Silicon + ) +{ + UINT8 Index; + UINT8 DevFuncIndex; + UINT8 PortDevMap [sizeof (DefaultPortDevMap)]; + PCIe_PLATFORM_CONFIG *Pcie; + D0F0x64_x30_STRUCT D0F0x64_x30; + + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Silicon->Header); + LibAmdMemCopy (&PortDevMap[0], &DefaultPortDevMap[0], sizeof (DefaultPortDevMap), GnbLibGetHeader (Pcie)); + for (Index = 0; Index < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) { + if (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] != 0) { + for (DevFuncIndex = 0; DevFuncIndex < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) { + if (PortDevMap[DevFuncIndex] == ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index]) { + PortDevMap[DevFuncIndex] = 0; + break; + } + } + } + } + for (Index = 0; Index < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) { + if (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] == 0) { + for (DevFuncIndex = 0; DevFuncIndex < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) { + if (PortDevMap[DevFuncIndex] != 0) { + ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] = PortDevMap[DevFuncIndex]; + PortDevMap[DevFuncIndex] = 0; + break; + } + } + } + GnbRegisterReadKB ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x30.Field.DevFnMap = ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index]; + GnbRegisterWriteKB ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build default SB configuration descriptor + * + * + * @param[in] SocketId Socket Id + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieGetSbConfigInfoKB ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_UNSUPPORTED; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c new file mode 100644 index 0000000000..2199796fd8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c @@ -0,0 +1,938 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87701 $ @e \$Date: 2013-02-07 12:58:51 -0600 (Thu, 07 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbUra.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "PcieLibKB.h" +#include "PcieComplexDataKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "OptionGnb.h" +#include "GnbSmuInitLibV7.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEEARLYINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Set port device/function mapping + * + * + * + * @param[in] Descriptor Silicon descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePortMapInitCallbackKB ( + IN PCIe_DESCRIPTOR_HEADER *Descriptor, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieSetPortPciAddressMapKB ((PCIe_SILICON_CONFIG *) Descriptor); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Static init for various registers. + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyStaticInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + + for (Index = 0; Index < PcieInitEarlyTableKB.Length; Index++) { + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS), + PcieInitEarlyTableKB.Table[Index].Reg, + AccessS3SaveWidth32, + (UINT32)~PcieInitEarlyTableKB.Table[Index].Mask, + PcieInitEarlyTableKB.Table[Index].Data, + GnbLibGetHeader (Pcie) + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init core registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyCoreInitKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + UINTN Index; + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitKB Enter\n"); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + for (Index = 0; Index < CoreInitTableKB.Length; Index++) { + UINT32 Value; + Value = PcieRegisterRead ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableKB.Table[Index].Reg), + Pcie + ); + Value &= (~CoreInitTableKB.Table[Index].Mask); + Value |= CoreInitTableKB.Table[Index].Data; + PcieRegisterWrite ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableKB.Table[Index].Reg), + Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitKB Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Pcie Phy Isolation + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +STATIC +PciePhyIsolationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 ActiveLaneBitmap; + UINT32 PhyRxIsoDis; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + UINT32 D0F0xE4_WRAP_8021; + UINT32 D0F0xE4_WRAP_8022; + UINT32 D0F0xE4_WRAP_8025; + UINT32 D0F0xE4_WRAP_8026; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Enter\n"); + + // Apply lane mux + D0F0xE4_WRAP_8021 = 0x07060504; + D0F0xE4_WRAP_8022 = 0x03020100; + D0F0xE4_WRAP_8025 = 0x07060504; + D0F0xE4_WRAP_8026 = 0x03020100; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), + D0F0xE4_WRAP_8021, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), + D0F0xE4_WRAP_8022, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8026_ADDRESS), + D0F0xE4_WRAP_8026, + FALSE, + Pcie + ); + + PhyRxIsoDis = GnbBuildOptions.CfgPciePhyIsolationEnable ? 0 : 3; + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, Wrapper); + if ((ActiveLaneBitmap & 0xF0) != 0) { + PhyRxIsoDis = 3; + } + + IDS_OPTION_HOOK (IDS_GNB_PCIE_PHY_ISOLATION, &PhyRxIsoDis, GnbLibGetHeader (Pcie)); + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = 3; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Exit\n"); +} + +UINT8 LaneMuxSelectorArrayKB[] = { 7, 6, 5, 4, 3, 2, 1, 0 }; + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate mux array index + * + * + * + * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array + * @param[in] LaneMuxValue The value that match to array + * @retval Index Index successfully mapped + */ +STATIC UINT8 +PcieTopologyLocateMuxIndexKB ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ) +{ + UINT8 Index; + for (Index = 0; Index < sizeof (LaneMuxSelectorArrayKB); Index++ ) { + if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply lane mux + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC VOID +PcieTopologyApplyLaneMuxKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Index; + UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayKB)]; + UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayKB)]; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxKB Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + LibAmdMemCopy ( + &TxLaneMuxSelectorArray[0], + &LaneMuxSelectorArrayKB[0], + sizeof (LaneMuxSelectorArrayKB), + GnbLibGetHeader (Pcie) + ); + LibAmdMemCopy ( + &RxLaneMuxSelectorArray[0], + &LaneMuxSelectorArrayKB[0], + sizeof (LaneMuxSelectorArrayKB), + GnbLibGetHeader (Pcie) + ); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + UINT32 CoreLaneBitmap; + UINT32 PifLaneBitmap; + UINT8 CurrentCoreLane; + UINT8 CurrentPifLane; + + CoreLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, EngineList); + PifLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList); + + while (CoreLaneBitmap != 0) { + CurrentCoreLane = LibAmdBitScanForward (CoreLaneBitmap); + CurrentPifLane = LibAmdBitScanForward (PifLaneBitmap); + + if (TxLaneMuxSelectorArray[CurrentPifLane] != CurrentCoreLane) { + TxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexKB (TxLaneMuxSelectorArray, CurrentCoreLane)] = TxLaneMuxSelectorArray[CurrentPifLane]; + TxLaneMuxSelectorArray[CurrentPifLane] = CurrentCoreLane; + } + + if (RxLaneMuxSelectorArray[CurrentCoreLane] != CurrentPifLane) { + RxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexKB (RxLaneMuxSelectorArray, CurrentPifLane)] = RxLaneMuxSelectorArray[CurrentCoreLane]; + RxLaneMuxSelectorArray[CurrentCoreLane] = CurrentPifLane; + } + + CoreLaneBitmap &= (~ (1 << CurrentCoreLane)); + PifLaneBitmap &= (~ (1 << CurrentPifLane)); + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + for (Index = 0; Index < 2; ++Index) { + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS + Index), + ((UINT32 *) TxLaneMuxSelectorArray) [Index], + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS + Index), + ((UINT32 *) RxLaneMuxSelectorArray) [Index], + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC VOID +PcieTopologyExecuteReconfigKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + PCIe_SILICON_CONFIG *Silicon; + DEV_OBJECT DevObject; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigKB Enter\n"); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x2; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + Silicon = PcieConfigGetParentSilicon (Wrapper); + + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xB8_ADDRESS, + 0x3f81c, + AccessWidth32, + (UINT32) ~0xff00, + Wrapper->WrapId << 8, + GnbLibGetHeader (Pcie) + ); + + DevObject.StdHeader = GnbLibGetHeader (Pcie); + DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); + DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue; + GnbSmuServiceRequestV7 ( + &DevObject, + 25, //SMC_MSG_RECONFIGURE, + 0, + 0 + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigKB Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply Misc settings for given wrapper + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ +STATIC VOID +PcieMiscInitKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; + GnbRegistersKB4915_STRUCT GnbRegistersKB4915; + GnbRegistersKB4940_STRUCT GnbRegistersKB4940; + GnbRegistersKB4965_STRUCT GnbRegistersKB4965; + GnbRegistersKB4990_STRUCT GnbRegistersKB4990; + GnbRegistersKB5015_STRUCT GnbRegistersKB5015; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMiscInitKB Enter\n"); + D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8011.Field.Bitfield_23_23 = 0; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011.Value, + TRUE, + Pcie + ); + + GnbRegistersKB4915.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x805), + Pcie + ); + + GnbRegistersKB4940.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x905), + Pcie + ); + + GnbRegistersKB4965.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0A05), + Pcie + ); + GnbRegistersKB4990.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0B05), + Pcie + ); + + GnbRegistersKB5015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0C05), + Pcie + ); + + GnbRegistersKB4915.Field.bit_31_24 = 0x40; + GnbRegistersKB4940.Field.bit_31_24 = 0x40; + GnbRegistersKB4965.Field.bit_31_24 = 0x40; + GnbRegistersKB4990.Field.bit_31_24 = 0x40; + GnbRegistersKB5015.Field.bit_31_24 = 0x40; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x805), + GnbRegistersKB4915.Value, + TRUE, + Pcie + ); + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x905), + GnbRegistersKB4940.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0A05), + GnbRegistersKB4965.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0B05), + GnbRegistersKB4990.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0C05), + GnbRegistersKB5015.Value, + TRUE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMiscInitKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Switch to PCIe Native Gen1 PLL. + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieNativeGen1PLLSwitchKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + UINT32 ParamValue; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieNativeGen1PLLSwitchKB Enter\n"); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + ParamValue = 0; + if (GlobalSpeedCap == PcieGen1) { + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, 87, &ParamValue, 0, GnbLibGetHeader (Pcie)); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieNativeGen1PLLSwitchKB Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieEarlyInitCallbackKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN CoreConfigChanged; + BOOLEAN PllConfigChanged; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackKB Enter\n"); + CoreConfigChanged = FALSE; + PllConfigChanged = FALSE; + IDS_OPTION_HOOK (IDS_BEFORE_RECONFIGURATION, Pcie, GnbLibGetHeader (Pcie)); + PcieTopologyPrepareForReconfig (Wrapper, Pcie); + Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); + ASSERT (Status == AGESA_SUCCESS); + PciePhyIsolationKB (Wrapper, Pcie); + PcieTopologyApplyLaneMuxKB (Wrapper, Pcie); + PciePifSetRxDetectPowerMode (Wrapper, Pcie); + PciePifSetLs2ExitTimeV5 (Wrapper, Pcie); + PciePifApplyGanging (Wrapper, Pcie); + PcieTopologySelectMasterPllKB (Wrapper, &PllConfigChanged, Pcie); + PcieMiscInitKB (Wrapper, Pcie); + PcieTopologyExecuteReconfigKB (Wrapper, Pcie); + PcieTopologyCleanUpReconfig (Wrapper, Pcie); + PcieTopologySetLinkReversalV4 (Wrapper, Pcie); + PciePifPllConfigureKB (Wrapper, Pcie); + PcieTopologyLaneControlV5 ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), + Wrapper, + Pcie + ); + + PciePollPifForCompeletion (Wrapper, Pcie); + PcieEarlyCoreInitKB (Wrapper, Pcie); + PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackKB Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieEarlyInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + BOOLEAN NativeGen1PLL; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + NativeGen1PLL = GnbBuildOptions.CfgNativeGen1PLL; + + Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, PciePortMapInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_OPTION_HOOK (IDS_GNB_PMM_NATIVEGEN1PLL, &NativeGen1PLL, GnbLibGetHeader (Pcie)); + + if (NativeGen1PLL == TRUE) { + Status = PcieNativeGen1PLLSwitchKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieEarlyStaticInitKB (Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitKB Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set misc slot capability + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieLinkSetSlotCapKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 IntPin; + PCIe_WRAPPER_CONFIG *Wrapper; + + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, + AccessWidth32, + 0xffffffff, + 1 << DxF0x58_SlotImplemented_OFFSET, + GnbLibGetHeader (Pcie) + ); + + if (Engine->Type.Port.Address.Address.Function < 5) { + IntPin = Engine->Type.Port.Address.Address.Function; + } else { + IntPin = Engine->Type.Port.Address.Address.Function - 4; + } + + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, + AccessWidth32, + 0xffffffff, + IntPin << DxF0x3C_IntPin_OFFSET, + GnbLibGetHeader (Pcie) + ); + + // Set MaxPayload straps for port + if (Engine->EngineData.StartLane == Engine->EngineData.EndLane) { + IDS_HDT_CONSOLE (GNB_TRACE, "Set MaxPayload strap for StartLane = %d and EndLane = %d\n", Engine->EngineData.StartLane, Engine->EngineData.EndLane); + Wrapper = PcieConfigGetParentWrapper (Engine); + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x804 + (Engine->Type.Port.PortId) * 0x100), + 0xe, + MAX_PAYLOAD_256 << 1, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieEarlyPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackKB Enter\n"); + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + PciePortProgramRegisterTable (PortInitEarlyTableKB.Table, PortInitEarlyTableKB.Length, Engine, FALSE, Pcie); + PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); + PcieSetLinkWidthCap (Engine, Pcie); + PcieCompletionTimeout (Engine, Pcie); + PcieLinkSetSlotCapKB (Engine, Pcie); + PcieLinkInitHotplugV5 (Engine, Pcie); + PciePhyChannelCharacteristicV5 (Engine, Pcie); + if (Engine->Type.Port.PortData.PortPresent == PortDisabled || + (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && + Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && + Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { + ASSERT (!PcieConfigIsSbPcieEngine (Engine)); + // + // Pass endpoint status in scratch + // + PciePortRegisterRMW ( + Engine, + 0x1, + 0x1, + 0x1, + FALSE, + Pcie + ); + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + if (PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +DdiEarlyPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 GMMx6464; + UINT32 GMMx5C6C; + UINT32 GMMx5C90; + + IDS_HDT_CONSOLE (GNB_TRACE, "DdiEarlyPortInitCallbackKB Enter\n"); + if ((Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDpToLvds) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvdsSwInit)) { + + IDS_HDT_CONSOLE (GNB_TRACE, "Found eDP/LVDS Connector\n"); + + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x6464, &GMMx6464, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c90, &GMMx5C90, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c6c, &GMMx5C6C, 0, GnbLibGetHeader (Pcie)); + GMMx6464 |= 1; + GMMx6464 |= 1 << 4; + GMMx6464 |= 1 << 25; + GMMx5C90 &= ~0x3f00; GMMx5C90 |= 1 << 8; + GMMx5C6C &= ~0x1800; GMMx5C6C |= 1 << 13; + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x6464, &GMMx6464, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c90, &GMMx5C90, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c6c, &GMMx5C6C, 0, GnbLibGetHeader (Pcie)); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "DdiEarlyPortInitCallbackKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +STATIC +PcieEarlyPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieEarlyPortInitCallbackKB, + NULL, + Pcie + ); + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + DdiEarlyPortInitCallbackKB, + NULL, + Pcie + ); + + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PcieEarlyInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieEarlyPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c new file mode 100644 index 0000000000..9656f26d9e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe env post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Env Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreKBS3Script_ID, 0, NULL); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c new file mode 100644 index 0000000000..61b07250a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c @@ -0,0 +1,463 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB specific PCIe services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87645 $ @e \$Date: 2013-02-06 13:08:17 -0600 (Wed, 06 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "PcieComplexDataKB.h" +#include "PcieLibKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbF1Table.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIELIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapKB ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +GnbTimeStampKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +PcieMaxPayloadKB ( + IN PCIe_ENGINE_CONFIG *Engine + ); +/*----------------------------------------------------------------------------------------*/ +/** + * PLL powerdown + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllConfigureKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureKB Enter\n"); + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0; + + if (Wrapper->Features.PowerOffUnusedPlls != 0) { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + } else { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0; + } + + if (Wrapper->Features.PllOffInL1 != 0) { + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; + } else { + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; + } + + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + 1), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes and plls + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrPowerDownUnusedLanesKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 UnusedLanes; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanesKB Enter\n"); + if (Wrapper->Features.PowerOffUnusedLanes != 0) { + UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); + PcieTopologyLaneControlV5 ( + DisableLanes, + UnusedLanes, + Wrapper, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanesKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request boot up voltage + * + * + * + * @param[in] LinkCap Global GEN capability + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +PcieSetVoltageKB ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 TargetVid; + UINT8 MinVidIndex; + UINT8 PP_FUSE_ARRAY_V2_fld32[5]; + UINT8 Index; + PP_F1_ARRAY_V2 *PpF1Array; + UINT32 Millivolt; + UINT32 D0F0xBC_xC0104007; + UINT32 D0F0xBC_xC0104008; + UINT32 D0F0xBC_xC010407C; + UINT32 D0F0xBC_xC0107064; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageKB Enter\n"); + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, GnbLibGetHeader (Pcie)); + if (PpF1Array == NULL) { + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0104007, &D0F0xBC_xC0104007, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0104008, &D0F0xBC_xC0104008, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC010407C, &D0F0xBC_xC010407C, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0107064, &D0F0xBC_xC0107064, 0, GnbLibGetHeader (Pcie)); + PP_FUSE_ARRAY_V2_fld32[0] = (UINT8) ((D0F0xBC_xC0104007 >> 5) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[1] = (UINT8) ((D0F0xBC_xC0104008 >> 5) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[2] = (UINT8) ((D0F0xBC_xC0104008 >> 13) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[3] = (UINT8) ((D0F0xBC_xC0104008 >> 21) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[4] = (UINT8) ((D0F0xBC_xC010407C >> 20) & 0xFF); + Index = (UINT8) ((D0F0xBC_xC0107064 >> 11) & 7); + } else { + PP_FUSE_ARRAY_V2_fld32[0] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[0]; + PP_FUSE_ARRAY_V2_fld32[1] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[1]; + PP_FUSE_ARRAY_V2_fld32[2] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[2]; + PP_FUSE_ARRAY_V2_fld32[3] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[3]; + PP_FUSE_ARRAY_V2_fld32[4] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[4]; + Index = PpF1Array->PcieGen2Vid; + } + if (LinkCap > PcieGen1) { + ASSERT (PP_FUSE_ARRAY_V2_fld32[Index] != 0); + TargetVid = PP_FUSE_ARRAY_V2_fld32[Index]; + } else { + + MinVidIndex = 0; + for (Index = 0; Index < 5; Index++) { + if (PP_FUSE_ARRAY_V2_fld32[Index] > PP_FUSE_ARRAY_V2_fld32[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (PP_FUSE_ARRAY_V2_fld32[MinVidIndex] != 0); + TargetVid = PP_FUSE_ARRAY_V2_fld32[MinVidIndex]; + } + + IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid); + Millivolt = GnbTranslateVidCodeToMillivoltV5 (TargetVid, GnbLibGetHeader (Pcie)) * 4 / 100; + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, SMC_MSG_VDDNB_REQUEST, &Millivolt, 0, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL power up latency + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + * @retval Pll wake up latency in us + */ +UINT8 +PciePifGetPllPowerUpLatencyKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return 35; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapKB ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIe_WRAPPER_CONFIG *Wrapper; + PCIe_PLATFORM_CONFIG *Pcie; + + Wrapper = PcieConfigGetParentWrapper (Engine); + Pcie = PcieConfigGetPlatform (Wrapper); + + LinkSpeedCapability = PcieGen2; + + if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { + Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; + } + if (Pcie->PsppPolicy == PsppPowerSaving) { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { + LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; + } + if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { + + if (( Pcie->PsppPolicy == PsppBalanceLow || + Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) + && !PcieConfigIsSbPcieEngine (Engine)) { + + LinkSpeedCapability = PcieGen1; + } + } + return LinkSpeedCapability; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family specific time stamp function + * + * + * @param[in] StdHeader Standard configuration header + * @retval Count + */ +UINT32 +GnbTimeStampKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TimeStamp; + + TimeStamp = 0; + + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xE0), + 0x13080F0, + AccessWidth32, + &TimeStamp, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTsKb: %08x\n", TimeStamp); + return TimeStamp; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Limit MaxPayload to 256 for x1 ports + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @retval MaxPayload MaxPayloadSupport + */ +UINT8 +PcieMaxPayloadKB ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 MaxPayload; + + MaxPayload = MAX_PAYLOAD_512; + if (Engine->EngineData.StartLane == Engine->EngineData.EndLane) { + MaxPayload = MAX_PAYLOAD_256; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadKB Exit with MaxPayload = %d for StartLane = %d and EndLane = %d\n", MaxPayload, Engine->EngineData.StartLane, Engine->EngineData.EndLane); + return MaxPayload; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Select master PLL + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologySelectMasterPllKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT16 MasterLane; + UINT16 MasterHotplugLane; + UINT16 EngineMasterLane; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); + MasterLane = 0xFFFF; + MasterHotplugLane = 0xFFFF; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) { + EngineMasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); + if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + MasterHotplugLane = (EngineMasterLane < MasterHotplugLane) ? EngineMasterLane : MasterHotplugLane; + } else { + MasterLane = (EngineMasterLane < MasterLane) ? EngineMasterLane : MasterLane; + if (PcieConfigIsSbPcieEngine (EngineList)) { + break; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + if (MasterLane == 0xffff) { + if (MasterHotplugLane != 0xffff) { + MasterLane = MasterHotplugLane; + } else { + MasterLane = 0x0; + } + } + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value; + + if (MasterLane <= 3 ) { + Wrapper->MasterPll = GNB_PCIE_MASTERPLL_A; + } else { + Wrapper->MasterPll = GNB_PCIE_MASTERPLL_B; + } + + IDS_OPTION_HOOK (IDS_GNB_PCIE_MASTERPLL_SELECTION, &(Wrapper->MasterPll), GnbLibGetHeader (Pcie)); + + if (Wrapper->MasterPll == GNB_PCIE_MASTERPLL_A) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + } else { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; + } + + if (ConfigChanged != NULL) { + *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h new file mode 100644 index 0000000000..0434b7886e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84519 $ @e \$Date: 2012-12-17 11:20:40 -0600 (Mon, 17 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIELIBKB_H_ +#define _PCIELIBKB_H_ + +VOID +PciePifPllConfigureKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrPowerDownUnusedLanesKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetVoltageKB ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PciePifGetPllPowerUpLatencyKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySelectMasterPllKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c new file mode 100644 index 0000000000..ef076477ea --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c @@ -0,0 +1,392 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88079 $ @e \$Date: 2013-02-15 15:28:53 -0600 (Fri, 15 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "GnbFamServices.h" +#include "PcieLibKB.h" +#include "PciePortServicesV4.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMidPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortProgramRegisterTable (PortInitMidTableKB.Table, PortInitMidTableKB.Length, Engine, TRUE, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PcieEnableSlotPowerLimitV5 (Engine, Pcie); + } + // If StartLane == 4/7 and EndLane == 7/4, this is GFX port + if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) || + ((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) { + // For GPP ports only set STRAP_MED_yTSx_COUNT=2 + PciePortRegisterRMW ( + Engine, + 0xC0, + 0x30, + 0x2 << 4, + TRUE, + Pcie + ); + } + PcieEnableAspm (Engine, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieMidPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + Status = AGESA_SUCCESS; + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMidPortInitCallbackKB, + NULL, + Pcie + ); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageKB (GlobalSpeedCap, Pcie); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Clock gating + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC VOID +PciePwrClockGatingKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; + D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; + D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; + D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; + D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; + UINT8 CoreId; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingKB Enter\n"); + D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + Pcie + ); + + if (Wrapper->Features.ClkGating == 0x1) { + D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0; + D0F0xE4_WRAP_8011.Field.Reserved_16_16 = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkPermStop = 0; + D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0; + D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; + + D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0; + + D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; + + } + + if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; + } + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + D0F0xE4_WRAP_8014.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + D0F0xE4_WRAP_8015.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + D0F0xE4_WRAP_8012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011.Value, + TRUE, + Pcie + ); + + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), + D0F0xE4_CORE_0011_DynClkLatency_OFFSET, + D0F0xE4_CORE_0011_DynClkLatency_WIDTH, + 0xf, + TRUE, + Pcie + ); + } + + if (Wrapper->Features.LclkGating == 0x1) { + D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; + D0F0xE4_WRAP_8016.Field.LclkDynGateLatency = 0x3F; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016.Value, + TRUE, + Pcie + ); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Late Init. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieMidInitCallbackKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePwrPowerDownUnusedLanesKB (Wrapper, Pcie); + PciePwrClockGatingKB (Wrapper, Pcie); + PcieLockRegisters (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Late Init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieMidInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PcieMidPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieMidInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c new file mode 100644 index 0000000000..77fb825982 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c @@ -0,0 +1,470 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "PcieLibKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePostEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreInitKBS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostS3PortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_LINK_TRAINING_STATE State; + + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + + if (!PcieConfigIsSbPcieEngine (Engine)) { + // + // General Port + // + State = LinkStateDeviceNotPresent; + if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { + // + // Non hotplug device: we only check status from previous boot + // + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + State = LinkStateResetExit; + } + } else { + UINT32 PcieScratch; + // + // Get endpoint staus from scratch + // + PcieScratch = PciePortRegisterRead (Engine, 0x1, Pcie); + // + // Hotplug device: we check ep status if reported + // + if ((PcieScratch & 0x1) == 0) { + State = LinkStateResetExit; + } + } + // + // For compliance we always leave link in enabled state + // + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { + State = LinkStateResetExit; + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + // + // SB port + // + State = LinkStateTrainingSuccess; + } + PcieTrainingSetPortState (Engine, State, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostEarlyPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostPortInitCallbackKB, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostS3PortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostS3PortInitCallbackKB, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PciePostInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageKB (GlobalSpeedCap, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + IDS_OPTION_HOOK (IDS_BEFORE_GPP_TRAINING, Pcie, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostEarlyPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePostPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +STATIC AGESA_STATUS +PciePostS3InterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePostS3PortInitKB (Pcie); + } else { + Status = PciePostPortInitKB (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe S3 restore + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context Context pointer (not used) + */ +VOID +PcieLateRestoreInitKBS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + PciePostS3InterfaceKB (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c new file mode 100644 index 0000000000..10f882808a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe init tables. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85361 $ @e \$Date: 2013-01-07 11:15:28 -0600 (Mon, 07 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbRegistersKB.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { + { + PHY_SPACE (0, 0, D0F0xE4_PHY_4440_ADDRESS), + D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK, + 0x2 << D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_4450_ADDRESS), + D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_MASK | + D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_MASK, + (0x0 << D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_OFFSET) | (0x90 << D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_OFFSET) + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_0004_ADDRESS), + D0F0xE4_PHY_0004_CfgIdleDetTh_MASK, + 0x0 << D0F0xE4_PHY_0004_CfgIdleDetTh_OFFSET + } + }; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB = { + &PcieInitEarlyTable[0], + sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + +STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { + { + D0F0xE4_CORE_0020_ADDRESS, + D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | + D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, + (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) + }, + { + D0F0xE4_CORE_0010_ADDRESS, + D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK, + (0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET) + }, + { + D0F0xE4_CORE_001C_ADDRESS, + D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | + D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | + D0F0xE4_CORE_001C_TxArbMstLimit_MASK, + (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) + }, + { + D0F0xE4_CORE_0040_ADDRESS, + D0F0xE4_CORE_0040_PElecIdleMode_MASK, + (0x1 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) + }, + { + D0F0xE4_CORE_0002_ADDRESS, + D0F0xE4_CORE_0002_HwDebug_0_MASK, + (0x1 << D0F0xE4_CORE_0002_HwDebug_0_OFFSET) + }, + { + D0F0xE4_CORE_00C1_ADDRESS, + D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | + D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, + (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | + (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) + }, + { + D0F0xE4_CORE_00B0_ADDRESS, + D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | + D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, + (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) | (0x0 << D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET) + } +}; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB = { + &CoreInitTable[0], + sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { + { + DxFxxE4_x70_ADDRESS, + DxFxxE4_x70_RxRcbCplTimeoutMode_MASK, + (0x1 << DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET) + }, + { + DxFxxE4_xA0_ADDRESS, + DxFxxE4_xA0_Lc16xClearTxPipe_MASK | DxFxxE4_xA0_LcL1ImmediateAck_MASK | DxFxxE4_xA0_LcL0sInactivity_MASK, + (0x1 << DxFxxE4_xA0_Lc16xClearTxPipe_OFFSET) | + (0x1 << DxFxxE4_xA0_LcL1ImmediateAck_OFFSET) | + (0x6 << DxFxxE4_xA0_LcL0sInactivity_OFFSET) + }, + { + DxFxxE4_xA1_ADDRESS, + DxFxxE4_xA1_LcDontGotoL0sifL1Armed_MASK, + (0x1 << DxFxxE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) + }, + { + DxFxxE4_xA2_ADDRESS, + DxFxxE4_xA2_LcRenegotiateEn_MASK | DxFxxE4_xA2_LcUpconfigureSupport_MASK, + (0x1 << DxFxxE4_xA2_LcRenegotiateEn_OFFSET) | + (0x1 << DxFxxE4_xA2_LcUpconfigureSupport_OFFSET) + }, + { + DxFxxE4_xA3_ADDRESS, + DxFxxE4_xA3_LcXmitFtsBeforeRecovery_MASK, + (0x1 << DxFxxE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) + }, + { + DxFxxE4_xB1_ADDRESS, + DxFxxE4_xB1_LcElecIdleMode_MASK | + DxFxxE4_xB1_LcDeassertRxEnInL0s_MASK | + DxFxxE4_xB1_LcBlockElIdleinL0_MASK, + (0x1 << DxFxxE4_xB1_LcElecIdleMode_OFFSET) | + (0x1 << DxFxxE4_xB1_LcDeassertRxEnInL0s_OFFSET) | + (0x1 << DxFxxE4_xB1_LcBlockElIdleinL0_OFFSET) + }, + { + 0xC0, + 0x70000, + (0x1 << 16) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB = { + &PortInitEarlyTable[0], + sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { + { + DxFxxE4_xA2_ADDRESS, + DxFxxE4_xA2_LcDynLanesPwrState_MASK, + (0x3 << DxFxxE4_xA2_LcDynLanesPwrState_OFFSET) + }, + { + DxFxxE4_x6A_ADDRESS, + DxFxxE4_x6A_ErrReportingDis_MASK, + (0x1 << DxFxxE4_x6A_ErrReportingDis_OFFSET) + }, +// { +// 0xC0, +// DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, +// (0x1 << DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) +// } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB = { + &PortInitMidTable[0], + sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h new file mode 100644 index 0000000000..1d9fc9fe5c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SCS Binary + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85201 $ @e \$Date: 2013-01-03 14:13:50 -0600 (Thu, 03 Jan 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _EXCEL925_H_ +#define _EXCEL925_H_ + +UINT8 excel925[] = { + 0x21, 0x53, 0x43, 0x53, 0x4B, 0x41, 0x42, 0x49, 0x4E, 0x49, 0x20, 0x20, 0x56, 0x30, 0x2E, 0x30, + 0x2E, 0x30, 0x2E, 0x31, 0x1 , 0x00, 0x00, 0x4 , 0x00, 0x3 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x16, 0x2 , 0x1 , 0xA5, 0xF7, 0x2D, 0x83, 0x4E, 0xC3, 0xC3, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, 0xCA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xB8, 0x59, 0x00, 0x00, 0x92, 0x00, 0x96, 0xB8, 0x00, 0xC3, 0x00, 0xB5, 0x54, 0xB4, 0x8B, 0x62, + 0xB5, 0x00, 0xC4, 0xC1, 0x00, 0xA6, 0x55, 0x00, 0x00, 0xC7, 0x00, 0x38, 0x3C, 0x71, 0x4C, 0xB0, + 0x00, 0x00, 0xB7, 0xC4, 0x00, 0xB5, 0x86, 0xA4, 0x00, 0xC4, 0x00, 0x9B, 0xCB, 0x9D, 0x85, 0xC2, + 0xFF, 0x86, 0xD4, 0xC0, 0x00, 0x00, 0xB0, 0xBD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x3 , 0x1 , 0xC7, 0x50, 0x7A, 0x3F, + 0x4A, 0xBE, 0x9E, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, + 0x00, 0x91, 0x00, 0x70, 0x00, 0x00, 0x98, 0x98, 0x9F, 0x9F, 0x00, 0x00, 0x43, 0x43, 0x43, 0x43, + 0x97, 0x00, 0xB4, 0x00, 0x00, 0x00, 0xAE, 0x00, 0x00, 0x00, 0x9E, 0x93, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x00, 0xA5, 0xA5, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA2, 0xA2, 0xA2, 0x00, 0x90, 0xDA, 0x96, + 0x8D, 0x8D, 0x8D, 0x8D, 0x90, 0x00, 0xFF, 0x00, 0xE6, 0x00, 0xDA, 0x4E, 0x00, 0x89, 0x89, 0x00, + 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x99, 0xA9, 0x91, 0x98, 0xC9, 0x00, 0x00, + 0x00, 0x16, 0x4 , 0x1 , 0xCC, 0xBF, 0x86, 0xAD, 0x43, 0x3A, 0x9D, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0xB2, + 0x7E, 0x7E, 0x00, 0x00, 0x97, 0x97, 0x97, 0x97, 0xA0, 0x00, 0xBE, 0x00, 0x00, 0x00, 0xBA, 0x00, + 0x00, 0x00, 0x9D, 0x57, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xA8, 0xA8, 0x00, 0x00, 0x4 , 0x4 , + 0xAB, 0xAB, 0xAB, 0xAB, 0x00, 0x00, 0xDE, 0x00, 0x75, 0x75, 0x75, 0x75, 0x64, 0x91, 0xFF, 0x00, + 0xE0, 0xE4, 0x95, 0x00, 0x00, 0x80, 0x80, 0xE9, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x95, 0xA5, 0xB5, 0xDE, 0x00, 0xB9, 0xCF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +#endif // _EXCEL925_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c new file mode 100644 index 0000000000..3a7c6ac8b2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB IOAPIC Initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#include "GnbRegistersCommonV2.h" +#define FILECODE PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbNbIoapicInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init IOAPIC on GNB port + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +IoapicInitCallbackV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCI_ADDR GnbPciAddress; + D0F0xFC_x10_STRUCT D0F0xFC_x10; + + GnbPciAddress = GnbGetHostPciAddress ((GNB_HANDLE *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header)); + D0F0xFC_x10.Value = 0x0; + + // Bounds check values - make sure the value is small enough to fit the field size + ASSERT (Engine->Type.Port.PortData.ApicDeviceInfo.GroupMap < (1 << D0F0xFC_x10_BrExtIntrGrp_WIDTH)); + ASSERT (Engine->Type.Port.PortData.ApicDeviceInfo.Swizzle < (1 << D0F0xFC_x10_BrExtIntrSwz_WIDTH)); + ASSERT (Engine->Type.Port.PortData.ApicDeviceInfo.BridgeInt < (1 << D0F0xFC_x10_BrIntIntrMap_WIDTH)); + + // Get the configuration from the PCIe_PORT_DATA APIC_DEVICE_INFO struct + D0F0xFC_x10.Field.BrExtIntrGrp = Engine->Type.Port.PortData.ApicDeviceInfo.GroupMap; + D0F0xFC_x10.Field.BrExtIntrSwz = Engine->Type.Port.PortData.ApicDeviceInfo.Swizzle; + D0F0xFC_x10.Field.BrIntIntrMap = Engine->Type.Port.PortData.ApicDeviceInfo.BridgeInt; + + // Write the register + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x10_ADDRESS + Engine->Type.Port.LogicalBridgeId, + AccessS3SaveWidth32, + &D0F0xFC_x10.Value, + GnbLibGetHeader (Pcie) + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to Enable IOAPIC on GNB + * + * + * + * @param[in] Descriptor Silicon descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + */ +STATIC AGESA_STATUS +IoapicEnableCallbackV5 ( + IN PCIe_DESCRIPTOR_HEADER *Descriptor, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCI_ADDR GnbPciAddress; + D0F0xFC_x00_STRUCT D0F0xFC_x00; + UINT32 *AddressPtr; + UINT32 AddressLow; + UINT32 AddressHigh; + + D0F0xFC_x00.Value = 0x0; + D0F0xFC_x00.Field.IoapicEnable = 1; + // Set the extended ID enable (default) + D0F0xFC_x00.Field.IoapicIdExtEn = 1; + // Enable SB feature for every APIC. ACPI OS may disable this once the OS boots + D0F0xFC_x00.Field.IoapicSbFeatureEn = 1; + AddressPtr = (UINT32*) Buffer; + AddressLow = AddressPtr[0] & 0xFFFFFF00; + AddressHigh = AddressPtr[1]; + // Get the PCI address of the GNB + GnbPciAddress = GnbGetHostPciAddress (GnbGetHandle (GnbLibGetHeader (Pcie))); + // If the BLDCFG base address is null, assume that the base address of the APIC has already been programmed + // If base address is defined in BLDCFG, program it here + if ((AddressLow != 0) || (AddressHigh != 0)) { + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x01_ADDRESS, + AccessS3SaveWidth32, + &AddressLow, + GnbLibGetHeader (Pcie) + ); + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x02_ADDRESS, + AccessS3SaveWidth32, + &AddressHigh, + GnbLibGetHeader (Pcie) + ); + } + // Enable the IOAPIC. + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x00_ADDRESS, + AccessS3SaveWidth32, + &D0F0xFC_x00.Value, + GnbLibGetHeader (Pcie) + ); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB IOAPIC + * + * + * + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbNbIoapicInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_MID_PARAMS *MidParamsPtr; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + UINT64 GnbNbIoapicAddress; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + MidParamsPtr = (AMD_MID_PARAMS *) StdHeader; + GnbNbIoapicAddress = MidParamsPtr->GnbMidConfiguration.GnbIoapicAddress; + // For each ENGINE, configure the group, swizzle, and pin per APIC_DEVICE_INFO + PcieConfigRunProcForAllEngines (DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, IoapicInitCallbackV5, NULL, Pcie); + + // For each GNB, configure the IOAPIC Enable, ID Size, and SB Feature Enable + Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, IoapicEnableCallbackV5, &GnbNbIoapicAddress, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Exit\n"); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h new file mode 100644 index 0000000000..42956570b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h @@ -0,0 +1,99 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV1_H_ +#define _GNBNBINITLIBV1_H_ + + +AGESA_STATUS +GnbSetTom ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPrevention ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbOrbDynamicWake ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLock ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +UINT8 +GnbLocateLowestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateLowestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c new file mode 100644 index 0000000000..b26679bb49 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -0,0 +1,386 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersCommonV2.h" +#include "heapManager.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define SMC_RAM_START_ADDR 0x10000ul + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GNB_TOPOLOGY_INFO *TopologyInfo; +} GNB_TOPOLOGY_INFO_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbSmuServiceRequestV4S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Check a PCIE device to see if it supports phantom functions + * + * @param[in] Device Device pci address + * @param[in] StdHeader Standard configuration header + * @return TRUE Current device supports phantom functions + */ +STATIC BOOLEAN +GnbCheckPhantomFuncSupport ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + Value = 0; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader); + } + return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status + */ + +SCAN_STATUS +STATIC +GnbTopologyInfoScanCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + GNB_TOPOLOGY_INFO_DATA *GnbTopologyInfo; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " GnbIommuInfoScanCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + GnbTopologyInfo = (GNB_TOPOLOGY_INFO_DATA *)ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + break; + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDevicePcieToPcix: + GnbTopologyInfo->TopologyInfo->PcieToPciexBridge = TRUE; + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + if (GnbCheckPhantomFuncSupport (Device, ScanData->StdHeader)) { + GnbTopologyInfo->TopologyInfo->PhantomFunction = TRUE; + } + ScanStatus = SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU topology info + * + * + * + * @param[in] StartPciAddress Start PCI address + * @param[in] EndPciAddress End PCI address + * @param[in] TopologyInfo Topology info structure + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_TOPOLOGY_INFO_DATA GnbTopologyInfo; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Enter\n"); + GnbTopologyInfo.ScanData.GnbScanCallback = GnbTopologyInfoScanCallback; + GnbTopologyInfo.ScanData.StdHeader = StdHeader; + GnbTopologyInfo.TopologyInfo = TopologyInfo; + GnbLibPciScan (StartPciAddress, EndPciAddress, &GnbTopologyInfo.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Exit\n"); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware download + * + * + * @param[in] GnbPciAddress GNB Pci Address + * @param[in] Firmware Pointer tp firmware + * @param[in] StdHeader Standard configuration header + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU PCI address + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR GnbIommuPciAddress; + GnbIommuPciAddress = GnbGetHostPciAddress (GnbHandle); + GnbIommuPciAddress.Address.Function = 0x2; + return GnbIommuPciAddress; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Value; + + Value = 0; + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_ENGINE, &GnbHandle->Header); + while (EngineList != NULL) { + if (EngineList->Type.Port.NumberOfUnitId != 0) { + if (!PcieConfigIsActivePcieEngine (EngineList)) { + Value |= (((1 << EngineList->Type.Port.NumberOfUnitId) - 1) << EngineList->Type.Port.UnitId); + } else { + if (EngineList->Type.Port.NumberOfUnitId > 1) { + Value |= (((1 << (EngineList->Type.Port.NumberOfUnitId - 1)) - 1) << (EngineList->Type.Port.UnitId + 1)); + } + } + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } + // Set GNB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x3A_ADDRESS, + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); + //Set UNB + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, GnbHandle->NodeId + 0x18, 0, D18F0x110_ADDRESS + GnbHandle->LinkId * 4), + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Config GNB to prevent LPC deadlock scenario + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_ENGINE_CONFIG *EngineList; + + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &GnbHandle->Header); + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &GnbHandle->Header); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && PcieConfigIsSbPcieEngine (EngineList)) { + PcieRegisterRMW ( + PcieConfigGetParentWrapper (EngineList), + CORE_SPACE (EngineList->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_UmiNpMemWrite_MASK, + 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, + TRUE, + Pcie + ); + //Enable special NP memory write protocol in ORB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x06_ADDRESS, + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, + StdHeader + ); + break; + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable IOMMU base address. (MMIO space ) + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT16 CapabilityOffset; + UINT64 BaseAddress; + UINT32 Value; + PCI_ADDR GnbIommuPciAddress; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Enter\n"); + + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + GnbIommuPciAddress = GnbGetIommuPciAddressV4 (GnbHandle, StdHeader); + CapabilityOffset = GnbLibFindPciCapability (GnbIommuPciAddress.AddressValue, IOMMU_CAP_ID, StdHeader); + + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessWidth32, &Value, StdHeader); + BaseAddress = (UINT64) Value << 32; + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessWidth32, &Value, StdHeader); + BaseAddress |= Value; + + if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); + } else { + ASSERT (FALSE); + Status = AGESA_ERROR; + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n"); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h new file mode 100644 index 0000000000..522a42e665 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV4_H_ +#define _GNBNBINITLIBV4_H_ + +#pragma pack (push, 1) + +/// Firmware header +typedef struct { + UINT32 Version; ///< Version + UINT32 HeaderLength; ///< Header length + UINT32 FirmwareLength; ///< Firmware length + UINT32 EntryPoint; ///< Entry point + UINT32 MessageDigest[5]; ///< Message digest + UINT32 Reserved_A[3]; ///< Reserved + UINT32 CurrentSystemState; ///< Current system state + UINT32 DpmCacHistory; ///< DpmCac History + UINT32 DpmResidencyCounters; ///< DPM recidency counters + UINT32 Reserved_B[16]; ///< Reserved + UINT32 Reserved_C[16]; ///< Reserved + UINT32 Reserved_D[16]; ///< Reserved + UINT32 HeaderEnd; ///< Header end signature +} FIRMWARE_HEADER_V4; + +/// SMU service request contect +typedef struct { + PCI_ADDR GnbPciAddress; ///< PCIe address of GNB + UINT8 RequestId; ///< Request/Msg ID +} SMU_MSG_CONTEXT; + +#pragma pack (pop) + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbSmuServiceRequestV4 ( + IN PCI_ADDR GnbPciAddress, + IN UINT8 RequestId, + IN UINT32 AccessFlags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbSmuFirmwareLoadV4 ( + IN PCI_ADDR GnbPciAddress, + IN FIRMWARE_HEADER_V4 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c new file mode 100644 index 0000000000..516739aa3c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c @@ -0,0 +1,348 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#include "GnbRegistersCommonV2.h" +#include "GnbF1Table.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbSetTomV5 ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +UINT8 +GnbLocateLowestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GnbTranslateVidCodeToMillivoltV5 ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidIndexV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB set top of memory + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbSetTomV5 ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT64 MsrData; + UINT64 GnbTom2; + UINT64 GnbTom3; + UINT32 Value; + + Status = AGESA_SUCCESS; + //Read memory size below 4G from MSR C001_001A + LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader); + //Write to NB register 0x90 + Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 + GnbLibPciRMW ( + NbPciAddress.AddressValue | D0F0x90_ADDRESS, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + if (Value == 0) { + Status = AGESA_WARNING; + } + + GnbTom2 = 0; + GnbTom3 = 0; + LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); + if ((MsrData & BIT21) != 0) { + //If SYS_CFG(MtrrTom2En) then configure GNB TOM2 and TOM3 + //Read memory size above 4G from TOP_MEM2 (MSR C001_001D) + LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader); + if ((MsrData & (UINT64)0x0000FFFFFFC00000) > ((UINT64)0x0000010000000000)) { + // If TOP_MEM2 is above 1TB, enable GNB TOM2 and TOM3 + // Set TOM2 for below 1TB limit + GnbTom2 = 0x000000FD00000000; + // TOM3 is INCLUSIVE, so set it to TOM - 1 using bits 47:22 + GnbTom3 = (MsrData - 1) & (UINT64)0x0000FFFFFFC00000; + } else { + // If TOP_MEM2 is below 1TB, set TOM2 using bits 39:22 + GnbTom2 = MsrData & (UINT64)0x000000FFFFC00000; //Keep bits 39:22 + // If TOP_MEM2 is below 1TB, disable GNB TOM3 + GnbTom3 = 0; + } + } + + if (GnbTom2 != 0) { + // Write memory size[39:32] to indirect register 1A[7:0] + Value = (UINT32) ((GnbTom2 >> 32) & 0xFF); + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0xFFFFFF00, + Value, + StdHeader + ); + // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0 + Value = (UINT32)GnbTom2 & 0xFF800000; //Keep bits 31:23 + Value |= BIT0; // Enable top of memory + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + } + + if (GnbTom3 != 0) { + // Above 1TB addressing TOM3 if MSR TOM is above 1TB + // Write memory size[47:22] to indirect register 4E[25:0] and enable memory through bit 31 + Value = (UINT32) (GnbTom3 >> 22); + Value |= BIT31; + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + 0x4e | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0x83FFFFFF, + Value, + StdHeader + ); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of highest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +UINT8 +GnbLocateHighestVidIndexV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVid; + UINT8 MaxVidIndex; + UINTN Index; + PP_F1_ARRAY_V2 *PpF1Array; + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + ASSERT (PpF1Array != NULL); + if (PpF1Array == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MaxVidIndex = 0; + MaxVid = 0xff; + for (Index = 0; Index < 5; Index++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index] != 0 && PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index] < MaxVid) { + MaxVid = PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index]; + MaxVidIndex = (UINT8) Index; + } + } + ASSERT (PpF1Array->PP_FUSE_ARRAY_V2_fld32[MaxVidIndex] != 0); + return MaxVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of lowest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +STATIC UINT8 +GnbLocateLowestVidIndexV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + UINTN Index; + PP_F1_ARRAY_V2 *PpF1Array; + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + ASSERT (PpF1Array != NULL); + if (PpF1Array == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MinVidIndex = 0; + + for (Index = 0; Index < 5; Index++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index] > PpF1Array->PP_FUSE_ARRAY_V2_fld32[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (PpF1Array->PP_FUSE_ARRAY_V2_fld32[MinVidIndex] != 0); + return MinVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the highest SCLK VID (high voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateHighestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVidIndex; + PP_F1_ARRAY_V2 *PpF1Array; + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + ASSERT (PpF1Array != NULL); + + MaxVidIndex = GnbLocateHighestVidIndexV5 (StdHeader); + ASSERT (PpF1Array->PP_FUSE_ARRAY_V2_fld32[MaxVidIndex] != 0); + return PpF1Array->PP_FUSE_ARRAY_V2_fld32[MaxVidIndex]; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the lowest SCLK VID (low voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateLowestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + PP_F1_ARRAY_V2 *PpF1Array; + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + ASSERT (PpF1Array != NULL); + MinVidIndex = GnbLocateLowestVidIndexV5 (StdHeader); + ASSERT (PpF1Array->PP_FUSE_ARRAY_V2_fld32[MinVidIndex] != 0); + return PpF1Array->PP_FUSE_ARRAY_V2_fld32[MinVidIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Translate VID code to millivolt with two fraction bits + * + * + * @param[in] Vid VID code + * @param[in] StdHeader Standard configuration header + * @retval 100 millivolt with two fraction bits + */ + +UINT32 +GnbTranslateVidCodeToMillivoltV5 ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Millivolt; + + // According to SVI2 spec, Vid Code 0xF7 is 6.25mv. 6.25mv is one boundary value. + if (Vid > 0xF7) { + Vid = 0xF7; + ASSERT (FALSE); + } + + // Equation: VID code increase/decrease 1, there is one 6.25mv change. + // 6.25mv could be described using integer 625 with two fraction bits. + Millivolt = (0xF7 - Vid + 1) * 625; + + return Millivolt; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h new file mode 100644 index 0000000000..df1eaa9d3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV5_H_ +#define _GNBNBINITLIBV5_H_ + +AGESA_STATUS +GnbSetTomV5 ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidIndexV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +UINT8 +GnbLocateLowestVidIndexV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateLowestVidCodeV5 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GnbTranslateVidCodeToMillivoltV5 ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c new file mode 100644 index 0000000000..0fb763b33a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c @@ -0,0 +1,463 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87263 $ @e \$Date: 2013-01-31 09:18:06 -0600 (Thu, 31 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "OptionGnb.h" +#include "PcieAlibV2.h" +#include "GnbF1Table.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern F_ALIB_GET *AlibGetBaseTableV2; +extern F_ALIB_UPDATE *AlibDispatchTableV2[]; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +AGESA_STATUS +PcieAlibUpdateGnbData ( + IN OUT VOID *SsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +PcieAlibUpdatePciePortDataCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieAlibBuildAcpiTableV2 ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ); + +AGESA_STATUS +PcieAlibUpdateVoltageData ( + IN OUT VOID *DataBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieAlibUpdatePcieData ( + IN OUT VOID *DataBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create ACPI ALIB SSDT table + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAlibV2Feature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_LATE_PARAMS *LateParamsPtr; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + return PcieAlibBuildAcpiTableV2 (StdHeader, &LateParamsPtr->AcpiAlib); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +PcieAlibBuildAcpiTableV2 ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + VOID *AlibSsdtBuffer; + VOID *AlibSsdtTable; + UINTN AlibSsdtlength; + UINT32 AmlObjName; + VOID *AmlObjPtr; + + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Enter\n"); + AgesaStatus = AGESA_SUCCESS; + AlibSsdtTable = AlibGetBaseTableV2 (StdHeader); + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength; + if (*AlibSsdtPtr == NULL) { + AlibSsdtBuffer = GnbAllocateHeapBuffer ( + AMD_ACPI_ALIB_BUFFER_HANDLE, + AlibSsdtlength, + StdHeader + ); + ASSERT (AlibSsdtBuffer != NULL); + if (AlibSsdtBuffer == NULL) { + return AGESA_ERROR; + } + *AlibSsdtPtr = AlibSsdtBuffer; + } else { + AlibSsdtBuffer = *AlibSsdtPtr; + } + // Check length of port data + ASSERT (sizeof (_ALIB_PORT_DATA) <= 20); + // Check length of global data + ASSERT (sizeof (_ALIB_GLOBAL_DATA) <= 32); + // Copy template to buffer + LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader); + // Update table OEM fields. + LibAmdMemCopy ( + (VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemId, + (VOID *) &GnbBuildOptions.OemIdString, + sizeof (GnbBuildOptions.OemIdString), + StdHeader); + LibAmdMemCopy ( + (VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemTableId, + (VOID *) &GnbBuildOptions.OemTableIdString, + sizeof (GnbBuildOptions.OemTableIdString), + StdHeader); + // + // Update register base base + // + PcieAlibUpdateGnbData (AlibSsdtBuffer, StdHeader); + // + // Update transfer block + // + AmlObjName = STRING_TO_UINT32 ('A', 'D', 'A', 'T'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + if (AmlObjPtr != NULL) { + AmlObjPtr = (UINT8 *) AmlObjPtr + 10; + } + // Dispatch function from table + Index = 0; + while (AlibDispatchTableV2[Index] != NULL) { + Status = AlibDispatchTableV2[Index] (AmlObjPtr, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Index++; + } + if (AgesaStatus != AGESA_SUCCESS) { + //Shrink table length to size of the header + ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); + } + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] SsdtBuffer Pointer to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdateGnbData ( + IN OUT VOID *SsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + UINT32 AmlObjName; + VOID *AmlObjPtr; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateGnbData Enter\n"); + // + // Locate Base address variable + // + AmlObjName = STRING_TO_UINT32 ('A', 'G', 'R', 'B'); + AmlObjPtr = GnbLibFind ( + SsdtBuffer, + ((ACPI_TABLE_HEADER*) SsdtBuffer)->TableLength, + (UINT8*) &AmlObjName, + sizeof (AmlObjName) + ); + /// @todo + // ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr == NULL) { + return AGESA_ERROR; + } + // + // Update PCIe MMIO base + // + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32) (LocalMsrRegister & 0xFFFFF00000); + } else { + ASSERT (FALSE); + return AGESA_ERROR; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateGnbData Exit\n"); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] DataBuffer Pointer to data buffer + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdateVoltageData ( + IN OUT VOID *DataBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_F1_ARRAY_V2 *PpF1Array; + AGESA_STATUS Status; + ALIB_DATA *AlibData; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageData Enter\n"); + Status = AGESA_SUCCESS; + ASSERT (DataBuffer != NULL); + AlibData = (ALIB_DATA *) DataBuffer; + // + // Locate F1 table + // + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + ASSERT (PpF1Array != NULL); + if (PpF1Array != NULL) { + // + // Update GEN1 Vid + // + AlibData->Data.Data.PcieVidGen1 = PpF1Array->PP_FUSE_ARRAY_V2_fld32[0]; + // + // Update GEN2 Vid + // + AlibData->Data.Data.PcieVidGen2 = PpF1Array->PP_FUSE_ARRAY_V2_fld32[PpF1Array->PcieGen2Vid]; + // + // Update DPM Mask + // + AlibData->Data.Data.DpmMask = (PpF1Array->PP_FUSE_ARRAY_V2_fld37 + 1); + IDS_HDT_CONSOLE (GNB_TRACE, " DpmMask = %02x\n", AlibData->Data.Data.DpmMask); + // + // Update Boost data + // + AlibData->Data.Data.NumBoostStates = (PpF1Array->PP_FUSE_ARRAY_V2_fld36); + IDS_HDT_CONSOLE (GNB_TRACE, " NumBoost = %02x\n", AlibData->Data.Data.NumBoostStates); + } else { + Status = AGESA_ERROR; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageData Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Update PCIe info + * + * + * + * + * @param[in] DataBuffer Ponter to data buffer + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdatePcieData ( + IN OUT VOID *DataBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + AMD_LATE_PARAMS *LateParamsPtr; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Enter\n"); + ASSERT (DataBuffer != NULL); + Status = AGESA_SUCCESS; + // + // Locate PCIe platform config + // + if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { + // + // Update policy data + // + ((ALIB_DATA *) DataBuffer)->Data.Data.PsppPolicy = Pcie->PsppPolicy; + // + // Update data for each port + // + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_PCIE_ENGINE, + PcieAlibUpdatePciePortDataCallback, + DataBuffer, + Pcie + ); + } else { + ASSERT (FALSE); + Status = AGESA_FATAL; + } + + LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader; + ((ALIB_DATA *) DataBuffer)->Data.Data.DockedTdpHeadroom = + LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom; + IDS_HDT_CONSOLE (GNB_TRACE, " DockedTdpHeadroom = %02x\n", + LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to update PCIe port data + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibUpdatePciePortDataCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + _ALIB_PORT_DATA *PortData; + + PortData = &((ALIB_DATA *) Buffer)->PortData[Engine->Type.Port.PcieBridgeId].PortData; + + if (PcieConfigIsEngineAllocated (Engine) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) { + // + // Various speed capability + // + PortData->PciePortMaxSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); + PortData->PciePortCurSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PortData->PciePortDcSpeed = PcieGen1; + PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed; + if (Pcie->PsppPolicy == PsppBalanceLow) { + PortData->PciePortAcSpeed = PcieGen1; + } + if (PcieConfigIsSbPcieEngine (Engine)) { + PortData->PcieSbPort = 0x1; + PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed; + } + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode != 0) { + PortData->PcieLinkSafeMode = 0x1; + PortData->PcieLocalOverrideSpeed = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; + } + // + // various port capability + // + PortData->StartPhyLane = (UINT8) Engine->EngineData.StartLane; + PortData->EndPhyLane = (UINT8) Engine->EngineData.EndLane; + PortData->StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; + PortData->EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; + PortData->PortId = Engine->Type.Port.PortId; + PortData->LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; + PortData->PciDev = (UINT8) Engine->Type.Port.Address.Address.Device; + PortData->PciFun = (UINT8) Engine->Type.Port.Address.Address.Function; + } else { + PortData->PciePortMaxSpeed = PcieGen1; + PortData->PciePortCurSpeed = PcieGen1; + PortData->PciePortDcSpeed = PcieGen1; + PortData->PciePortAcSpeed = PcieGen1; + PortData->PcieLocalOverrideSpeed = PcieGen1; + } +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h new file mode 100644 index 0000000000..322d7c43c8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84514 $ @e \$Date: 2012-12-17 10:44:17 -0600 (Mon, 17 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBV2_H_ +#define _PCIEALIBV2_H_ + +#pragma pack (push, 1) + +/// _ALIB_PORT_DATA structure +typedef struct { + UINT8 PciePortMaxSpeed; ///< Maximum speed for PCIe Port + UINT8 PciePortAcSpeed; ///< AC power speed for PCIe Port + UINT8 PciePortDcSpeed; ///< DC power speed for PCIe Port + UINT8 PciePortCurSpeed; ///< Current speed for PCIe Port + UINT8 PcieSbPort; ///< Sb Port + UINT8 PcieLinkSafeMode; ///< Link Safe Mode + UINT8 PcieLocalOverrideSpeed; ///< Local Override Speed + UINT8 StartPhyLane; ///< Start PHY lane + UINT8 EndPhyLane; ///< End PHY lane + UINT8 StartCoreLane; ///< Start CORE lane + UINT8 EndCoreLane; ///< End Core lane + UINT8 PortId; ///< Logical Port ID + UINT8 LinkHotplug; ///< Hotplug Flags + UINT8 PciDev; ///< PCI Device Number + UINT8 PciFun; ///< PCI Function Number +} _ALIB_PORT_DATA; + +/// Set size for Port Data +typedef union { + _ALIB_PORT_DATA PortData; ///< Port data for ALIB + UINT8 Padding[20]; ///< Padding size +} ALIB_PORT_DATA; + +/// _ALIB_GLOBAL_DATA structure +typedef struct { + UINT8 PsppPolicy; ///< PSPP Policy + UINT8 PcieVidGen1; ///< VID for Gen1 + UINT8 PcieVidGen2; ///< VID for Gen2 + UINT8 PcieVidGen3; ///< VID for Gen3 + UINT8 DpmMask; ///< DPM Mask + UINT8 NumBoostStates; ///< DPM States + UINT8 DockedTdpHeadroom; ///< Docked TDP Headroom +} _ALIB_GLOBAL_DATA; + +/// Set size for Global Data +typedef union { + _ALIB_GLOBAL_DATA Data; ///< Global data struct for ALIB + UINT8 Padding[32]; ///< Padding size +} ALIB_GLOBAL_DATA; + +/// ALIB_GLOBAL_DATA structure +typedef struct { + ALIB_GLOBAL_DATA Data; ///< Global data struct for ALIB + ALIB_PORT_DATA PortData[12]; ///< Padding size +} ALIB_DATA; + + +#pragma pack (pop) + +AGESA_STATUS +PcieAlibV2Feature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c new file mode 100644 index 0000000000..22339890dc --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c @@ -0,0 +1,374 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "PcieAspmBlackList.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + PCIE_ASPM_TYPE Aspm; + PCI_ADDR DownstreamPort; + BOOLEAN AspmL0sBlackList; +} PCIE_ASPM_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +excel950_fun0 ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN OUT BOOLEAN *AspmL0sBlackList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCIE_ASPM_TYPE +excel950_fun1 ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +excel950_fun2 ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_ASPM_DATA PcieAspmData; + PcieAspmData.Aspm = Aspm; + PcieAspmData.ScanData.StdHeader = StdHeader; + PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback; + PcieAspmData.AspmL0sBlackList = FALSE; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData); +} + +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_ASPM_DATA *PcieAspmData; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieAspmData = (PCIE_ASPM_DATA *) ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + PcieAspmData->DownstreamPort = Device; + //PcieExitLatencyData->LinkCount++; + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + //PcieExitLatencyData->LinkCount--; + + //Pcie ASPM Black List for L0s with HW method change + if ((DeviceType == PcieDeviceRootComplex) && (PcieAspmData->AspmL0sBlackList == TRUE)) { + IDS_HDT_CONSOLE (GNB_TRACE, " Black List L0s disabled = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function); + GnbLibPciIndirectRMW (Device.AddressValue | 0xE0, 0xA0, AccessS3SaveWidth32, 0xfffff0ff, 0, ScanData->StdHeader); + } + break; + case PcieDeviceUpstreamPort: + excel950_fun0 ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + &PcieAspmData->AspmL0sBlackList, + ScanData->StdHeader + ); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + excel950_fun0 ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + &PcieAspmData->AspmL0sBlackList, + ScanData->StdHeader + ); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +VOID +excel950_fun4 ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , + AccessS3SaveWidth8, + (UINT32)~(BIT0 | BIT1), + Aspm, + StdHeader + ); + } +} + +STATIC VOID +excel950_fun5 ( + IN PCI_ADDR Device, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + excel950_fun4 (Device, Aspm, StdHeader); + } + } +} + +VOID +excel950_fun0 ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN OUT BOOLEAN *AspmL0sBlackList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_LINK_ASPM LinkAsmp; + PCIE_ASPM_TYPE DownstreamCap; + PCIE_ASPM_TYPE UpstreamCap; + LinkAsmp.DownstreamPort = Downstream; + DownstreamCap = excel950_fun1 (Downstream, StdHeader); + LinkAsmp.UpstreamPort = Upstream; + UpstreamCap = excel950_fun1 (Upstream, StdHeader); + LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1; + LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm; + LinkAsmp.RequestedAspm = Aspm; + if ((UpstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.UpstreamAspm |= AspmL0s; + } + if ((DownstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.DownstreamAspm |= AspmL0s; + } + if (GnbBuildOptions.PcieAspmBlackListEnable == 1) { + PcieAspmBlackListFeature (&LinkAsmp, StdHeader); + if ((LinkAsmp.DownstreamAspm & AspmL0s) == 0) { + *AspmL0sBlackList = LinkAsmp.BlackList; + } + } + //AgesaPcieLinkAspm (&LinkAsmp, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.UpstreamAspm) , + LinkAsmp.UpstreamPort.Address.Bus, + LinkAsmp.UpstreamPort.Address.Device, + LinkAsmp.UpstreamPort.Address.Function + ); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.DownstreamAspm) , + LinkAsmp.DownstreamPort.Address.Bus, + LinkAsmp.DownstreamPort.Address.Device, + LinkAsmp.DownstreamPort.Address.Function + ); + // Disable ASPM Upstream component + excel950_fun5 (Upstream, AspmDisabled, StdHeader); + // Enable ASPM Donstream component + excel950_fun4 (Downstream, LinkAsmp.DownstreamAspm, StdHeader); + // Enable ASPM Upstream component + excel950_fun5 (Upstream, LinkAsmp.UpstreamAspm, StdHeader); +} + + + +PCIE_ASPM_TYPE +excel950_fun1 ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return 0; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + return (Value >> 10) & 3; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAspmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + excel950_fun2 ( + Engine->Type.Port.Address, + Engine->Type.Port.PortData.LinkAspm, + GnbLibGetHeader (Pcie) + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAspmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h new file mode 100644 index 0000000000..1424a907c3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h @@ -0,0 +1,63 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPM_H_ +#define _PCIEASPM_H_ + +VOID +excel950_fun2 ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +excel950_fun4 ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c new file mode 100644 index 0000000000..64f01c0754 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c @@ -0,0 +1,326 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Clock Power Managment + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "PcieClkPm.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Clock Power Managment on function of the device + * + * + * + * @param[in] Function PCI address of function. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnFunction ( + IN PCI_ADDR Function, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), + AccessS3SaveWidth32, + (UINT32)~(BIT8), + BIT8, + StdHeader + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * check capability of intire device including its functions + * + * + * + * @param[in] Device PCI address of downstream port + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE - Device support Clock Power Managment + */ + /*----------------------------------------------------------------------------------------*/ +STATIC BOOLEAN +PcieClkPmCheckDeviceCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT8 MaxFunc; + UINT8 CurrentFunc; + UINT8 PcieCapPtr; + UINT32 Value; + + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return FALSE; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + if ((Value & BIT18) == 0) { + return FALSE; + } + } + } + return TRUE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Clock power managment on device + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnDevice ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) { + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable Clock Power Managment for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieClkPmEnableOnFunction (Device, StdHeader); + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +STATIC SCAN_STATUS +PcieClkPmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieClkPmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + break; + case PcieDeviceUpstreamPort: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Confiugure Clock Power Managment + * + * + * + * + * @param[in] DownstreamPort Downstream port PCI address + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +STATIC +PcieClkPmPortInitConfigure ( + IN PCI_ADDR DownstreamPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_PCI_SCAN_DATA ScanData; + ScanData.StdHeader = StdHeader; + ScanData.GnbScanCallback = PcieClkPmCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &ScanData); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieClkPmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PcieClkPmPortInitConfigure ( + Engine->Type.Port.Address, + GnbLibGetHeader (Pcie) + ); + } +} + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieClkPmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h new file mode 100644 index 0000000000..fe054f543a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIECLKPM_H_ +#define _PCIECLKPM_H_ + +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c new file mode 100644 index 0000000000..d498ad00e0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate/manes GNB/PCIe configuration + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB handle + * + * + * @param[in] StdHeader Standard configuration header + */ +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AGESA_STATUS Status; + GnbHandle = NULL; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + } + return GnbHandle; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB socket ID + * + * + * @param[in] GnbHandle Gnb handle + */ +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ) +{ + return PcieConfigGetParentComplex (GnbHandle)->SocketId; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Get PCI_ADDR of GNB + * + * + * @param[in] Handle Pointer to GNB_HANDLE + * @retval PCI_ADDR PCI_ADDR of device + */ + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ) +{ + ASSERT (Handle != NULL); + return Handle->Address; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h new file mode 100644 index 0000000000..8fc984764c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBHANDLELIB_H_ +#define _GNBHANDLELIB_H_ + + +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ); + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ); + + +#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY) + +#define GnbGetSiliconId(Handle) (Handle != NULL ? (Handle)->SiliconId : 0) +#define GnbGetNodeId(Handle) (Handle != NULL ? (Handle)->NodeId : 0) + +#define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE) + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h new file mode 100644 index 0000000000..d216c79c8b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h @@ -0,0 +1,54 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBPCIECONFIG_H_ +#define _GNBPCIECONFIG_H_ + +#include "GnbPcie.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "GnbHandleLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c new file mode 100644 index 0000000000..5a25844884 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -0,0 +1,533 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "OptionGnb.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" +#include "cpuServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#define PcieConfigAttachChild(P, C) (P)->Child = (UINT16) ((UINT8 *) C - (UINT8 *) P); +#define PcieConfigAttachParent(P, C) (C)->Parent = (UINT16) ((UINT8 *) C - (UINT8 *) P); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ); + +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_SILICON_CONFIG *Silicon; + UINT8 SocketId; + UINTN CurrentComplexesDataLength; + UINTN ComplexesDataLength; + UINT8 ComplexIndex; + VOID *Buffer; + ComplexesDataLength = 0; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + ComplexesDataLength += CurrentComplexesDataLength; + } + } + ComplexIndex = 0; + Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); + ASSERT (Pcie != NULL); + if (Pcie != NULL) { + PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); + Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Pcie->ComplexList[ComplexIndex].SocketId = SocketId; + //Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration + PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header); + //Attach Comples to Pcie + PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); + PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); + while (Silicon != NULL) { + PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header); + GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader); + GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader); + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + + if (ComplexIndex > 0) { + PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); + } + PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); + ComplexIndex++; + } + } + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParamsPtr; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + UINTN NumberOfComplexes; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Enter\n"); + AgesaStatus = AGESA_SUCCESS; + EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; + PcieComplexList = PcieConfigProcessUserConfig (EarlyParamsPtr->GnbConfig.PcieComplexList, StdHeader); + GNB_DEBUG_CODE ( + if (PcieComplexList != NULL) { + PcieUserConfigConfigDump (PcieComplexList); + } + ); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + while (Complex != NULL) { + for (Index = 0; Index < NumberOfComplexes; Index++) { + ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); + if (ComplexDescriptor->SocketId == Complex->SocketId) { + Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Complex = PcieLibGetNextDescriptor (Complex); + } + } + Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; + Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; + Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; + Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; + Pcie->GfxCardWorkaround = GfxWorkaroundEnable; + Pcie->TrainingExitState = LinkStateTrainingCompleted; + Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; + if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + Pcie->GfxCardWorkaround = GfxWorkaroundDisable; + } + Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); + GNB_DEBUG_CODE ( + PcieConfigDebugDump (Pcie); + ); + HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] PcieComplexList User PCIe topology configuration + * @param[out] StdHeader Standard configuration header + * @retval Updated topology configuration + */ +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Node0SocketId; + UINT32 Node0SiliconId; + UINTN NumberOfComplexes; + UINTN NumberOfPorts; + UINTN Index; + UINT16 DescriptorLoLane; + UINT16 DescriptorHiLane; + PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; + PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; + PCIe_PORT_DESCRIPTOR *SbPortDescriptor; + PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + AGESA_STATUS Status; + SbPortDescriptor = NULL; + GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); + Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); + if (Status == AGESA_UNSUPPORTED) { + return PcieComplexList; + } + if (PcieComplexList == NULL) { + // No complex descriptor for any silicon was provided + // 1. Create complex descriptor + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + } else { + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); + if (SbComplexDescriptor == NULL) { + // No complex descriptor for silicon that have SB attached. + // 1. Create complex descriptor. Will be first one in the list + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + LibAmdMemCopy ( + (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + + } else { + // Complex descriptor that represent silicon that have SB attached exist + // 1. Determine if complex have descriptor for SB + // 2. Create new descriptor for SB if needed + NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( + AMD_GNB_TEMP_DATA_HANDLE, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Copy complex descriptor array + LibAmdMemCopy ( + ResultComplexConfig, + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + if (NumberOfPorts != 0) { + // Copy port descriptor array associated with complex with SB attached + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + SbComplexDescriptor->PciePortList, + NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Update SB complex pointer on in memory list + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); + // Attach port descriptor array to complex + SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); + for (Index = 0; Index < NumberOfPorts; ++Index) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; + } + } + } + } + if (SbPortDescriptor == NULL) { + // No descriptor that represent SB where found, create new one, will be first one in list + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + // Copy default config info + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } else { + // Move SB descriptor to be first one in array + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + SbPortDescriptor, + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Disable original SB descriptor + SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; + //Update pointer to new SB descriptor + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + //It is no longer a descriptor that terminates list + SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } + } + } + // Mark descriptor as SB link + SbPortDescriptor->Port.MiscControls.SbLink = 0x1; + return ResultComplexConfig; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully located + * @retval AGESA_FATAL Configuration can not be located. + */ +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ) +{ + *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); + if (*Pcie == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Pcie)->StdHeader = (PVOID) StdHeader; + PcieUpdateConfigurationData (*Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attache descriptors + * + * + * @param[in] Type Descriptor type + * @param[in,out] Base Base descriptor + * @param[in,out] New New descriptor + */ +VOID +STATIC +PcieConfigAttachDescriptors ( + IN UINT32 Type, + IN OUT PCIe_DESCRIPTOR_HEADER *Base, + IN OUT PCIe_DESCRIPTOR_HEADER *New + ) +{ + PCIe_DESCRIPTOR_HEADER *Left; + PCIe_DESCRIPTOR_HEADER *Right; + + Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); + ASSERT (Left != NULL); + Right = PcieConfigGetChild (Type, New); + Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); + PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach configurations of two GNB to each other. + * + * Function will link all data structure to linked lists + * + * @param[in,out] Base Base complex descriptor + * @param[in,out] New New complex descriptor + */ +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ) +{ + // Connect Complex + Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); + PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); + // Connect Silicon + PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); + // Connect Wrappers + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); + // Connect Engines + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update configuration data + * + * Puprouse of this structure to update config data that base on programming of + * other silicon compoments. For instance PCI address of GNB and PCIe ports + * can change by AGESA or external agent + * + * + * @param[in,out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully update + * @retval AGESA_FATAL Failt to update configuration + */ +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + PCIe_ENGINE_CONFIG *Engine; + PCI_ADDR NewAddress; + // Update silicon configuration + Silicon = PcieConfigGetChildSilicon (Pcie); + while (Silicon != NULL) { + NewAddress = GnbFmGetPciAddress ((GNB_HANDLE *) PcieConfigGetParentComplex (Silicon), GnbLibGetHeader (Pcie)); + if (Silicon->Address.AddressValue != NewAddress.AddressValue) { + Silicon->Address.AddressValue = NewAddress.AddressValue; + Engine = PcieConfigGetChildEngine (Silicon); + while (Engine != NULL) { + if (PcieConfigIsPcieEngine (Engine)) { + Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); + } + } + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h new file mode 100644 index 0000000000..b38287c569 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h @@ -0,0 +1,57 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIECONFIGDATA_H_ +#define _PCIECONFIGDATA_H_ + + +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c new file mode 100644 index 0000000000..8e5e3dd43a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -0,0 +1,799 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * get Master Lane of PCIe port engine + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Master Engine Lane Number + */ +UINT8 +PcieConfigGetPcieEngineMasterLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 MasterLane; + PCIe_WRAPPER_CONFIG *Wrapper; + ASSERT (PcieConfigIsPcieEngine (Engine)); + + Wrapper = PcieConfigGetParentWrapper (Engine); + if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { + MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane); + } else { + MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane); + } + return MasterLane; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of core lanes + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Number of core lane + */ +UINT8 +PcieConfigGetNumberOfCoreLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { + return 0; + } + return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable engine + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +VOID +PcieConfigDisableEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (PcieConfigIsSbPcieEngine (Engine)) { + return; + } + PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable all engines on wrapper + * + * + * + * @param[in] EngineTypeMask Engine type bitmap. + * @param[in] Wrapper Pointer to wrapper config descriptor + */ +VOID +PcieConfigDisableAllEngines ( + IN UINTN EngineTypeMask, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { + PcieConfigDisableEngine (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get engine PHY lanes bitmap + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +UINT32 +PcieConfigGetEnginePhyLaneBitMap ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitMap; + LaneBitMap = 0; + if (PcieLibIsEngineAllocated (Engine)) { + LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); + } + return LaneBitMap; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of phy lanes + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @retval Number of Phy lane + */ +UINT8 +PcieConfigGetNumberOfPhyLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + return 0; + } + if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { + return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); + } else { + return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get port configuration signature for given wrapper and core + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] CoreId Core ID + * @retval Configuration Signature + */ +UINT64 +PcieConfigGetConfigurationSignature ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId + ) +{ + UINT64 ConfigurationSignature; + PCIe_ENGINE_CONFIG *EngineList; + ConfigurationSignature = 0; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) { + ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return ConfigurationSignature; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check Port Status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] PortStatus Check if status asserted for port + * @retval TRUE if status asserted + */ +BOOLEAN +PcieConfigCheckPortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT32 PortStatus + ) +{ + return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set/Reset port status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] SetStatus SetStatus + * @param[in] ResetStatus ResetStatus + * + */ +UINT16 +PcieConfigUpdatePortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_ENGINE_INIT_STATUS SetStatus, + IN PCIe_ENGINE_INIT_STATUS ResetStatus + ) +{ + Engine->InitStatus |= SetStatus; + Engine->InitStatus &= (~ResetStatus); + return Engine->InitStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all descriptor of specific type + * + * + * @param[in] InDescriptorFlags Include descriptor flags + * @param[in] OutDescriptorFlags Exlude descriptor flags + * @param[in] TerminationFlags Termination flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllDescriptors ( + IN UINT32 InDescriptorFlags, + IN UINT32 OutDescriptorFlags, + IN UINT32 TerminationFlags, + IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_DESCRIPTOR_HEADER *Descriptor; + + AgesaStatus = AGESA_SUCCESS; + Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); + while (Descriptor != NULL) { + if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { + Status = Callback (Descriptor, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); + } + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all wrappers in topology + * + * + * @param[in] DescriptorFlags Wrapper Flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllWrappers ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_WRAPPER_CONFIG *Wrapper; + + AgesaStatus = AGESA_SUCCESS; + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); + while (Wrapper != NULL) { + if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { + Status = Callback (Wrapper, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all engine in topology + * + * + * @param[in] DescriptorFlags Engine flags. + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieConfigRunProcForAllEngines ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + PCIe_ENGINE_CONFIG *Engine; + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); + while (Engine != NULL) { + if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { + if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { + Callback (Engine, Buffer, Pcie); + } + } + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get parent descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetParent ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Parent != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get child descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetChild ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Child != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get peer descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetPeer ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + ASSERT (Descriptor != NULL); + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Peer != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check is engine is active or potentially active + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval TRUE - engine active + * @retval FALSE - engine not active + */ +BOOLEAN +PcieConfigIsActivePcieEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + ASSERT (PcieConfigIsPcieEngine (Engine)); + Result = FALSE; + if (PcieConfigIsEngineAllocated (Engine)) { + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) { + Result = TRUE; + } + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate SB engine on wrapper + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval SB engine pointer or NULL + */ +PCIe_ENGINE_CONFIG * +PcieConfigLocateSbEngine ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsSbPcieEngine (EngineList)) { + return EngineList; + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return NULL; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump engine configuration + * + * + * @param[in] EngineList Engine Configuration + */ +VOID +PcieConfigEngineDebugDump ( + IN PCIe_ENGINE_CONFIG *EngineList + ) +{ + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", + ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); + IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); + if (PcieLibIsPcieEngine (EngineList)) { + IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", + (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", + EngineList->Type.Port.Address.Address.Bus, + EngineList->Type.Port.Address.Address.Device, + EngineList->Type.Port.Address.Address.Function + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", + (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); + IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", + (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); + IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", + EngineList->Type.Port.PortData.LinkSpeedCapability + ); + } else { + IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDpToVga) ? "DP-to-VGA" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDpToLvds) ? "DP-to-LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ? "eDP To Lvds - No SW Init Required" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvdsSwInit) ? "Third party eDP To Lvds - SW Init Required" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown")))))))))))) + ); + ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); + IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); + IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump wrapper configuration + * + * + * @param[in] WrapperList Wrapper Configuration + */ +VOID +PcieConfigWrapperDebugDump ( + IN PCIe_WRAPPER_CONFIG *WrapperList + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", + PcieFmDebugGetWrapperNameString (WrapperList) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start PHY lane - %02d\n", WrapperList->StartPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End PHY lane - %02d\n", WrapperList->EndPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n" + " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n", + WrapperList->Features.PowerOffUnusedLanes, + WrapperList->Features.PowerOffUnusedPlls, + WrapperList->Features.ClkGating, + WrapperList->Features.LclkGating, + WrapperList->Features.TxclkGatingPllPowerDown, + WrapperList->Features.PllOffInL1 + ); + IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n", + PcieFmDebugGetWrapperNameString (WrapperList) + ); + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + PcieConfigEngineDebugDump (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump configuration to debug out + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieConfigDebugDump ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *SiliconList; + PCIe_WRAPPER_CONFIG *WrapperList; + PCIe_COMPLEX_CONFIG *ComplexList; + ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n", + (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" : + (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : ( + (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : ( + (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : ( + (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown"))) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n", + (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled" + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n", + Pcie->LinkL0Pooling + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n", + Pcie->LinkGpioResetAssertionTime + ); + IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n", + Pcie->LinkReceiverDetectionPooling + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n", + (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : ( + (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown") + ); + while (ComplexList != NULL) { + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId); + SiliconList = PcieConfigGetChildSilicon (ComplexList); + while (SiliconList != NULL) { + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId); + IDS_HDT_CONSOLE (PCIE_MISC, " Node ID - %d\n", SiliconList->NodeId); + IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n", + SiliconList->Address.Address.Bus, + SiliconList->Address.Address.Device, + SiliconList->Address.Address.Function + ); + WrapperList = PcieConfigGetChildWrapper (SiliconList); + while (WrapperList != NULL) { + PcieConfigWrapperDebugDump (WrapperList); + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n"); + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n"); + ComplexList = PcieLibGetNextDescriptor (ComplexList); + } + IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump input configuration to user engine descriptor + * + * + * @param[in] EngineDescriptor Pointer to engine descriptor + */ +VOID +PcieUserDescriptorConfigDump ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ) +{ + + IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n", + (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : ( + (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : ( + (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid")) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n", + EngineDescriptor->EngineData.StartLane, + EngineDescriptor->EngineData.EndLane + ); + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" , + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink, + ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls + ); + } + if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" , + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType, + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex, + ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump input configuration to debug out + * + * + * @param[in] ComplexDescriptor Pointer to user defined complex descriptor + */ +VOID +PcieUserConfigConfigDump ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor + ) +{ + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor; + UINTN ComplexIndex; + UINTN Index; + UINTN NumberOfEngines; + UINTN NumberOfComplexes; + + IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n"); + + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor); + for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) { + CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex); + NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor); + IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n", + ComplexDescriptor->SocketId, + NumberOfEngines + ); + + for (Index = 0; Index < NumberOfEngines; Index++) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); + PcieUserDescriptorConfigDump (EngineDescriptor); + } + } + IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n"); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h new file mode 100644 index 0000000000..45e5e460df --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h @@ -0,0 +1,221 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIECONFIGLIB_H_ +#define _PCIECONFIGLIB_H_ + +typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) ( + IN PCIe_DESCRIPTOR_HEADER *Descriptor, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PcieConfigGetPcieEngineMasterLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT8 +PcieConfigGetNumberOfCoreLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +VOID +PcieConfigDisableAllEngines ( + IN UINTN EngineTypeMask, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieConfigDisableEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +PcieConfigGetEnginePhyLaneBitMap ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT8 +PcieConfigGetNumberOfPhyLane ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT64 +PcieConfigGetConfigurationSignature ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId + ); + +BOOLEAN +PcieConfigCheckPortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT32 PortStatus + ); + +UINT16 +PcieConfigUpdatePortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_ENGINE_INIT_STATUS SetStatus, + IN PCIe_ENGINE_INIT_STATUS ResetStatus + ); + +VOID +PcieConfigRunProcForAllEngines ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieConfigRunProcForAllWrappers ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieConfigRunProcForAllDescriptors ( + IN UINT32 InDescriptorFlags, + IN UINT32 OutDescriptorFlags, + IN UINT32 TerminationFlags, + IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetParent ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetChild ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetPeer ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ); + +BOOLEAN +PcieConfigIsActivePcieEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +PCIe_ENGINE_CONFIG * +PcieConfigLocateSbEngine ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieConfigDebugDump ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieConfigWrapperDebugDump ( + IN PCIe_WRAPPER_CONFIG *WrapperList + ); + +VOID +PcieConfigEngineDebugDump ( + IN PCIe_ENGINE_CONFIG *EngineList + ); + +VOID +PcieUserConfigConfigDump ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor + ); + +VOID +PcieUserDescriptorConfigDump ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ); + +#define PcieConfigGetParentWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) +#define PcieConfigGetParentSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header))) +#define PcieConfigGetParentComplex(Descriptor) ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header))) +#define PcieConfigGetPlatform(Descriptor) ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header))) +#define PcieConfigGetChildWrapper(Descriptor) ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header))) +#define PcieConfigGetChildEngine(Descriptor) ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header))) +#define PcieConfigGetChildSilicon(Descriptor) ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header))) +#define PcieConfigGetNextDescriptor(Descriptor) ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) +#define PcieConfigIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE) +#define PcieConfigIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE) +#define PcieConfigIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE) +#define PcieConfigIsSbPcieEngine(Engine) (Engine != NULL ? ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) : FALSE) +#define PcieConfigIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE) +#define PcieConfigIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE) +#define PcieConfigIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE) +#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags) if (Descriptor != NULL) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags +#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) if (Descriptor != NULL) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags)) +#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL) +#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (Descriptor != NULL ? (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) : NULL) +#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY) +#define PcieConfigGetNextDataDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0 ? NULL : Descriptor+1) + +#define PcieConfigGetStdHeader(Descriptor) ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader) + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c new file mode 100644 index 0000000000..8a174b5344 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c @@ -0,0 +1,277 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to parse PCIe input configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINTN Index + ); + +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptorOfSocket ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINT32 SocketId + ); + +PCIe_ENGINE_DESCRIPTOR* +PcieInputParserGetEngineDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex, + IN UINTN Index + ); + +UINTN +PcieInputParserGetNumberOfEngines ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); + +UINTN +PcieInputParserGetNumberOfComplexes ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + ); + +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of complexes in platform topology configuration + * + * + * + * @param[in] ComplexList First complex configuration in complex configuration array + * @retval Number of Complexes + * + */ +UINTN +PcieInputParserGetNumberOfComplexes ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + ) +{ + UINTN Result; + Result = 0; + while (ComplexList != NULL) { + Result++; + ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of PCIe engines in given complex + * + * + * + * @param[in] Complex Complex configuration + * @retval Number of Engines + */ +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + PCIe_PORT_DESCRIPTOR *PciePortList; + Result = 0; + PciePortList = Complex->PciePortList; + while (PciePortList != NULL) { + Result++; + PciePortList = PcieInputParsetGetNextDescriptor (PciePortList); + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of DDI engines in given complex + * + * + * + * @param[in] Complex Complex configuration + * @retval Number of Engines + */ +STATIC UINTN +PcieInputParserGetLengthOfDdiEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + PCIe_DDI_DESCRIPTOR *DdiLinkList; + Result = 0; + DdiLinkList = Complex->DdiLinkList; + while (DdiLinkList != NULL) { + Result++; + DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList); + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of engines in given complex + * + * + * + * @param[in] Complex Complex configuration header + * @retval Number of Engines + */ +UINTN +PcieInputParserGetNumberOfEngines ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ) +{ + UINTN Result; + + Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) + + PcieInputParserGetLengthOfPcieEnginesList (Complex); + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Complex descriptor by index from given Platform configuration + * + * + * + * @param[in] ComplexList Platform topology configuration + * @param[in] Index Complex descriptor Index + * @retval Pointer to Complex Descriptor + */ +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINTN Index + ) +{ + ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList))); + return &ComplexList[Index]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Complex descriptor by index from given Platform configuration + * + * + * + * @param[in] ComplexList Platform topology configuration + * @param[in] SocketId Socket Id + * @retval Pointer to Complex Descriptor + */ +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptorOfSocket ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINT32 SocketId + ) +{ + PCIe_COMPLEX_DESCRIPTOR *Result; + Result = NULL; + while (ComplexList != NULL) { + if (ComplexList->SocketId == SocketId) { + Result = ComplexList; + break; + } + ComplexList = PcieInputParsetGetNextDescriptor (ComplexList); + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Engine descriptor from given complex by index + * + * + * + * @param[in] Complex Complex descriptor + * @param[in] Index Engine descriptor index + * @retval Pointer to Engine Descriptor + */ +PCIe_ENGINE_DESCRIPTOR* +PcieInputParserGetEngineDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex, + IN UINTN Index + ) +{ + UINTN PcieListlength; + ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex))); + PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex); + if (Index < PcieListlength) { + return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]); + } else { + return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]); + } +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h new file mode 100644 index 0000000000..488c514040 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to parse PCIe input configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEINPUTPARSER_H_ +#define _PCIEINPUTPARSER_H_ + + +UINTN +PcieInputParserGetNumberOfComplexes ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList + ); + +UINTN +PcieInputParserGetNumberOfEngines ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); + + +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINTN Index + ); + +PCIe_ENGINE_DESCRIPTOR* +PcieInputParserGetEngineDescriptor ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex, + IN UINTN Index + ); + +PCIe_COMPLEX_DESCRIPTOR* +PcieInputParserGetComplexDescriptorOfSocket ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexList, + IN UINT32 SocketId + ); + +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c new file mode 100644 index 0000000000..cb24a9b284 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c @@ -0,0 +1,645 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to map user define topology to processor configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GeneralServices.h" +#include "PcieInputParser.h" +#include "PcieMapTopology.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +AGESA_STATUS +STATIC +PcieMapPortsPciAddresses ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieMapTopologyOnWrapper ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieMapInitializeEngineData ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +BOOLEAN +PcieCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieIsDescriptorLinkWidthValid ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ); + +BOOLEAN +PcieCheckLanesMatch ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieCheckDescriptorMapsToWrapper ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PcieAllocateEngine ( + IN UINT8 DescriptorIndex, + IN PCIe_ENGINE_CONFIG *Engine + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in] Complex Pointer to complex descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieMapTopologyOnComplex ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_COMPLEX_CONFIG *Complex, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + PCIe_WRAPPER_CONFIG *Wrapper; + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n"); + Silicon = PcieConfigGetChildSilicon (Complex); + while (Silicon != NULL) { + Wrapper = PcieConfigGetChildWrapper (Silicon); + while (Wrapper != NULL) { + Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n", + PcieFmDebugGetWrapperNameString (Wrapper) + ); + ASSERT (FALSE); + } + Wrapper = PcieLibGetNextDescriptor (Wrapper); + } + Status = PcieMapPortsPciAddresses (Silicon, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Silicon = PcieLibGetNextDescriptor (Silicon); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] EngineType Engine type + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ +STATIC AGESA_STATUS +PcieEnginesToWrapper ( + IN PCIE_ENGINE_TYPE EngineType, + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + AGESA_STATUS Status; + PCIe_ENGINE_CONFIG *EngineList; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + UINT8 ConfigurationId; + UINT8 Allocations; + UINTN Index; + UINTN NumberOfDescriptors; + + ConfigurationId = 0; + Allocations = 0; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n"); + NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor); + do { + Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++); + if (Status == AGESA_SUCCESS) { + Allocations = 0; + for (Index = 0; Index < NumberOfDescriptors; Index++) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index); + if (EngineDescriptor->EngineData.EngineType == EngineType) { + // Step 1, belongs to wrapper check. + if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) { + ++Allocations; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (!PcieLibIsEngineAllocated (EngineList)) { + // Step 2.user descriptor less or equal to link width of engine + if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) { + // Step 3, Check if link width is correct.x1, x2, x4, x8, x16. + if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) { + PcieConfigDisableEngine (EngineList); + return AGESA_ERROR; + } + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + // Step 4, Family specifc, port device number match engine device + if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { + //Step 5, Family specifc, lanes can be muxed. + if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) { + PcieAllocateEngine ((UINT8) Index, EngineList); + --Allocations; + break; + } + } + } else { + PcieAllocateEngine ((UINT8) Index, EngineList); + --Allocations; + break; + } + } + } //end if PcieLibIsEngineAllocated + EngineList = PcieLibGetNextDescriptor (EngineList); + } + } //end if PcieCheckDescriptorMapsToWrapper + } // end if EngineType + } //end for + } + } while (Status == AGESA_SUCCESS && Allocations != 0); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * + * + * @param[in] EngineDescriptor Pointer to used define engine descriptor + * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG + * @retval TRUE Belongs to wrapper + * @retval FALSE Not belongs to wrapper + */ +BOOLEAN +PcieCheckDescriptorMapsToWrapper ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + Result = FALSE; + + if (Wrapper->StartPhyLane <= DescriptorLoLane && DescriptorHiLane <= Wrapper->EndPhyLane) { + // Lanes of descriptor belongs to wrapper + Result = TRUE; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Engine to be allocated. + * + * + * @param[in] DescriptorIndex UINT8 index + * @param[in] Engine Pointer to engine config + */ +VOID +PcieAllocateEngine ( + IN UINT8 DescriptorIndex, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); + Engine->Scratch = DescriptorIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * PCIE port + * + * + * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) + * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 + * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG) + * 5 Check if lane can be muxed + * + * + * DDI Link + * + * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG) + * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) + * + * + * + * @param[in] ComplexDescriptor Pointer to used define complex descriptor + * @param[in,out] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ +AGESA_STATUS +PcieMapTopologyOnWrapper ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_ENGINE_CONFIG *EngineList; + UINT32 WrapperPhyLaneBitMap; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (PcieLibIsPcieWrapper (Wrapper)) { + Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + // If we can not map topology on wrapper we can not enable any engines. + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION, + Wrapper->WrapId, + Wrapper->StartPhyLane, + Wrapper->EndPhyLane, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableAllEngines (PciePortEngine, Wrapper); + } + } + if (PcieLibIsDdiWrapper (Wrapper)) { + Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_ERROR) { + // If we can not map topology on wrapper we can not enable any engines. + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION, + Wrapper->WrapId, + Wrapper->StartPhyLane, + Wrapper->EndPhyLane, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper); + } + } + // Copy engine data + PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie); + + EngineList = PcieConfigGetChildEngine (Wrapper); + // Verify if we oversubscribe lanes and PHY link width + WrapperPhyLaneBitMap = 0; + while (EngineList != NULL) { + UINT32 EnginePhyLaneBitMap; + if (PcieLibIsEngineAllocated (EngineList)) { + EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList); + if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) { + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n", + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_LANES_CONFIGURATION, + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + PcieConfigDisableEngine (EngineList); + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } else { + WrapperPhyLaneBitMap |= EnginePhyLaneBitMap; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize engine data + * + * + * + * @param[in] ComplexDescriptor Pointer to user defined complex descriptor + * @param[in,out] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieMapInitializeEngineData ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN OUT PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (EngineList->Scratch != 0xFF) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch); + LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie)); + if (PcieLibIsDdiEngine (EngineList)) { + LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie)); + EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch; + } else if (PcieLibIsPcieEngine (EngineList)) { + LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie)); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate PCI addresses for all PCIe engines on silicon + * + * + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + + if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber && + PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) || + (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) { + Result = TRUE; + } else { + Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); + } + + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate PCI addresses for all PCIe engines on silicon + * + * + * + * @param[in] Silicon Pointer to silicon configurration + * @param[in] Pcie Pointer PCIe configuration + * @retval AGESA_ERROR Fail to allocate PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports + */ + +AGESA_STATUS +STATIC +PcieMapPortsPciAddresses ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_WRAPPER_CONFIG *WrapperList; + PCIe_ENGINE_CONFIG *EngineList; + AgesaStatus = AGESA_SUCCESS; + WrapperList = PcieConfigGetChildWrapper (Silicon); + while (WrapperList != NULL) { + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + Status = PcieFmMapPortPciAddress (EngineList); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO ( + 0, + Silicon->Address.Address.Bus, + EngineList->Type.Port.PortData.DeviceNumber, + EngineList->Type.Port.PortData.FunctionNumber, + 0 + ); + } else { + EngineList->Type.Port.PortData.PortPresent = OFF; + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n" + ); + //Report error + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION, + EngineList->Type.Port.PortData.DeviceNumber, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * If link width from user descriptor less or equal to link width of engine + * + * + * @param[in] EngineDescriptor Pointer to used define engine descriptor + * @param[in] Engine Pointer to engine config + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckLanesMatch ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + Result = FALSE; + + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + // + // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG) + // + if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) { + Result = TRUE; + } + } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + // + //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG) + // + if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) { + Result = TRUE; + } + } + + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8 + * + * + * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieIsDescriptorLinkWidthValid ( + IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor + ) +{ + BOOLEAN Result; + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + + Result = FALSE; + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 || + DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) { + Result = TRUE; + } + } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) { + if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) { + Result = TRUE; + } + } + + GNB_DEBUG_CODE ( + if (!Result) { + IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n", + DescriptorLoLane, + DescriptorHiLane + ); + } + ); + + return Result; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h new file mode 100644 index 0000000000..9cd49db41e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h @@ -0,0 +1,57 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Procedure to map user define topology to processor configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEMAPTOPOLOGY_H_ +#define _PCIEMAPTOPOLOGY_H_ + +AGESA_STATUS +PcieMapTopologyOnComplex ( + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_COMPLEX_CONFIG *Complex, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h new file mode 100644 index 0000000000..01cd3530a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h @@ -0,0 +1,60 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Init Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEINITLIBV1_H_ +#define _PCIEINITLIBV1_H_ + +#include "PciePifServices.h" +#include "PciePortRegAcc.h" +#include "PciePowerMgmt.h" +#include "PcieTimer.h" +#include "PcieTopologyServices.h" +#include "PcieUtilityLib.h" +#include "PcieWrapperRegAcc.h" +#include "PcieAspmExitLatency.h" +#include "PcieSiliconServices.h" +#include "PciePortServices.h" +#include "PcieAspm.h" +#include "PciePhyServices.h" +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c new file mode 100644 index 0000000000..64e7cb36fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -0,0 +1,173 @@ +/** + * @file + * + * PCIe link ASPM Black List + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "PcieAspmBlackList.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +UINT16 AspmBrDeviceTable[] = { + 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s), + 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), + 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), + 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), + 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), + 0x1B4B, 0x9123, (UINT16) ~(AspmL0s), + 0x1969, 0x1083, (UINT16) ~(AspmL0s), + 0x1033, 0x0194, (UINT16) ~(AspmL0s), + 0x1180, 0xE832, (UINT16) ~(AspmL0s), + 0x1180, 0xE823, (UINT16) ~(AspmL0s) +}; + +UINT16 Aspm168cL0sEnabled[] = { + 0x002B, + 0x002C, + 0x002E, + 0x002A, + 0x002D, + 0x0024, + 0x001B, + 0x0030, + 0x0032 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie ASPM Black List + * + * + * + * @param[in] LinkAspm PCie ASPM black list + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAspmBlackListFeature ( + IN PCIe_LINK_ASPM *LinkAspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 UpstreamDeviceId; + UINT32 DownstreamDeviceId; + UINTN i; + UINT32 DeviceId; + UINT32 VendorId; + + GnbLibPciRead (LinkAspm->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader); + GnbLibPciRead (LinkAspm->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader); + LinkAspm->BlackList = FALSE; + for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) { + VendorId = AspmBrDeviceTable[i]; + DeviceId = AspmBrDeviceTable[i + 1]; + if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) { + if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) { + LinkAspm->UpstreamAspm &= AspmBrDeviceTable[i + 2]; + LinkAspm->DownstreamAspm &= AspmBrDeviceTable[i + 2]; + LinkAspm->BlackList = TRUE; + } + } + } + if ((UINT16)UpstreamDeviceId == 0x168c) { + // Atheros (Ignore dev capability enable L1 if requested) + LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL1; + LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm; + GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader); + + DeviceId = UpstreamDeviceId >> 16; + for (i = 0; i < (sizeof (Aspm168cL0sEnabled) / sizeof (UINT16)); i++) { + if (DeviceId == Aspm168cL0sEnabled[i]) { + LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL0sL1; + LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm & AspmL1; + } + } + + } + if (UpstreamDeviceId == 0x10831969) { + GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x12F8, AccessS3SaveWidth32, 0xFFF7F7FF, 0, StdHeader); + } + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h new file mode 100644 index 0000000000..3ae175da73 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h @@ -0,0 +1,55 @@ +/** + * @file + * + * PCIe ASPM Black List + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPMBLACKLIST_H_ +#define _PCIEASPMBLACKLIST_H_ + +///PCIe ASPM Black List + +AGESA_STATUS +PcieAspmBlackListFeature ( + IN PCIe_LINK_ASPM *LinkAspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h new file mode 100644 index 0000000000..a6aff55594 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to calculate PCIe topology segment maximum exit latency + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPMEXITLATENCY_H_ +#define _PCIEASPMEXITLATENCY_H_ + +VOID +PcieAspmGetMaxExitLatency ( + IN PCI_ADDR DownstreamPort, + OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h new file mode 100644 index 0000000000..9b8156b563 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PHY initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEPHYSERVICES_H_ +#define _PCIEPHYSERVICES_H_ + +VOID +PciePhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePhyForceDccRecalibration ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c new file mode 100644 index 0000000000..2c9d1ce304 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c @@ -0,0 +1,622 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define PIF_GANG_0to1 0x1 +#define PIF_GANG_2to3 (0x1 << 1) +#define PIF_GANG_4to5 (0x1 << 2) +#define PIF_GANG_6to7 (0x1 << 3) +#define PIF_GANG_0to3 (0x1 << 4) +#define PIF_GANG_4to7 (0x1 << 8) +#define PIF_GANG_0to7 (0x1 << 9) +#define PIF_GANG_ALL (0x1 << 25) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply PIF ganging for all lanes for given wrapper + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +VOID +PciePifApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 LaneBitmap; + UINT8 Pif; + D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2]; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n"); + LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie)); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList); + switch (LaneBitmap) { + case 0x0003: + D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1; + break; + case 0x000c: + D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1; + break; + case 0x0030: + D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1; + break; + case 0x00c0: + D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1; + break; + case 0x000f: + D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1; + break; + case 0x00f0: + D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1; + break; + case 0x00ff: + D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1; + break; + case 0x0300: + D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1; + break; + case 0x0c00: + D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1; + break; + case 0x3000: + D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1; + break; + case 0xc000: + D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1; + break; + case 0x0f00: + D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1; + break; + case 0xf000: + D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1; + break; + case 0xff00: + D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1; + break; + case 0xffff: + D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1; + D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1; + break; + default: + break; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS), + D0F0xE4_PIF_0011[Pif].Value, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL powerdown + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllPowerDown ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + UINT16 NibbleBitmap; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n"); + for (Nibble = 0; Nibble < 4; Nibble++) { + NibbleBitmap = (0xF << (Nibble * 4)); + if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL init for DDI + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllInitForDdi ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + UINT32 LaneBitmap; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + for (Nibble = 0; Nibble < 4; Nibble++) { + if (LaneBitmap & (0xF << (Nibble * 4))) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for on PIF to indicate action completion + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollPifForCompeletion ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + UINT32 Value; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + do { + Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, 0x15), + Pcie + ); + } while ((Value & 0xff) != 0xff); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable fifo reset + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +VOID +PciePifDisableFifoReset ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET, + D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH, + 0, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program LS2 exit time + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePifSetLs2ExitTime ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, + D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, + 0x0, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PLL mode for L1 + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + for (Nibble = 0; Nibble < 4; Nibble++) { + if (LaneBitmap & (0xF << (Nibble * 4))) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + Pcie + ); + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program receiver detection power mode + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET, + D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH, + 0x1, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Pll ramp up time + * + * + * + * @param[in] Rampup Ramp up time + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifSetPllRampTime ( + IN PCIE_PLL_RAMPUP_TIME Rampup, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; + D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0013.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0010.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + Pcie + ); + if (Rampup == NormalRampup) { + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; + D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1; + D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0; + } else { + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3; + D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3; + D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6; + } + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010.Value, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down PIFs + * + * + * + * @param[in] Control Power up or Power down control + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifPllPowerControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + UINT8 PllPowerStateInOff; + PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET, + D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH, + PllPowerStateInOff, + FALSE, + Pcie + ); + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET, + D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH, + PllPowerStateInOff, + FALSE, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down PIFs + * + * + * + * @param[in] Control Power up/Down control + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePifFullPowerStateControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + D0F0xE4_PIF_0013.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + Pcie + ); + if (Control == PowerDownPifs) { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff; + } else { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; + D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2; + D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0; + } + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), + D0F0xE4_PIF_0013.Value, + FALSE, + Pcie + ); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h new file mode 100644 index 0000000000..50dca90570 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h @@ -0,0 +1,120 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEPIFSERVICES_H_ +#define _PCIEPIFSERVICES_H_ + +VOID +PciePifApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerDown ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllInitForDdi ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollPifForCompeletion ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifDisableFifoReset ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetLs2ExitTime ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetPllRampTime ( + IN PCIE_PLL_RAMPUP_TIME Rampup, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifFullPowerStateControl ( + IN PCIE_PIF_POWER_CONTROL Control, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c new file mode 100644 index 0000000000..3fc8561c02 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c @@ -0,0 +1,273 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe port indirect register + * space. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT32 +PciePortRegisterRead ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWrite ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PciePortRegisterReadField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWriteField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterRMW ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe port indirect register. + * + * Support for unify register access through index/data pair on PCIe port + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] Pcie Pointer to internal configuration data area + * @retval Register Value + */ + +UINT32 +PciePortRegisterRead ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save for S3 flag + * @param[in] Pcie Pointer to internal configuration data area + */ +VOID +PciePortRegisterWrite ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ASSERT (S3Save == TRUE || S3Save == FALSE); + + IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n", + Engine->Type.Port.Address.Address.Bus, + Engine->Type.Port.Address.Address.Device, + Engine->Type.Port.Address.Address.Function, + Address, + Value + ); + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] S3Save Save for S3 flag + * @param[in] Value New register value + * @param[in] Pcie Pointer to internal configuration data area + */ + +VOID +PciePortRegisterWriteField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Data; + UINT32 Mask; + Data = PciePortRegisterRead (Engine, Address, Pcie); + Mask = (1 << FieldWidth) - 1; + Value &= Mask; + Data &= (~(Mask << FieldOffset)); + PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe Port Indirect register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Pcie Pointer to internal configuration data area + * @retval Register Field Value. + */ + +UINT32 +PciePortRegisterReadField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PciePortRegisterRead (Engine, Address, Pcie); + Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe port register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Engine Pointer to Engine descriptor for this port + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePortRegisterRMW ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PciePortRegisterRead (Engine, Address, Pcie); + Value = (Value & (~AndMask)) | OrMask; + PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h new file mode 100644 index 0000000000..a6195485e8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe port indirect register space. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTREGACC_H_ +#define _PCIEPORTREGACC_H_ + +UINT32 +PciePortRegisterRead ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWrite ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterWriteField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PciePortRegisterReadField ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortRegisterRMW ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT16 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c new file mode 100644 index 0000000000..c6688ebe96 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c @@ -0,0 +1,396 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +UINT8 L1State = 0x1b; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Set completion timeout + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieCompletionTimeout ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | 0x80, + AccessWidth32, + 0xffffffff, + 0x6 << 0, + GnbLibGetHeader (Pcie) + ); + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PciePortRegisterWriteField ( + Engine, + 0x20, + 15, + 1, + 0x0, + TRUE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init hotplug port + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkInitHotplug ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { + Value = PciePortRegisterRead (Engine, 0xb5, Pcie); + Value |= 3 << 12; + Value |= 3 << 14; + Value |= 1 << 10; + PciePortRegisterWrite ( + Engine, + 0xb5, + Value, + TRUE, + Pcie + ); + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, + D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, + 0x5, + TRUE, + Pcie + ); + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, + D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, + 0x1, + TRUE, + Pcie + ); + } + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | 0x6c, + AccessS3SaveWidth32, + 0xffffffff, + 1 << 6, + GnbLibGetHeader (Pcie) + ); + PciePortRegisterWriteField ( + Engine, + 0x20, + 15, + 1, + 0x0, + TRUE, + Pcie + ); + PciePortRegisterWriteField ( + Engine, + 0x70, + 19, + 1, + 0x1, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set misc slot capability + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkSetSlotCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | 0x58, + AccessWidth32, + 0xffffffff, + 1 << 24, + GnbLibGetHeader (Pcie) + ); + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | 0x3c, + AccessWidth32, + 0xffffffff, + 1 << 8, + GnbLibGetHeader (Pcie) + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Safe mode to force link advertize Gen1 only capability in TS + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkSafeMode ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieFmSetLinkSpeedCap (PcieGen1, Engine, Pcie); + PciePortRegisterRMW ( + Engine, + 0xa2, + 0x2000, + (1 << 13), + FALSE, + Pcie + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetLinkWidthCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortRegisterRMW ( + Engine, + 0xa2, + 0x2000, + 0, + FALSE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Force compliance + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieForceCompliance ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | 0x88, + AccessWidth32, + 0xffffffff, + 0x1 << 4, + GnbLibGetHeader (Pcie) + ); + } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { + PciePortRegisterWriteField ( + Engine, + 0xc0, + 13, + 1, + 0x1, + FALSE, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable ASPM on SB link + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieEnableAspm ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { + if (PcieConfigIsSbPcieEngine (Engine)) { + SbPcieLinkAspmControl (Engine, Pcie); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for link to get into L1 + * + * + * + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollLinkForL1Entry ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[8]; + do { + PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); + } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State))); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll for link to get into L0 + * + * + * + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePollLinkForL0Exit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[4]; + do { + PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie); + } while (LinkHwStateHistory[0] != 0x10); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h new file mode 100644 index 0000000000..67c66bb6fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTSERVICES_H_ +#define _PCIEPORTSERVICES_H_ + + +VOID +PcieSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetLinkWidthCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkSafeMode ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieCompletionTimeout ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkSetSlotCap ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkInitHotplug ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieForceCompliance ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieEnableSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieEnableAspm ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollLinkForL1Entry ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePollLinkForL0Exit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h new file mode 100644 index 0000000000..0eeee7979a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERSAVINGFEATURES_H_ +#define _PCIEPOWERSAVINGFEATURES_H_ + + +VOID +PciePwrPowerDownUnusedLanes ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieLanesToPowerDownPllInL1 ( + IN UINT8 PllPowerUpLatency, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrAutoPowerDownElectricalIdleDetector ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrClockGating ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h new file mode 100644 index 0000000000..66e59f41ea --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h @@ -0,0 +1,72 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Complex Services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIESILICONSERVICES_H_ +#define _PCIESILICONSERVICES_H_ + +UINT8 +PcieSiliconGetGen1VoltageIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieSiliconRequestVoltage ( + IN UINT8 VidIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieSiliconUnHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconHidePorts ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c new file mode 100644 index 0000000000..2a7a0db50c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c @@ -0,0 +1,95 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe timer access procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbTimerLib.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Get PCIe timer timestamp + * + * + * + * @param[in] Pcie Pointer to internal configuration data area + * @retval Time stamp value + */ + +UINT32 +PcieTimerGetTimeStamp ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return GnbFmTimeStamp (GnbLibGetHeader (Pcie)); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h new file mode 100644 index 0000000000..c68d214602 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe timer access procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIETIMER_H_ +#define _PCIETIMER_H_ + +UINT32 +PcieTimerGetTimeStamp ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2)) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c new file mode 100644 index 0000000000..5151fb445d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -0,0 +1,722 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Cleanup reconfig + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyCleanUpReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (PcieLibIsPcieWrapper (Wrapper)) { + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062_ConfigXferMode_MASK, + 1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET, + FALSE, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare for reconfiguration + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyPrepareForReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + UINT8 CoreId; + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), + D0F0xE4_CORE_0011_DynClkLatency_OFFSET, + D0F0xE4_CORE_0011_DynClkLatency_WIDTH, + 0xf, + FALSE, + Pcie + ); + } + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0; + D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + } +} + + +UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate mux array index + * + * + * + * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array + * @param[in] LaneMuxValue The value that match to array + * @retval Index Index successfully mapped + */ +STATIC UINT8 +PcieTopologyLocateMuxIndex ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ) +{ + UINT8 Index; + for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) { + if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply lane mux + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologyApplyLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT8 CurrentPhyLane; + UINT8 CurrentCoreLane; + UINT8 CoreLaneIndex; + UINT8 PhyLaneIndex; + UINT8 NumberOfPhyLane; + UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; + UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)]; + UINT8 Index; + UINT32 TxMaxSelectorValue; + UINT32 RxMaxSelectorValue; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + EngineList = PcieConfigGetChildEngine (Wrapper); + LibAmdMemCopy ( + &TxLaneMuxSelectorArray[0], + &LaneMuxSelectorTable[0], + sizeof (LaneMuxSelectorTable), + GnbLibGetHeader (Pcie) + ); + LibAmdMemCopy ( + &RxLaneMuxSelectorArray[0], + &LaneMuxSelectorTable[0], + sizeof (LaneMuxSelectorTable), + GnbLibGetHeader (Pcie) + ); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; + NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); + CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; + if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { + CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane; + } + for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) { + CoreLaneIndex = (CurrentCoreLane + Index) / 2; + PhyLaneIndex = (CurrentPhyLane + Index) / 2; + + if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) { + RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex]; + RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex; + } + if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) { + TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex]; + TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + RxMaxSelectorValue = 0; + TxMaxSelectorValue = 0; + for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) { + RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4)); + TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4)); + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), + TxMaxSelectorValue, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), + RxMaxSelectorValue, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Select master PLL + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologySelectMasterPll ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT16 MasterLane; + UINT16 MasterHotplugLane; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); + MasterLane = 0xFFFF; + MasterHotplugLane = 0xFFFF; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) { + if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList); + } else { + MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); + if (PcieConfigIsSbPcieEngine (EngineList)) { + break; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + if (MasterLane == 0xffff) { + if (MasterHotplugLane != 0xffff) { + MasterLane = MasterHotplugLane; + } else { + MasterLane = 0x0; + } + } + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value; + if ( MasterLane <= 3 ) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xA; + } else if (MasterLane <= 7) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xB; + } else if (MasterLane <= 11) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0; + Wrapper->MasterPll = 0xC; + } else { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1; + Wrapper->MasterPll = 0xD; + } + if (ConfigChanged != NULL) { + *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyExecuteReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n"); + + PcieTopologyServices136_fun (FALSE, Wrapper, Pcie); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + D0F0xE4_WRAP_8060.Value, + FALSE, + Pcie + ); + do { + D0F0xE4_WRAP_8060.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS), + Pcie + ); + + } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1); + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + PcieTopologyServices136_fun (TRUE, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable lane reversal + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologySetLinkReversal ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (PcieLibIsPcieEngine (EngineList)) { + if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { + PciePortRegisterWriteField ( + EngineList, + 0xc1, + 4, + 1, + 0x1, + FALSE, + Pcie + ); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Reduce link width + * + * + * @param[in] LinkWidth Link width + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyReduceLinkWidth ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *Wrapper; + UINT32 LinkReversed; + UINT8 DeltaLinkWidthBitmap; + UINT32 LanesToDisable; + Wrapper = PcieConfigGetParentWrapper (Engine); + LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie); + + DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1; + LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth))); + + PcieTopologyLaneControl ( + DisableLanes, + LanesToDisable, + Wrapper, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Lanes enable/disable control + * + * @param[in] Control Lane control action + * @param[in] LaneBitMap Core lanes bitmap + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyLaneControl ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023; + D0F0xE4_WRAP_8023.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), + Pcie + ); + + if (Control == EnableLanes) { + D0F0xE4_WRAP_8023.Value |= LaneBitMap; + } else if (Control == DisableLanes) { + D0F0xE4_WRAP_8023.Value &= (~LaneBitMap); + } + D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), + D0F0xE4_WRAP_8023.Value, + TRUE, + Pcie + ); +} + +VOID +PcieTopologyServices136_fun ( + IN BOOLEAN fv0, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GNBREGCOMMON_STR1_STRUCT GNBREGCOMMON_STR1; + GNBREGCOMMON_STR1.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8063), + Pcie + ); + if (fv0) { + GNBREGCOMMON_STR1.Field.bit4 = 0x1; + GNBREGCOMMON_STR1.Field.bit5 = 0x1; + GNBREGCOMMON_STR1.Field.bit12 = 0x1; + GNBREGCOMMON_STR1.Field.bit13 = 0x1; + GNBREGCOMMON_STR1.Field.bit14 = 0x1; + } else { + GNBREGCOMMON_STR1.Field.bit4 = 0x0; + GNBREGCOMMON_STR1.Field.bit5 = 0x0; + GNBREGCOMMON_STR1.Field.bit12 = 0x0; + GNBREGCOMMON_STR1.Field.bit13 = 0x0; + GNBREGCOMMON_STR1.Field.bit14 = 0x0; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x8063), + GNBREGCOMMON_STR1.Value, + FALSE, + Pcie + ); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set core configuration according to PCIe port topology + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieTopologySetCoreConfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + AGESA_STATUS Status; + D0F0xE4_WRAP_0080_STRUCT D0F0xE4_WRAP_0080; + + Status = AGESA_SUCCESS; + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + UINT64 ConfigurationSignature; + UINT8 NewConfigurationValue; + ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId); + Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue); + if (Status == AGESA_SUCCESS) { + IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n", + PcieFmDebugGetWrapperNameString (Wrapper), + CoreId, + PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue) + ); + D0F0xE4_WRAP_0080.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), + Pcie + ); + if (ConfigChanged != NULL) { + if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) { + *ConfigChanged = TRUE; + } + } + D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS), + D0F0xE4_WRAP_0080.Value, + FALSE, + Pcie + ); + } else { + IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n", + PcieFmDebugGetWrapperNameString (Wrapper), + ((UINT32*)&ConfigurationSignature)[1], + ((UINT32*)&ConfigurationSignature)[0] + ); + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + } + } + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set TX control for PCIe lanes + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieWrapSetTxS1CtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025; + UINT32 LaneBitmap; + UINTN Index; + D0F0xE4_WRAP_8025.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + Pcie + ); + Index = 0; + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); + while (LaneBitmap != 0) { + if ((LaneBitmap & 0xf) != 0) { + D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8))); + D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8)); + } + LaneBitmap >>= 4; + ++Index; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025.Value, + FALSE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set TX control for lane muxes + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieWrapSetTxOffCtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + 0x1f1f1f1f, + FALSE, + Pcie + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h new file mode 100644 index 0000000000..00ffd58d9f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIETOPOLOGYSERVICES_H_ +#define _PCIETOPOLOGYSERVICES_H_ + +VOID +PcieTopologyCleanUpReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyPrepareForReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieTopologySetCoreConfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyApplyLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySelectMasterPll ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyExecuteReconfig ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySetLinkReversal ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +VOID +PcieTopologyReduceLinkWidth ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyLaneControl ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyServices136_fun ( + IN BOOLEAN fv0, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetDdiOwnPhy ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieWrapSetTxS1CtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieWrapSetTxOffCtrlForLaneMux ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c new file mode 100644 index 0000000000..6af26def32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -0,0 +1,661 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/// Lane type +typedef enum { + LaneTypeCore, ///< Core Lane + LaneTypePhy, ///< Package Phy Lane + LaneTypeNativePhy ///< Native Phy Lane +} LANE_TYPE; + +/// Lane Property +typedef enum { + LanePropertyConfig, ///< Configuration + LanePropertyActive, ///< Active + LanePropertyAllocated ///< Allocated +} LANE_PROPERTY; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct { + UINT32 Flags; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; +} PCIE_GLOBAL_GEN_CAP_WORKSPACE; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link state history from HW state machine + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[out] History Buffer to save history + * @param[in] Length Buffer length + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieUtilGetLinkHwStateHistory ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT UINT8 *History, + IN UINT8 Length, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 ReadLength; + UINT32 LocalHistory [6]; + UINT16 Index; + ASSERT (Length <= 16); + ASSERT (Length > 0); + if (Length > 6*4) { + Length = 6*4; + } + ReadLength = (Length + 3) / 4; + for (Index = 0; Index < ReadLength; Index++) { + LocalHistory[Index] = PciePortRegisterRead ( + Engine, + 0xa5 + Index, + Pcie + ); + } + LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Search array for specific pattern + * + * + * @param[in] Buf1 Pointer to source buffer which will be subject of search + * @param[in] Buf1Length Length of the source buffer + * @param[in] Buf2 Pointer to pattern buffer + * @param[in] Buf2Length Length of the pattern buffer + * @retval TRUE Pattern found + * @retval TRUE Pattern not found + */ + +BOOLEAN +PcieUtilSearchArray ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ) +{ + UINT8 *CurrentBuf1Ptr; + CurrentBuf1Ptr = Buf1; + while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { + UINT8 *SourceBufPtr; + UINT8 *PatternBufPtr; + UINTN PatternBufLength; + SourceBufPtr = CurrentBuf1Ptr; + PatternBufPtr = Buf2; + PatternBufLength = Buf2Length; + while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); + if (PatternBufLength == 0) { + return TRUE; + } + CurrentBuf1Ptr++; + } + return FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link reversed + * + * + * @param[in] HwLinkState Check for HW auto link reversal + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to PCIe config descriptor + * @retval TRUE if link reversed + */ +BOOLEAN +PcieUtilIsLinkReversed ( + IN BOOLEAN HwLinkState, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LinkReversal; + + LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0; + if (HwLinkState) { + UINT32 Value; + Value = PciePortRegisterRead ( + Engine, + 0x50, + Pcie + ); + LinkReversal ^= (Value & 1); + } + return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link width detected during training + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Link width + */ +UINT8 +PcieUtilGetLinkWidth ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkWidth; + UINT32 Value; + Value = PciePortRegisterRead ( + Engine, + 0xA2, + Pcie + ); + switch ((Value & 7) >> 4) { + case 0x6: + LinkWidth = 16; + break; + case 0x5: + LinkWidth = 12; + break; + case 0x4: + LinkWidth = 8; + break; + case 0x3: + LinkWidth = 4; + break; + case 0x2: + LinkWidth = 2; + break; + case 0x1: + LinkWidth = 1; + break; + default: + LinkWidth = 0; + } + return LinkWidth; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of PCIE engine lane of requested type + * + * + * @param[in] LaneType Lane type + * @param[in] LaneProperty Lane Property + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetPcieEngineLaneBitMap ( + IN LANE_TYPE LaneType, + IN LANE_PROPERTY LaneProperty, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + UINT8 Width; + UINT16 Offset; + UINT16 LoPhylane; + UINT16 HiPhylane; + PCIe_PLATFORM_CONFIG *Pcie; + + Width = 0; + Offset = 0; + LaneBitmap = 0; + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + + if (PcieConfigIsPcieEngine (Engine)) { + if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) { + Width = PcieConfigGetNumberOfCoreLane (Engine); + Offset = Engine->Type.Port.StartCoreLane; + LaneBitmap = ((1 << Width) - 1) << Offset; + } else if (PcieConfigIsEngineAllocated (Engine)) { + if (LaneType == LaneTypeNativePhy) { + LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); + LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); + } else { + if (LaneType == LaneTypeCore) { + if (LaneProperty == LanePropertyActive) { + Width = PcieUtilGetLinkWidth (Engine, Pcie); + Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; + } else if (LaneProperty == LanePropertyAllocated) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane; + } + } + if (LaneType == LaneTypePhy) { + LoPhylane = PcieLibGetLoPhyLane (Engine); + HiPhylane = PcieLibGetHiPhyLane (Engine); + if (LaneProperty == LanePropertyActive) { + Width = PcieUtilGetLinkWidth (Engine, Pcie); + Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + } else if (LaneProperty == LanePropertyAllocated) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + } + } + LaneBitmap = ((1 << Width) - 1) << Offset; + } + } + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of PCIE engine lane of requested type + * + * + * @param[in] LaneType Lane type + * @param[in] LaneProperty Lane Property + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetDdiEngineLaneBitMap ( + IN LANE_TYPE LaneType, + IN LANE_PROPERTY LaneProperty, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + UINT8 Width; + UINT16 Offset; + Width = 0; + Offset = 0; + LaneBitmap = 0; + if (PcieConfigIsDdiEngine (Engine)) { + if (PcieConfigIsEngineAllocated (Engine)) { + if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) { + Width = PcieConfigGetNumberOfPhyLane (Engine); + Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane; + LaneBitmap = ((1 << Width) - 1) << Offset; + } + if (LaneType == LaneTypeNativePhy) { + LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine); + LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine); + } + } + } + return LaneBitmap; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of engine lane of requested type + * + * + * @param[in] IncludeLaneType Include Lane type + * @param[in] ExcludeLaneType Exclude Lane type + * @param[in] Engine Pointer to engine config descriptor + * @retval Lane bitmap + */ + +UINT32 +PcieUtilGetEngineLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitmap; + LaneBitmap = 0; + if (IncludeLaneType & LANE_TYPE_PCIE_LANES) { + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) { + if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } else { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine); + } + } + } + if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine); + } + if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_PHY) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) { + if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } else { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); + } + } + } + if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) { + LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + } + if (IncludeLaneType & LANE_TYPE_DDI_LANES) { + if (IncludeLaneType & LANE_TYPE_DDI_PHY) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine); + } + if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) { + LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine); + } + } + if (ExcludeLaneType != 0) { + LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine)); + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of phy lane confugred for master pll + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval Lane bitmap + */ + +STATIC UINT32 +PcieUtilGetMasterPllLaneBitMap ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + if (Wrapper->MasterPll != 0) { + return 0xf << (Wrapper->MasterPll - 0xA) * 4; + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bitmap of Wrapper lane of requested type + * + * + * @param[in] IncludeLaneType Include Lane type + * @param[in] ExcludeLaneType Exclude Lane type + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval Lane bitmap + */ + +UINT32 +PcieUtilGetWrapperLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 LaneBitmap; + EngineList = PcieConfigGetChildEngine (Wrapper); + LaneBitmap = 0; + if ((IncludeLaneType | ExcludeLaneType) != 0) { + if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) { + LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1; + if (ExcludeLaneType != 0) { + LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper)); + } + } else { + while (EngineList != NULL) { + LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList); + EngineList = PcieLibGetNextDescriptor (EngineList); + } + if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) { + LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper); + } + if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) { + LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper)); + } + } + } + return LaneBitmap; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program port register table + * + * + * + * @param[in] Table Pointer to table + * @param[in] Length number of entries + * @param[in] Engine Pointer to engine config descriptor + * @param[in] S3Save Save for S3 flag + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PciePortProgramRegisterTable ( + IN PCIE_PORT_REGISTER_ENTRY *Table, + IN UINTN Length, + IN PCIe_ENGINE_CONFIG *Engine, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + UINT32 Value; + for (Index = 0; Index < Length; Index++) { + Value = PciePortRegisterRead ( + Engine, + Table[Index].Reg, + Pcie + ); + Value &= (~Table[Index].Mask); + Value |= Table[Index].Data; + PciePortRegisterWrite ( + Engine, + Table[Index].Reg, + Value, + S3Save, + Pcie + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Lock registers + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieLockRegisters ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_HwInitWrLock_OFFSET, + D0F0xE4_CORE_0010_HwInitWrLock_WIDTH, + 0x1, + TRUE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Training state handling + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Indicate if engine in non final state + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieUtilGlobalGenCapabilityCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_HOTPLUG_TYPE HotPlugType; + UINT32 Flags; + + Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; + GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; + LinkSpeedCapability = PcieGen1; + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; + } + HotPlugType = Engine->Type.Port.PortData.LinkHotplug; + if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { + Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; + } + if ((GlobalGenCapability->Flags & Flags) != 0) { + ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); + LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine); + if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { + GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine global GEN capability + * + * + * @param[in] Flags global GEN capability flags + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalCapability; + PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap; + + GlobalGenCap.LinkSpeedCapability = PcieGen1; + GlobalGenCap.Flags = Flags; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieUtilGlobalGenCapabilityCallback, + &GlobalGenCap, + Pcie + ); + + GlobalCapability = GlobalGenCap.LinkSpeedCapability; + + return GlobalCapability; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h new file mode 100644 index 0000000000..09f090329b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h @@ -0,0 +1,131 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEUTILLIB_H_ +#define _PCIEUTILLIB_H_ + +/// Core lanes +typedef enum { + AllCoreLanes, ///< All core lanes + AllocatedCoreLanes, ///< Allocated core lanes + ActiveCoreLanes, ///< Active core lanes + HotplugCoreLanes, ///< Hot plug core lanes + SbCoreLanes, ///< South bridge core lanes +} CORE_LANES; + +/// DDI lanes +typedef enum { + DdiAllLanes, ///< All DDI Lanes + DdiActiveLanes ///< Active DDI Lanes +} DDI_LANES; + +BOOLEAN +PcieUtilSearchArray ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ); + +VOID +PcieUtilGetLinkHwStateHistory ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT UINT8 *History, + IN UINT8 Length, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +BOOLEAN +PcieUtilIsLinkReversed ( + IN BOOLEAN HwLinkState, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +UINT8 +PcieUtilGetLinkWidth ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +UINT32 +PcieUtilGetEngineLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +PcieUtilGetWrapperLaneBitMap ( + IN UINT32 IncludeLaneType, + IN UINT32 ExcludeLaneType, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PciePortProgramRegisterTable ( + IN PCIE_PORT_REGISTER_ENTRY *Table, + IN UINTN Length, + IN PCIe_ENGINE_CONFIG *Engine, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLockRegisters ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c new file mode 100644 index 0000000000..eed1d2fb77 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c @@ -0,0 +1,300 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to Wrapper descriptor + * @param[in] Address Register address + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register Value + */ +UINT32 +PcieRegisterRead ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { + Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); + } + return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register Value + */ + +UINT32 +PcieSiliconRegisterRead ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieRegisterWrite ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { + Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); + } + PcieSiliconRegisterWrite ( + PcieConfigGetParentSilicon (Wrapper), + Address, + Value, + S3Save, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register value. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] Value New register value + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSiliconRegisterWrite ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n", + PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)), + Silicon->Address.Address.Bus, + Silicon->Address.Address.Device, + Silicon->Address.Address.Function, + Address, + Value + ); + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); + GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCIe register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Pcie Pointer to global PCIe configuration + * @retval Register field value + */ + +UINT32 +PcieRegisterReadField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PcieRegisterRead (Wrapper, Address, Pcie); + Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth)); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCIe register field. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Value Value to write + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + + +VOID +PcieRegisterWriteField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TempValue; + UINT32 Mask; + TempValue = PcieRegisterRead (Wrapper, Address, Pcie); + Mask = (~(0xFFFFFFFF << FieldWidth)); + Value &= Mask; + TempValue &= (~(Mask << FieldOffset)); + PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper descriptor + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieRegisterRMW ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { + Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); + } + PcieSiliconRegisterRMW ( + PcieConfigGetParentSilicon (Wrapper), + Address, + AndMask, + OrMask, + S3Save, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCIe register. + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Silicon Pointer to silicon descriptor + * @param[in] Address Register address + * @param[in] AndMask Value & (~AndMask) + * @param[in] OrMask Value | OrMask + * @param[in] S3Save Save register for S3 (True/False) + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieSiliconRegisterRMW ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + Value = PcieSiliconRegisterRead (Silicon, Address, Pcie); + Value = (Value & (~AndMask)) | OrMask; + PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h new file mode 100644 index 0000000000..9a7e9013ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h @@ -0,0 +1,127 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIEWRAPPERREGACC_H_ +#define _PCIEWRAPPERREGACC_H_ + +//#define WRAP_SPACE(w, x) (0x01300000ul | (w << 16) | (x)) +//#define CORE_SPACE(c, x) (0x00010000ul | (c << 24) | (x)) +//#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x)) +//#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x)) +#define IMP_SPACE(x) (0x01080000ul | (x)) + +UINT32 +PcieRegisterRead ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterWrite ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieRegisterReadField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterWriteField ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieRegisterRMW ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieSiliconRegisterRead ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconRegisterWrite ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSiliconRegisterRMW ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT32 Address, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN BOOLEAN S3Save, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h new file mode 100644 index 0000000000..e6221fff07 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h @@ -0,0 +1,52 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Init Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEINITLIBV4_H_ +#define _GNBPCIEINITLIBV4_H_ + +#include "PcieWrapperServicesV4.h" +#include "PciePowerMgmtV4.h" +#include "PciePortServicesV4.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c new file mode 100644 index 0000000000..fc43dee21d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c @@ -0,0 +1,202 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +PcieInitPortForIommuV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetLinkSpeedCapV4 ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieSetLinkSpeedCapV4 ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D2FxxE4_xA4_STRUCT D2FxxE4_xA4; + D2FxxE4_xC0_STRUCT D2FxxE4_xC0; + D2Fxx88_STRUCT D2Fxx88; + GnbLibPciRead ( + Engine->Type.Port.Address.AddressValue | D2Fxx88_ADDRESS, + AccessWidth32, + &D2Fxx88.Value, + GnbLibGetHeader (Pcie) + ); + D2FxxE4_xA4.Value = PciePortRegisterRead ( + Engine, + D2FxxE4_xA4_ADDRESS, + Pcie + ); + D2FxxE4_xC0.Value = PciePortRegisterRead ( + Engine, + D2FxxE4_xC0_ADDRESS, + Pcie + ); + + switch (LinkSpeedCapability) { + case PcieGen2: + D2FxxE4_xA4.Field.LcGen2EnStrap = 0x1; + D2FxxE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; + D2Fxx88.Field.TargetLinkSpeed = 0x2; + D2Fxx88.Field.HwAutonomousSpeedDisable = 0x0; + break; + case PcieGen1: + D2FxxE4_xA4.Field.LcGen2EnStrap = 0x0; + D2FxxE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; + D2Fxx88.Field.TargetLinkSpeed = 0x1; + D2Fxx88.Field.HwAutonomousSpeedDisable = 0x1; + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (Engine), + WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, + D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, + 0, + FALSE, + Pcie + ); + break; + default: + ASSERT (FALSE); + break; + } + + if (Pcie->PsppPolicy == PsppDisabled) { + D2FxxE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; + } else { + D2FxxE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; + } + + PciePortRegisterWrite ( + Engine, + D2FxxE4_xA4_ADDRESS, + D2FxxE4_xA4.Value, + FALSE, + Pcie + ); + PciePortRegisterWrite ( + Engine, + D2FxxE4_xC0_ADDRESS, + D2FxxE4_xC0.Value, + FALSE, + Pcie + ); + GnbLibPciWrite ( + Engine->Type.Port.Address.AddressValue | D2Fxx88_ADDRESS, + AccessWidth32, + &D2Fxx88.Value, + GnbLibGetHeader (Pcie) + ); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Enable passing TLP prefix to IOMMU if IOMMU enabled + * + * + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieInitPortForIommuV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortRegisterRMW ( + Engine, + D2FxxE4_xC1_ADDRESS, + D2FxxE4_xC1_StrapE2EPrefixEn_MASK | D2FxxE4_xC1_StrapExtendedFmtSupported_MASK, + (1 << D2FxxE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << D2FxxE4_xC1_StrapExtendedFmtSupported_OFFSET), + TRUE, + Pcie + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h new file mode 100644 index 0000000000..b6f485fae7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h @@ -0,0 +1,64 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEPORTSERVICESV4_H_ +#define _PCIEPORTSERVICESV4_H_ + + +VOID +PcieSetLinkSpeedCapV4 ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieInitPortForIommuV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h new file mode 100644 index 0000000000..b55c2d4672 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h @@ -0,0 +1,71 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power saving features/services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERSAVINGFEATURESV4_H_ +#define _PCIEPOWERSAVINGFEATURESV4_H_ + +VOID +PciePwrClockGatingV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrPowerDownDdiPllsV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieAcsCapabilityWrapperEnableV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieAcsCapabilityPortEnableV4 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c new file mode 100644 index 0000000000..2d1a9ddb62 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe wrapper services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +PcieSetSsidV4 ( + IN UINT32 Ssid, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySetLinkReversalV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetDdiOwnPhyV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyExecuteReconfigV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Relinquish control to DDI for specific lanes + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetDdiOwnPhyV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + UINT32 LaneBitmap; + UINT8 Slice; + if (PcieLibIsDdiWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + for (Slice = 0; Slice < 4; Slice++) { + if ((LaneBitmap & (1 << (Slice * 4))) != 0) { + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice), + D0F0xE4_WRAP_8040_OwnSlice_MASK, + 1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n"); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SSID + * + * + * @param[in] Ssid SSID + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetSsidV4 ( + IN UINT32 Ssid, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (PcieLibIsPcieWrapper (Wrapper)) { + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS), + Ssid, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable lane reversal + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologySetLinkReversalV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + if (PcieLibIsPcieEngine (EngineList)) { + if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { + PciePortRegisterWriteField ( + EngineList, + D2FxxE4_xC1_ADDRESS, + D2FxxE4_xC1_StrapReverseLanes_OFFSET, + D2FxxE4_xC1_StrapReverseLanes_WIDTH, + 0x1, + FALSE, + Pcie + ); + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h new file mode 100644 index 0000000000..52002ff065 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h @@ -0,0 +1,77 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe wrapper services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEWRAPPERSERVICESV4_H_ +#define _PCIEWRAPPERSERVICESV4_H_ + + +VOID +PcieSetDdiOwnPhyV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +VOID +PcieTopologyExecuteReconfigV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetSsidV4 ( + IN UINT32 Ssid, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySetLinkReversalV4 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h new file mode 100644 index 0000000000..f2bdf75d24 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Init Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87271 $ @e \$Date: 2013-01-31 10:11:23 -0600 (Thu, 31 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEINITLIBV5_H_ +#define _GNBPCIEINITLIBV5_H_ + +VOID +PciePifApplyGangingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerDownV5 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyApplyLaneMuxV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +BOOLEAN +PcieTopologyIsGen3SupportedV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +VOID +PciePwrPowerDownUnusedLanesV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrClockGatingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortsVisibilityControlV5 ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieLinkInitHotplugV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieEnableSlotPowerLimitV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyApplyGangingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyChannelCharacteristicV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyLaneControlV5 ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyReduceLinkWidthV5 ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologyExecuteReconfigV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetLs2ExitTimeV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c new file mode 100644 index 0000000000..bc5023431e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +PciePhyApplyGangingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePhyChannelCharacteristicV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PHY channel characteristic + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePhyChannelCharacteristicV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + /// @todo +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c new file mode 100644 index 0000000000..1f7dc6545d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c @@ -0,0 +1,269 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe PIF initialization routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88079 $ @e \$Date: 2013-02-15 15:28:53 -0600 (Fri, 15 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +PciePifApplyGangingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifPllPowerDownV5 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePifSetLs2ExitTimeV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply PIF ganging for all lanes for given wrapper + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +VOID +PciePifApplyGangingV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 LaneBitmap; + D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011; + D0F0xE4_PIF_0011.Value = 0; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGangingV5 Enter\n"); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsEngineAllocated (EngineList)) { + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList); + switch (LaneBitmap) { + case 0x0003: + D0F0xE4_PIF_0011.Field.X2Lane10 = 0x1; + break; + case 0x000c: + D0F0xE4_PIF_0011.Field.X2Lane32 = 0x1; + break; + case 0x0030: + D0F0xE4_PIF_0011.Field.X2Lane54 = 0x1; + break; + case 0x00c0: + D0F0xE4_PIF_0011.Field.X2Lane76 = 0x1; + break; + case 0x000f: + D0F0xE4_PIF_0011.Field.X4Lane30 = 0x1; + break; + case 0x00f0: + D0F0xE4_PIF_0011.Field.X4Lane74 = 0x1; + break; + case 0x00ff: + D0F0xE4_PIF_0011.Field.X8Lane70 = 0x1; + break; + case 0x0300: + D0F0xE4_PIF_0011.Field.X2Lane98 = 0x1; + break; + case 0x0c00: + D0F0xE4_PIF_0011.Field.X2Lane1110 = 0x1; + break; + case 0x3000: + D0F0xE4_PIF_0011.Field.X2Lane1312 = 0x1; + break; + case 0xc000: + D0F0xE4_PIF_0011.Field.X2Lane1514 = 0x1; + break; + case 0x0f00: + D0F0xE4_PIF_0011.Field.X4Lane118 = 0x1; + break; + case 0xf000: + D0F0xE4_PIF_0011.Field.X4Lane1512 = 0x1; + break; + case 0xff00: + D0F0xE4_PIF_0011.Field.X8Lane158 = 0x1; + break; + case 0xffff: + D0F0xE4_PIF_0011.Field.X16Lane150 = 0x1; + break; + default: + break; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0011_ADDRESS), + D0F0xE4_PIF_0011.Value, + FALSE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGangingV5 Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL powerdown + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllPowerDownV5 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Nibble; + UINT16 NibbleBitmap; + UINT16 PifRegAffress; + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDownV5 Enter\n"); + for (Nibble = 0; Nibble < 4; Nibble++) { + NibbleBitmap = (0xF << (Nibble * 4)); + if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { + PifRegAffress = ((Nibble < 2) ? D0F0xE4_PIF_0012_ADDRESS : D0F0xE4_PIF_0017_ADDRESS) + (Nibble & 0x1); + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, PifRegAffress), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, PifRegAffress), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDownV5 Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program LS2 exit time + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePifSetLs2ExitTimeV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Pif; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTimeV5 Enter\n"); + for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { + PcieRegisterWriteField ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), + D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, + D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, + 0x5, + FALSE, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTimeV5 Exit\n"); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c new file mode 100644 index 0000000000..803d134dd1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c @@ -0,0 +1,147 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init hotplug port + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieLinkInitHotplugV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + PcieLinkInitHotplug (Engine, Pcie); + if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) { + Value = 1; + } else { + Value = 0; + } + PciePortRegisterWriteField ( + Engine, + 0x10, + 3, + 1, + Value, + TRUE, + Pcie + ); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set slot power limit + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to PCIe configuration + */ + + +VOID +PcieEnableSlotPowerLimitV5 ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) { + IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); + Silicon = PcieConfigGetParentSilicon (Engine); + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xC8_ADDRESS, + D0F0xCC_x01_ADDRESS | ((Engine->Type.Port.PortData.DeviceNumber << 3 | Engine->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET), + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0xCC_x01_SetPowEn_OFFSET, + GnbLibGetHeader (Pcie) + ); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c new file mode 100644 index 0000000000..0b2be80970 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c @@ -0,0 +1,198 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe complex initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV5.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +PcieSiliconControlPortsV5 ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieSiliconEnablePortsV5 ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Control port visibility in PCI config space + * + * + * @param[in] Control Control Hide/Unhide ports + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePortsVisibilityControlV5 ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *SiliconList; + SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + while (SiliconList != NULL) { + switch (Control) { + case UnhidePorts: + PcieSiliconControlPortsV5 (UnhidePorts, SiliconList, Pcie); + break; + case HidePorts: + PcieSiliconControlPortsV5 (HidePorts, SiliconList, Pcie); + PcieSiliconEnablePortsV5 (SiliconList, Pcie); + break; + default: + ASSERT (FALSE); + } + SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (SiliconList, DESCRIPTOR_TERMINATE_TOPOLOGY); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Hide/Unhide all ports + * + * + * @param[in] Control Control Hide/Unhide ports + * @param[in] Silicon Pointer to silicon configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +STATIC +PcieSiliconControlPortsV5 ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Value; + Value = (Control == HidePorts) ? ((1 << D0F0xCC_x01_BridgeDis_OFFSET) | (1 << D0F0xCC_x01_CfgDis_OFFSET)) : 0; + EngineList = PcieConfigGetChildEngine (Silicon); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList)) { + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xC8_ADDRESS, + D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.NativeDevNumber << 3 | EngineList->Type.Port.NativeFunNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET), + AccessS3SaveWidth32, + (UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK), + Value, + GnbLibGetHeader (Pcie) + ); + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Hide unused ports + * + * + * + * @param[in] Silicon Pointer to silicon configuration data area + * @param[in] Pcie Pointer to data area up to 256 byte + */ + +VOID +STATIC +PcieSiliconEnablePortsV5 ( + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Silicon); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList)) { + if (!PcieConfigIsSbPcieEngine (EngineList) && + (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && + (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) { + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xC8_ADDRESS, + D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET), + AccessS3SaveWidth32, + (UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK), + ((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)), + GnbLibGetHeader (Pcie) + ); + } + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c new file mode 100644 index 0000000000..9c602e1442 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Lanes enable/disable control + * + * @param[in] Control Lane control action + * @param[in] LaneBitMap Core lanes bitmap + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyLaneControlV5 ( + IN LANE_CONTROL Control, + IN UINT32 LaneBitMap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8029_STRUCT D0F0xE4_WRAP_8029; + D0F0xE4_WRAP_8029.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8029_ADDRESS), + Pcie + ); + + if (Control == EnableLanes) { + D0F0xE4_WRAP_8029.Value |= LaneBitMap; + } else if (Control == DisableLanes) { + D0F0xE4_WRAP_8029.Value &= (~LaneBitMap); + } + D0F0xE4_WRAP_8029.Value &= ((1 << Wrapper->NumberOfLanes) - 1); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8029_ADDRESS), + D0F0xE4_WRAP_8029.Value, + TRUE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Reduce link width + * + * + * @param[in] LinkWidth Link width + * @param[in] Engine Pointer to Engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyReduceLinkWidthV5 ( + IN UINT8 LinkWidth, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *Wrapper; + UINT32 LinkReversed; + UINT8 DeltaLinkWidthBitmap; + UINT32 LanesToDisable; + Wrapper = PcieConfigGetParentWrapper (Engine); + LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie); + + DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1; + LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth))); + + PcieTopologyLaneControlV5 ( + DisableLanes, + LanesToDisable, + Wrapper, + Pcie + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c new file mode 100644 index 0000000000..89547bfd95 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c @@ -0,0 +1,184 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe topology initialization service procedures. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbRegistersCommonV2.h" +#include "GnbSmuInitLibV7.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +UINT8 LaneMuxSelectorArrayV5[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if lane topology supports Gen3 + * + * Check if more that one link mapped to single PIF slice + * + * @param[in] Wrapper Pointer to wrapper config descriptor + */ + +BOOLEAN +PcieTopologyIsGen3SupportedV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + UINT8 LaneNibbleArray [4]; + UINT32 LaneBitmap; + UINT8 Nibble; + UINT8 NibbleBitmap; + PCIe_ENGINE_CONFIG *Engine; + + + LibAmdMemFill (&LaneNibbleArray[0], 0x00, sizeof (LaneNibbleArray), PcieConfigGetStdHeader (Wrapper)); + Engine = PcieConfigGetChildEngine (Wrapper); + while (Engine != NULL) { + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Engine); + for (Nibble = 0; Nibble < 4; Nibble++) { + NibbleBitmap = (0xF << (Nibble * 4)); + if ((LaneBitmap & NibbleBitmap) != 0) { + if (++LaneNibbleArray [Nibble] > 1) { + return FALSE; + } + } + } + Engine = PcieLibGetNextDescriptor (Engine); + } + return TRUE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieTopologyExecuteReconfigV5 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + PCIe_SILICON_CONFIG *Silicon; + DEV_OBJECT DevObject; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Enter\n"); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x2; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + Silicon = PcieConfigGetParentSilicon (Wrapper); + DevObject.StdHeader = GnbLibGetHeader (Pcie); + DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); + DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue; + GnbSmuServiceRequestV7 ( + &DevObject, + 25, + 0, + 0 + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Exit\n"); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c new file mode 100644 index 0000000000..edf877264b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c @@ -0,0 +1,376 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Configure Max Payload + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMaxPayload.h" +#include "OptionGnb.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + UINT8 MaxPayload; +} PCIE_MAX_PAYLOAD_DATA; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +SCAN_STATUS +PcieGetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +SCAN_STATUS +PcieSetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +AGESA_STATUS +PciePayloadBlackListFeature ( + IN PCI_ADDR Device, + IN UINT8 *MaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieMaxPayloadInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine maximum payload size for PCIe segment + * + * Scan through all link in segment to determine maximum payload by EPs. + * + * @param[in] DownstreamPort PCI address of PCIe port + * @param[in] EngineMaxPayload MaxPayload supported by the engine + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +PcieSetMaxPayload ( + IN PCI_ADDR DownstreamPort, + IN UINT8 EngineMaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_MAX_PAYLOAD_DATA PcieMaxPayloadData; + + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayload for Device = %d:%d:%d\n", + DownstreamPort.Address.Bus, + DownstreamPort.Address.Device, + DownstreamPort.Address.Function + ); + PcieMaxPayloadData.MaxPayload = EngineMaxPayload; + PcieMaxPayloadData.ScanData.StdHeader = StdHeader; + PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); + PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadExit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieGetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; + PCIE_DEVICE_TYPE DeviceType; + UINT32 Value; + UINT8 PcieCapPtr; + UINT8 DeviceMaxPayload; + + PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieGetMaxPayloadCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), + AccessWidth32, + &Value, + ScanData->StdHeader + ); + DeviceMaxPayload = (UINT8) (Value & 0x7); + PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value); + if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) { + PcieMaxPayloadData->MaxPayload = DeviceMaxPayload; + } + } + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + break; + default: + break; + } + return SCAN_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure the Max Payload setting to all devices in the PCIe Segment + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieSetMaxPayloadCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; + PCIE_DEVICE_TYPE DeviceType; + UINT8 PcieCapPtr; + + PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function, + PcieMaxPayloadData->MaxPayload + ); + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER), + AccessWidth32, + ~(UINT32) (0x7 << 5), + ((UINT32)PcieMaxPayloadData->MaxPayload << 5), + ScanData->StdHeader + ); + } + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + break; + default: + break; + } + return SCAN_SUCCESS; +} + +UINT16 PayloadBlacklistDeviceTable[] = { + 0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Max_Payload_Size Black List + * + * + * + * @param[in] Device PCI_ADDR of PCIe Device to evaluate + * @param[in] MaxPayload Pointer to Max_Payload_Size value + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PciePayloadBlackListFeature ( + IN PCI_ADDR Device, + IN UINT8 *MaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TargetDeviceId; + UINTN i; + UINT32 DeviceId; + UINT32 VendorId; + + GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); + for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { + VendorId = PayloadBlacklistDeviceTable[i]; + DeviceId = PayloadBlacklistDeviceTable[i + 1]; + if (VendorId == (UINT16)TargetDeviceId) { + if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) { + *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2]; + } + } + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMaxPayloadInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_MAXPAYLOAD_SERVICE *PcieMaxPayloadProtocol; + UINT8 EngineMaxPayload; + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + + + + if ((GnbBuildOptions.CfgMaxPayloadEnable != 0) && + (!PcieConfigIsSbPcieEngine (Engine)) && + (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) { + EngineMaxPayload = MAX_PAYLOAD; + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Status = GnbLibLocateService (GnbPcieMaxPayloadService, Complex->SocketId, (VOID **)&PcieMaxPayloadProtocol, GnbLibGetHeader (Pcie)); + if (Status == AGESA_SUCCESS) { + EngineMaxPayload = PcieMaxPayloadProtocol->SetMaxPayload (Engine); + } + PcieSetMaxPayload (Engine->Type.Port.Address, EngineMaxPayload, GnbLibGetHeader (Pcie)); + } +} + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to configure MaxPayloadSize on PCIE interface + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieMaxPayloadInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMaxPayloadInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h new file mode 100644 index 0000000000..d36724400e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Configure Max Payload + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEMAXPAYLOAD_H_ +#define _PCIEMAXPAYLOAD_H_ + +VOID +PcieSetMaxPayload ( + IN PCI_ADDR DownstreamPort, + IN UINT8 EngineMaxPayload, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h new file mode 100644 index 0000000000..490d5eb348 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h @@ -0,0 +1,51 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe training library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIETRAININGV2_H_ +#define _GNBPCIETRAININGV2_H_ + +#include "PcieTrainingV2.h" +#include "PcieWorkaroundsV2.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c new file mode 100644 index 0000000000..36044ac885 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c @@ -0,0 +1,801 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link training + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85361 $ @e \$Date: 2013-01-07 11:15:28 -0600 (Mon, 07 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbPcieTrainingV2.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Set link State + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] State State to set + * @param[in] UpdateTimeStamp Update time stamp + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieTrainingSetPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIE_LINK_TRAINING_STATE State, + IN BOOLEAN UpdateTimeStamp, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + CurrentEngine->Type.Port.State = (UINT8) State; + if (UpdateTimeStamp) { + TimeStamp = PcieTimerGetTimeStamp (Pcie); + CurrentEngine->Type.Port.TimeStamp = TimeStamp; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set state for all engines connected to same reset ID + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Pointer to Reset Id + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +STATIC VOID +PcieSetResetStateOnEngines ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 ResetId; + ResetId = *(UINT8 *)Buffer; + if (Engine->Type.Port.PortData.ResetId == ResetId && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie); + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, + AccessWidth32, + (UINT32) ~DxFxx68_LinkDis_MASK, + 1 << DxFxx68_LinkDis_OFFSET, + GnbLibGetHeader (Pcie) + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Assert GPIO port reset. + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingAssertReset ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SLOT_RESET_INFO ResetInfo; + ResetInfo.ResetControl = AssertSlotReset; + ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; + LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieSetResetStateOnEngines, + (VOID *)&CurrentEngine->Type.Port.PortData.ResetId, + Pcie + ); + AgesaPcieSlotResetControl (0, &ResetInfo); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check for reset duration + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +STATIC VOID +PcieTrainingCheckResetDuration ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) { + PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Deassert GPIO port reset. + * + * Transition to LinkStateResetDuration state + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Platform configuration + * + */ +STATIC VOID +PcieTrainingDeassertReset ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SLOT_RESET_INFO ResetInfo; + ResetInfo.ResetControl = DeassertSlotReset; + ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; + LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); + AgesaPcieSlotResetControl (0, &ResetInfo); + GnbLibPciRMW ( + CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, + AccessWidth32, + (UINT32) ~DxFxx68_LinkDis_MASK, + 0 << DxFxx68_LinkDis_OFFSET, + GnbLibGetHeader (Pcie) + ); + PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check for after reset deassertion timeout + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCheckResetTimeout ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) { + PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Release training + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingRelease ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkTrainingState; + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (CurrentEngine), + WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), + D0F0xE4_WRAP_0800_HoldTraining_OFFSET, + D0F0xE4_WRAP_0800_HoldTraining_WIDTH, + 0, + FALSE, + Pcie + ); + if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + LinkTrainingState = LinkStateCompliance; + } else { + LinkTrainingState = LinkStateDetectPresence; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Detect presence of any EP on the link + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingDetectPresence ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[4]; + UINT32 TimeStamp; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); + if (LinkHwStateHistory[0] > 4) { + PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); + return; + } + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) { + PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); + } +} + +UINT8 FailPattern1 [] = {0x2a, 0x6}; +UINT8 FailPattern2 [] = {0x2a, 0x9}; +UINT8 FailPattern3 [] = {0x2a, 0xb}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Detect Link State + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingDetectLinkState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkHwStateHistory[16]; + UINT32 TimeStamp; + UINT8 LinkTrainingState; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie); + if (LinkHwStateHistory[0] == 0x10) { + PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie); + return; + }; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) { + LinkTrainingState = LinkStateTrainingFail; + PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie); + if (LinkHwStateHistory[0] == 0x7) { + LinkTrainingState = LinkStateCompliance; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) { + LinkTrainingState = LinkStateBrokenLane; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) { + LinkTrainingState = LinkStateGen2Fail; + } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern3, sizeof (FailPattern3))) { + LinkTrainingState = LinkStateGen2Fail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Broken Lane + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +STATIC VOID +PcieTrainingBrokenLineV2 ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CurrentLinkWidth; + UINT8 LinkTrainingState; + CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); + if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { + CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; + PcieTopologyReduceLinkWidthV5 (CurrentLinkWidth, CurrentEngine, Pcie); + LinkTrainingState = LinkStateResetAssert; + PutEventLog ( + AGESA_WARNING, + GNB_EVENT_BROKEN_LANE_RECOVERY, + CurrentEngine->Type.Port.Address.AddressValue, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } else { + LinkTrainingState = LinkStateGen2Fail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link fail because device does not support Gen2 + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +STATIC VOID +PcieTrainingGen2Fail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 LinkTrainingState; + if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); + CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; + PcieLinkSafeMode (CurrentEngine, Pcie); + LinkTrainingState = LinkStateResetAssert; + PutEventLog ( + AGESA_WARNING, + GNB_EVENT_BROKEN_LANE_RECOVERY, + CurrentEngine->Type.Port.Address.AddressValue, + 0, + 0, + 0, + GnbLibGetHeader (Pcie) + ); + } else { + LinkTrainingState = LinkStateTrainingFail; + } + PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Link in L0 + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieCheckLinkL0 ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Check if link fail because device does not support Gen X + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCheckVcoNegotiation ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + DxFxx128_STRUCT DxFxx128; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxFxx128_ADDRESS, AccessWidth32, &DxFxx128, GnbLibGetHeader (Pcie)); + if (DxFxx128.Field.VcNegotiationPending == 0) { + UINT16 NumberOfPhyLane; + NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine); + if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) { + // Limit exposure of workaround to x8 and x16 port. + PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie); + } else { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); + } + return; + } + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) { + PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if for GFX workaround condition + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingGfxWorkaround ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 TimeStamp; + GFX_WORKAROUND_STATUS GfxWorkaroundStatus; + TimeStamp = PcieTimerGetTimeStamp (Pcie); + + GfxWorkaroundStatus = PcieGfxCardWorkaroundV2 (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie)); + switch (GfxWorkaroundStatus) { + case GFX_WORKAROUND_DEVICE_NOT_READY: + if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= (3 * 1000000)) { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); + } + break; + case GFX_WORKAROUND_SUCCESS: + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie); + break; + case GFX_WORKAROUND_RESET_DEVICE: + if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) { + CurrentEngine->Type.Port.GfxWrkRetryCount++; + PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie); + } else { + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie); + } + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Retrain link + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingRetrainLink ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GnbLibPciRMW ( + CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, + AccessWidth32, + (UINT32) ~DxFxx68_RetrainLink_MASK, + 1 << DxFxx68_RetrainLink_OFFSET, + GnbLibGetHeader (Pcie) + ); + PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Training fail on this port + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingFail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Links training success + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingSuccess ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); + GnbLibPciRMW ( + CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, + AccessWidth32, + (UINT32) ~DxFxx68_LinkBWManagementStatus_MASK, + 1 << DxFxx68_LinkBWManagementStatus_OFFSET, + GnbLibGetHeader (Pcie) + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Links in compliance + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCompliance ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCie EP not present + * + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingNotPresent ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) { + } else { + PcieRegisterWriteField ( + PcieConfigGetParentWrapper (CurrentEngine), + WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId), + D0F0xE4_WRAP_0800_HoldTraining_OFFSET, + D0F0xE4_WRAP_0800_HoldTraining_WIDTH, + 1, + FALSE, + Pcie + ); + } + PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Final state. Port training completed. + * + * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus + * + * @param[in] CurrentEngine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieTrainingCompleted ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Training state handling + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Indicate if engine in non final state + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieTrainingPortCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + BOOLEAN *TrainingComplete; + TrainingComplete = (BOOLEAN *) Buffer; + if (Engine->Type.Port.State < Pcie->TrainingExitState) { + *TrainingComplete = FALSE; + } else { + return; + } + switch (Engine->Type.Port.State) { + case LinkStateResetAssert: + PcieTrainingAssertReset (Engine, Pcie); + break; + case LinkStateResetDuration: + PcieTrainingCheckResetDuration (Engine, Pcie); + break; + case LinkStateResetExit: + PcieTrainingDeassertReset (Engine, Pcie); + break; + case LinkTrainingResetTimeout: + PcieTrainingCheckResetTimeout (Engine, Pcie); + break; + case LinkStateReleaseTraining: + PcieTrainingRelease (Engine, Pcie); + break; + case LinkStateDetectPresence: + PcieTrainingDetectPresence (Engine, Pcie); + break; + case LinkStateDetecting: + PcieTrainingDetectLinkState (Engine, Pcie); + break; + case LinkStateBrokenLane: + PcieTrainingBrokenLineV2 (Engine, Pcie); + break; + case LinkStateGen2Fail: + PcieTrainingGen2Fail (Engine, Pcie); + break; + case LinkStateL0: + PcieCheckLinkL0 (Engine, Pcie); + break; + case LinkStateVcoNegotiation: + PcieTrainingCheckVcoNegotiation (Engine, Pcie); + break; + case LinkStateRetrain: + PcieTrainingRetrainLink (Engine, Pcie); + break; + case LinkStateTrainingFail: + PcieTrainingFail (Engine, Pcie); + break; + case LinkStateGfxWorkaround: + PcieTrainingGfxWorkaround (Engine, Pcie); + break; + case LinkStateTrainingSuccess: + PcieTrainingSuccess (Engine, Pcie); + break; + case LinkStateCompliance: + PcieTrainingCompliance (Engine, Pcie); + break; + case LinkStateDeviceNotPresent: + PcieTrainingNotPresent (Engine, Pcie); + break; + case LinkStateTrainingCompleted: + PcieTrainingCompleted (Engine, Pcie); + break; + default: + break; + } + +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Main link training procedure + * + * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/ + * LinkStateTrainingSuccess + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PcieTraining ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN TrainingComplete; + + IDS_PERF_TIMESTAMP (TP_BEGINGNBPCIETRAINING, GnbLibGetHeader (Pcie)); + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n"); + do { + TrainingComplete = TRUE; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieTrainingPortCallback, + &TrainingComplete, + Pcie + ); + } while (!TrainingComplete); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status); + IDS_PERF_TIMESTAMP (TP_ENDGNBPCIETRAINING, GnbLibGetHeader (Pcie)); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h new file mode 100644 index 0000000000..c31f73aa47 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h @@ -0,0 +1,63 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link training + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIETRAINING_H_ +#define _PCIETRAINING_H_ + + +AGESA_STATUS +PcieTraining ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingSetPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIE_LINK_TRAINING_STATE State, + IN BOOLEAN UpdateTimeStamp, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c new file mode 100644 index 0000000000..159ea3e699 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c @@ -0,0 +1,375 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various workarounds + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbRegistersCommonV2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieConfigureBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieFreeBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +GFX_WORKAROUND_STATUS +PcieDeskewWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +GFX_WORKAROUND_STATUS +PcieNvWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieProgramCpuMmio ( + OUT UINT32 *SaveValues, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieRestoreCpuMmio ( + IN UINT32 *RestoreValues, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +PcieIsDeskewCardDetected ( + IN UINT16 DeviceId + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * + * + * @param[in] Port PCI address of the port + * @param[in] StdHeader Standard configuration header + * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status + */ +GFX_WORKAROUND_STATUS +PcieGfxCardWorkaroundV2 ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_WORKAROUND_STATUS Status; + UINT16 DeviceId; + UINT16 VendorId; + UINT8 DevClassCode; + UINT32 SaveValueData[2]; + PCI_ADDR Ep; + + Status = GFX_WORKAROUND_SUCCESS; + + Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0); + if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) { + GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader); + Status = GFX_WORKAROUND_DEVICE_NOT_READY; + if (DeviceId != 0xffff) { + GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader); + if (VendorId != 0xffff) { + GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader); + Status = GFX_WORKAROUND_SUCCESS; + if (DevClassCode == 3) { + PcieProgramCpuMmio (SaveValueData, StdHeader); + if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) { + Status = PcieDeskewWorkaround (Ep, StdHeader); + } else if (VendorId == 0x10DE) { + Status = PcieNvWorkaround (Ep, StdHeader); + } + PcieRestoreCpuMmio (SaveValueData, StdHeader); + } + } + } + PcieFreeBridgeResources (Port, StdHeader); + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * RV370/RV380 Deskew workaround + * + * + * + * @param[in] Device Pcie Address + * @param[in] StdHeader Standard configuration header + */ +GFX_WORKAROUND_STATUS +PcieDeskewWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN MmioBase; + UINT16 MmioData1; + UINT32 MmioData2; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return GFX_WORKAROUND_SUCCESS; + } + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , (UINT32)~BIT1, BIT1, StdHeader); + GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); + GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); + if (MmioData1 == 0xb700) { + GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader); + GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader); + if (MmioData2 == 0x13) { + GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader); + if (MmioData2 & BIT8) { + return GFX_WORKAROUND_RESET_DEVICE; + } + } + } + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, (UINT32)~BIT1, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); + + return GFX_WORKAROUND_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * NV43 card workaround (lost SSID) + * + * + * + * @param[in] Device Pcie Address of NV43 card. + * @param[in] StdHeader Standard configuration header + */ +GFX_WORKAROUND_STATUS +PcieNvWorkaround ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceSSID; + UINTN MmioBase; + UINT32 MmioData3; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return GFX_WORKAROUND_SUCCESS; + } + GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader); + GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader); + GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader); + if (DeviceSSID != MmioData3) { + GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader); + } + GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader); + return GFX_WORKAROUND_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate temporary resources for Pcie P2P bridge + * + * + * + * @param[in] Port Pci Address of Port to initialize. + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +PcieConfigureBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + UINT32 MmioBase; + + MmioBase = UserOptions.CfgTempPcieMmioBaseAddress; + if (MmioBase == 0) { + return AGESA_WARNING; + } + Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16); + GnbLibPciWrite (Port.AddressValue | DxFxx18_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = MmioBase + (MmioBase >> 16); + GnbLibPciWrite (Port.AddressValue | DxFxx20_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = 0x000fff0; + GnbLibPciWrite (Port.AddressValue | DxFxx24_ADDRESS, AccessWidth32, &Value, StdHeader); + Value = 0x2; + GnbLibPciWrite (Port.AddressValue | D0F0x04_ADDRESS, AccessWidth8, &Value, StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Free temporary resources for Pcie P2P bridge + * + * + * + * @param[in] Port Pci Address of Port to clear resource allocation. + * @param[in] StdHeader Standard configuration header + */ +VOID +PcieFreeBridgeResources ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + + Value = 0; + GnbLibPciWrite (Port.AddressValue | D0F0x04_ADDRESS, AccessWidth8, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxFxx18_ADDRESS, AccessWidth32, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxFxx20_ADDRESS, AccessWidth32, &Value, StdHeader); + GnbLibPciWrite (Port.AddressValue | DxFxx24_ADDRESS, AccessWidth32, &Value, StdHeader); + +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Save CPU MMIO register + * + * + * + * @param[out] UINT32 SaveValues + * @param[in] StdHeader Standard configuration header + * + */ +VOID +PcieProgramCpuMmio ( + OUT UINT32 *SaveValues, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + //Save CPU MMIO Register + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader); + + //Write Temp Pcie MMIO to CPU + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader); + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Restore CPU MMIO register + * + * + * + * @param[in] PCIe_PLATFORM_CONFIG Pcie + * @param[in] StdHeader Standard configuration header + */ +VOID +PcieRestoreCpuMmio ( + IN UINT32 *RestoreValues, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + //Restore CPU MMIO Register + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader); + GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if card required test for deskew workaround + * + * + * + * @param[in] DeviceId Device ID + */ + +BOOLEAN +PcieIsDeskewCardDetected ( + IN UINT16 DeviceId + ) +{ + if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) || + (DeviceId == 0x3E50) || (DeviceId == 0x3E54) || + ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) { + return TRUE; + } + return FALSE; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h new file mode 100644 index 0000000000..3fefdd2a19 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various workarounds + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIEWORKAROUNDSV2_H_ +#define _PCIEWORKAROUNDSV2_H_ + +GFX_WORKAROUND_STATUS +PcieGfxCardWorkaroundV2 ( + IN PCI_ADDR Port, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c new file mode 100644 index 0000000000..43705063f7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c @@ -0,0 +1,169 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB Single Socket Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbLib.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Host bridge PCI Address + * + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + * @retval PCI address of GNB for a given socket/silicon. + */ + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Gnb; + Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + return Gnb; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bus range decoded by GNB + * + * Final bus allocation can not be assumed until AmdInitMid + * + * @param[in] GnbHandle GNB handle + * @param[out] StartBusNumber Beginning of the Bus Range + * @param[out] EndBusNumber End of the Bus Range + * @param[in] StdHeader Standard configuration header + * @retval Status + */ + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *StartBusNumber = 0x0; + *EndBusNumber = 0xff; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link to which GNB connected to + * + * + * @param[in] GnbHandle GNB handle + * @param[out] LinkId Link to which GNB connected to + * @param[in] StdHeader Standard configuration header + * @retval Status + */ + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + *LinkId = 0x00; + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c new file mode 100644 index 0000000000..209da2394d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT32 +SbGetSbIoApicBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +SbGetSbMmioBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +SbGetAlinkIoAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + *Get SB IOAPIC Base Address + * + * + * @param[in] StdHeader Standard configuration header + * @retval ApicBaseAddress + */ +UINT32 +SbGetSbIoApicBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ApicBaseAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader); + return ApicBaseAddress & 0xffffffe0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Get SB MMIO Base Address + * + * + * @param[in] StdHeader Standard configuration header + * @retval MMIO base address + */ +UINT32 +SbGetSbMmioBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MmioBaseAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader); + return MmioBaseAddress & 0xfffffffc; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Alink config address + * + * @param[in] StdHeader Standard configuration header + * @retval AlinkPortAddress + */ +/*----------------------------------------------------------------------------------------*/ + +UINT16 +SbGetAlinkIoAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT16 AlinkPortAddress; + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader); + return AlinkPortAddress; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h new file mode 100644 index 0000000000..516b77ac3c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBSBLIB_H_ +#define _GNBSBLIB_H_ + +#include "GnbPcie.h" + +UINT32 +SbGetSbIoApicBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +SbGetSbMmioBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +SbGetAlinkIoAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +SbPcieInitAspm ( + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +SbPcieLinkAspmControl ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c new file mode 100644 index 0000000000..cc8cbf873c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB-SB link procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbSbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable/Disable ASPM on GNB-SB link + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +AGESA_STATUS +SbPcieLinkAspmControl ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_ASPM_TYPE Aspm; + + Aspm = Engine->Type.Port.PortData.LinkAspm; + + Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie)); + if (Status != AGESA_SUCCESS) { + return AGESA_UNSUPPORTED; + } + + excel950_fun4 (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init SB ASPM. + * Enable ASPM states on SB + * + * + * @param[in] Aspm ASPM bitmap. + * @param[in] StdHeader Standard configuration header + */ +/*----------------------------------------------------------------------------------------*/ + +AGESA_STATUS +SbPcieInitAspm ( + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 AlinkPort; + + AlinkPort = SbGetAlinkIoAddress (StdHeader); + ASSERT (AlinkPort != 0); + if (AlinkPort == 0) { + return AGESA_UNSUPPORTED; + } + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader); + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader); + GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader); + GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader); + return AGESA_SUCCESS; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c new file mode 100644 index 0000000000..91130298f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c @@ -0,0 +1,198 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "OptionGnb.h" +#include "GnbSmuInitLibV7.h" +#include "heapManager.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#ifndef TYPE_D0F0xBC + #define TYPE_D0F0xBC 0x4 +#endif + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbSmuInitLibV7139_fun0 ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 *ScsDataPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + DEV_OBJECT DevObject; + AGESA_STATUS Status; + + IDS_PERF_TIMESTAMP (TP_BEGINGNBLOADSCSDATA, StdHeader); + + Status = AGESA_SUCCESS; + if (GnbBuildOptions.CfgScsSupport == TRUE) { + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuInitLibV7139_fun0 Enter\n"); + //Check input parameters + ASSERT ((ScsDataPtr != NULL) && (StdHeader != NULL)); + if ((ScsDataPtr == NULL) || (StdHeader == NULL)) { + return AGESA_ERROR; + } + + //Verify the SCS block signature + ASSERT (*(UINT32 *)ScsDataPtr == GnbSmuInitLibV7136_macro0); + if (*(UINT32 *)ScsDataPtr != GnbSmuInitLibV7136_macro0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Verify SCS Binary fail\n", ScsDataPtr); + return AGESA_ERROR; + } + + //Load SCS block + IDS_HDT_CONSOLE (GNB_TRACE, "Load SCS @%08x\n", ScsDataPtr); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = StdHeader; + GnbSmuServiceRequestV7 (&DevObject, 0x50, (UINT32) (UINTN) ScsDataPtr, 0); + + //Get SCS result and save to Heap + IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result\n", ScsDataPtr); + Status = GnbSmuInitLibV7139_fun1 (GnbHandle, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result %s\n", (Status == AGESA_SUCCESS) ? "Success" : "Fail"); + } + + IDS_PERF_TIMESTAMP (TP_ENDGNBLOADSCSDATA, StdHeader); + return Status; +} + +AGESA_STATUS +GnbSmuInitLibV7139_fun1 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 ScsResultAddr; + UINT32 *ScsResultBuf; + UINT32 NumApmWeights; + AGESA_STATUS Status; + DEV_OBJECT DevObject; + GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol; + ALLOCATE_HEAP_PARAMS AllocateHeapParams; + + Status = AGESA_SUCCESS; + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = StdHeader; + DevObject.DevPciAddress = GnbGetHostPciAddress (GnbHandle); + + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + return Status; + } + + //Get the command result (A pointer to SMURAM) + ScsResultAddr = 0; + GnbUraGet (&DevObject, TRxSmuIntArgument, &ScsResultAddr); + IDS_HDT_CONSOLE (GNB_TRACE, "SMURAMAddr %08x ", ScsResultAddr); + ASSERT (ScsResultAddr != 0); + + + Status = GnbRegisterAccessProtocol->Read (GnbHandle, 0x4, ScsResultAddr + offsetof (SMU_RAM_CPU_INFO, CountApmWeights), &NumApmWeights, 0, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NumApmWeights %d\n", NumApmWeights); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + return Status; + } + + //Allocate heap for store the result + AllocateHeapParams.BufferHandle = AMD_SCS_SMU_RAM_INFO; + AllocateHeapParams.Persist = HEAP_LOCAL_CACHE; + AllocateHeapParams.BufferPtr = NULL; + AllocateHeapParams.RequestedBufferSize = sizeof (SMU_RAM_CPU_INFO) + SIZE_OF_APMWEIGHTS * NumApmWeights; + Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + return Status; + } + + ScsResultBuf = (UINT32 *)AllocateHeapParams.BufferPtr; + //Get the result point by RxSmuIntArgument from SMURAM + for (i = 0; i < (sizeof (SMU_RAM_CPU_INFO) / sizeof (UINT32) + NumApmWeights); i++) { + Status = GnbRegisterAccessProtocol->Read (GnbHandle, 0x4, ScsResultAddr, &ScsResultBuf[i], 0, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + break; + } + ScsResultAddr += sizeof (UINT32); + } + + if (Status != AGESA_SUCCESS) { + IDS_HDT_CONSOLE (GNB_TRACE, "Fail on get SCS Result @%08x\n", ScsResultAddr); + HeapDeallocateBuffer (AMD_SCS_SMU_RAM_INFO, StdHeader); + } else { + } + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c new file mode 100644 index 0000000000..2f4038979e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c @@ -0,0 +1,330 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85506 $ @e \$Date: 2013-01-08 15:38:33 -0600 (Tue, 08 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbSmuInitLibV7.h" +#include "heapManager.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSMULIBV7_GNBSMUINITLIBV7_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define SMC_RAM_START_ADDR 0x20000ul +#ifndef INVALID_SMU_MSG + #define INVALID_SMU_MSG 0xFF +#endif + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbSmuServiceRequestV7S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request + * + * + * @param[in] DevObject Pointer to Device object + * @param[in] RequestId Request ID + * @param[in] RequestArgument Request Argument + * @param[in] AccessFlags See GNB_ACCESS_FLAGS_* definitions + */ + +VOID +GnbSmuServiceRequestV7 ( + IN DEV_OBJECT *DevObject, + IN UINT8 RequestId, + IN UINT32 RequestArgument, + IN UINT32 AccessFlags + ) +{ + UINT32 BFIntDone; + UINT32 BFIntToggle; + UINT32 BFIntAck; + UINT32 RxSmuIntArgument; + URA_TUPLE UraTuple[2]; + UINT32 IsMsgValid; + + IsMsgValid = FALSE; + if (RequestId != INVALID_SMU_MSG) { + IsMsgValid = TRUE; + } + + if (IsMsgValid == TRUE) { + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV7 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Service Request %d\n", RequestId); + IDS_HDT_CONSOLE (NB_MISC, " Service Request Argument 0x%x\n", RequestArgument); + + if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) { + SMU_MSG_CONTEXTV7 SmuMsgContext; + SmuMsgContext.GnbPciAddress.AddressValue = DevObject->DevPciAddress.AddressValue; + SmuMsgContext.RequestId = RequestId; + SmuMsgContext.RequestArgument = RequestArgument; + S3_SAVE_DISPATCH (DevObject->StdHeader, GnbSmuServiceRequestV7S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext); + } + + do { + GnbUraGet (DevObject, TBfxSmuIntDone, &BFIntDone); + } while (BFIntDone == 0x0); + + RxSmuIntArgument = RequestArgument; + GnbUraSet (DevObject, TRxSmuIntArgument, &RxSmuIntArgument); + + GnbUraGet (DevObject, TBfxSmuIntToggle, &BFIntToggle); + UraTuple[0].Token = TBfxSmuIntToggle; + UraTuple[0].Value = ~BFIntToggle; + UraTuple[1].Token = TBfxSmuServiceIndex; + UraTuple[1].Value = RequestId; + GnbUraCombinedSet (DevObject, TRxSmuIntReq, &UraTuple[0], 2); + + do { + GnbUraGet (DevObject, TBfxSmuIntAck, &BFIntAck); + } while (BFIntAck == 0x0); + + do { + GnbUraGet (DevObject, TBfxSmuIntDone, &BFIntDone); + } while (BFIntDone == 0x0); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV7 Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request for S3 script + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context length + * @param[in] Context Pointer to Context + */ + +VOID +GnbSmuServiceRequestV7S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ) +{ + SMU_MSG_CONTEXTV7 *SmuMsgContext; + DEV_OBJECT DevObject; + SmuMsgContext = (SMU_MSG_CONTEXTV7 *) Context; + + DevObject.StdHeader = StdHeader; + DevObject.DevPciAddress = SmuMsgContext->GnbPciAddress; + DevObject.GnbHandle = GnbGetHandle (StdHeader); + + GnbSmuServiceRequestV7 (&DevObject, SmuMsgContext->RequestId, SmuMsgContext->RequestArgument, 0); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware download + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Firmware Pointer t0 firmware + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbSmuFirmwareLoadV7 ( + IN GNB_HANDLE *GnbHandle, + IN FIRMWARE_HEADER_V7 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT32 BfxSmuProtectedMode; + UINT32 BfxSmuBootSeqDone; + UINT32 BfxSmuAuthDone; + UINT32 BfxSmuAuthPass; + UINT32 RxSmuAuthVector; + UINT32 BfxSmuRstReg; + UINT32 BfxSmuCkDisable; + UINT32 BfxSmuInterruptsEnabled; + UINT32 RxSmuRamStartAddr; + GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol; + PCI_ADDR GnbPciAddress; + DEV_OBJECT DevObject; + URA_TUPLE UraTuple; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Firmware version 0x%x\n", Firmware->Version); + IDS_OPTION_HOOK (IDS_REPORT_SMU_FW_VERSION, &(Firmware->Version), StdHeader); + + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = StdHeader; + DevObject.DevPciAddress.AddressValue = GnbPciAddress.AddressValue; + + IDS_HDT_CONSOLE (GNB_TRACE, "Step 2 & 10: make sure Rom firmware sequence is done\n"); + // Step 2, 10, make sure Rom firmware sequence is done + do { + GnbUraGet (&DevObject, TBfxSmuBootSeqDone, &BfxSmuBootSeqDone); + } while (BfxSmuBootSeqDone == 0); + + IDS_HDT_CONSOLE (GNB_TRACE, "Step 1: check if firmware running in protected mode\n"); + // Step 1, check if firmware running in protected mode + GnbUraGet (&DevObject, TBfxSmuProtectedMode, &BfxSmuProtectedMode); + if (BfxSmuProtectedMode == 0) { + // Step3, Clear firmware interrupt flags + IDS_HDT_CONSOLE (GNB_TRACE, "Step 3: Clear firmware interrupt flags\n"); + //IDS_HDT_CONSOLE (GNB_TRACE, "Read register data 0x%x\n", FIRMWARE_FLAGS.Value); + BfxSmuInterruptsEnabled = 0; + GnbUraSet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); + } + + //Step 4, 11, Assert SMU reset + IDS_HDT_CONSOLE (GNB_TRACE, "Step 4, 11: Assert SMU reset\n"); + BfxSmuRstReg = 1; + GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); + + // Step5, 12, Load firmware + IDS_HDT_CONSOLE (GNB_TRACE, "Step5, 12, Load firmware\n"); + // 4 means byte length of next address during firmware download + UraTuple.StepLength = 4; + UraTuple.Value = (UINT32) ((UINTN) (Firmware)); + GnbUraCombinedSet (&DevObject, TRxSmuRamStartAddr | GNB_URA_STREAM_SET, &UraTuple, (Firmware->ImageSize >> 2)); + + if (BfxSmuProtectedMode == 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Step6, write jmp to RAM firmware\n"); + //Step 6, Write jmp to RAM firmware + RxSmuRamStartAddr = 0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderSize) >> 2); + GnbUraSet (&DevObject, TRxSmuRomStartAddr, &RxSmuRamStartAddr); + } else { + //Step 13, Clear authentification done + IDS_HDT_CONSOLE (GNB_TRACE, "Step 13, Clear authentification done\n"); + BfxSmuAuthDone = 0; + GnbUraSet (&DevObject, TBfxSmuAuthDone, &BfxSmuAuthDone); + } + + // Step 7, 14 Enable SMU clock + IDS_HDT_CONSOLE (GNB_TRACE, "Step 7, 14 Enable SMU clock\n"); + BfxSmuCkDisable = 0; + GnbUraSet (&DevObject, TBfxSmuCkDisable, &BfxSmuCkDisable); + + //Step 8, 15, Deassert SMU reset + IDS_HDT_CONSOLE (GNB_TRACE, "Step 8, 15, Deassert SMU reset\n"); + BfxSmuRstReg = 0; + GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); + + if (BfxSmuProtectedMode == 1) { + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init authentication vector\n"); + // Step 16, Wait for rom firmware init authentication vector + IDS_HDT_CONSOLE (GNB_TRACE, "Step 16, Wait for rom firmware init authentication vector\n"); + do { + GnbUraGet (&DevObject, TRxSmuAuthVector, &RxSmuAuthVector); + } while (RxSmuAuthVector != 0x400); + // Call Authentication service + GnbSmuServiceRequestV7 (&DevObject, 0, 0, 0); + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init authentication done\n"); + // Wait for authentication done + do { + GnbUraGet (&DevObject, TBfxSmuAuthDone, &BfxSmuAuthDone); + } while (BfxSmuAuthDone == 0x0); + + //Step 17, Check Authentication results + IDS_HDT_CONSOLE (GNB_TRACE, "Step 17, Check Authentication results\n"); + GnbUraGet (&DevObject, TBfxSmuAuthPass, &BfxSmuAuthPass); + if (BfxSmuAuthPass == 0) { + IDS_HDT_CONSOLE (NB_MISC, " ERROR!!!Authentication fail!!!\n"); + ASSERT (FALSE); + return AGESA_FATAL; + } + // Step 18, Clear firmware interrupt enable flag + IDS_HDT_CONSOLE (GNB_TRACE, "Step 18, Clear firmware interrupt enable flag\n"); + BfxSmuInterruptsEnabled = 0; + GnbUraSet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); + + //Step 19, Assert SMU reset + IDS_HDT_CONSOLE (GNB_TRACE, "Step 19, Assert SMU reset\n"); + BfxSmuRstReg = 1; + GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); + + //Step 20, Deassert SMU reset + IDS_HDT_CONSOLE (GNB_TRACE, "Step 20, Deassert SMU reset\n"); + BfxSmuRstReg = 0; + GnbUraSet (&DevObject, TBfxSmuRstReg, &BfxSmuRstReg); + } + + //Step 9, 21 Wait firmware to initialize + IDS_HDT_CONSOLE (GNB_TRACE, "Step 9, 21 Wait firmware to initialize\n"); + do { + GnbUraGet (&DevObject, TBfxSmuInterruptsEnabled, &BfxSmuInterruptsEnabled); + } while (BfxSmuInterruptsEnabled == 0); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Exit\n"); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h new file mode 100644 index 0000000000..6f7f9d7faf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h @@ -0,0 +1,123 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85506 $ @e \$Date: 2013-01-08 15:38:33 -0600 (Tue, 08 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV7_H_ +#define _GNBNBINITLIBV7_H_ + +#pragma pack (push, 1) +#include "GnbUraServices.h" + +/// Firmware header +typedef struct { + UINT32 Digest[5]; ///< Digest + UINT32 Version; ///< Version + UINT32 HeaderSize; ///< Header length + UINT32 Flags; ///< Flags + UINT32 EntryPoint; ///< Entry Point + UINT32 CodeSize; ///< Code Size + UINT32 ImageSize; ///< Image Size + UINT32 Rtos; ///< Rtos + UINT32 SoftRegisters; ///< Soft Registers + UINT32 DpmTable; ///< Dpm Table + UINT32 FanTable; ///< Fan Table + UINT32 CacConfigTable; ///< Cac Configuration Table + UINT32 CacStatusTable; ///< Cac Status Table + UINT32 mcRegisterTable; ///< mc Register Table + UINT32 mcArbDramTimingTable; ///< mc Arb Dram Timing Table + UINT32 Globals; ///< Globals + UINT32 Signature; ///< Signature + UINT32 Reserved[44]; ///< Reserved space +} FIRMWARE_HEADER_V7; + +/// SMU service request contect +typedef struct { + PCI_ADDR GnbPciAddress; ///< PCIe address of GNB + UINT8 RequestId; ///< Request/Msg ID + UINT32 RequestArgument; ///< Request/Msg Argument +} SMU_MSG_CONTEXTV7; + + +#define SIZE_OF_APMWEIGHTS (sizeof (UINT32)) +typedef struct { + UINT64 EnergyCountConstant; + UINT64 BoostTimeConstant; + UINT32 CountApmWeights; ///< length of APMWeights array +// UINT32 ApmWeights[1]; ///< ApmWeights +} SMU_RAM_CPU_INFO; + + +#pragma pack (pop) + +VOID +GnbSmuServiceRequestV7 ( + IN DEV_OBJECT *DevObject, + IN UINT8 RequestId, + IN UINT32 RequestArgument, + IN UINT32 AccessFlags + ); + +AGESA_STATUS +GnbSmuFirmwareLoadV7 ( + IN GNB_HANDLE *GnbHandle, + IN FIRMWARE_HEADER_V7 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#define GnbSmuInitLibV7136_macro0 STRING_TO_UINT32 ('!', 'S', 'C', 'S') + +AGESA_STATUS +GnbSmuInitLibV7139_fun0( + IN GNB_HANDLE *GnbHandle, + IN UINT8 *ScsDataPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbSmuInitLibV7139_fun1( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c new file mode 100644 index 0000000000..4ebb28f59c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c @@ -0,0 +1,128 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Interface to initialize Graphics Controller at mid POST + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbCommonLib.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersCommon.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxInitSview ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init SVIEW configuration + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxInitSview ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (GfxLibIsControllerPresent (StdHeader)) { + if (!GfxFmIsVbiosPosted (Gfx)) { + GFX_VBIOS_IMAGE_INFO VbiosImageInfo; + LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + VbiosImageInfo.ImagePtr = NULL; + VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress; + VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST; + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader); + Status = AgesaGetVbiosImage (0, &VbiosImageInfo); + if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) { + GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx); + } else { + GfxFmDisableController (StdHeader); + AgesaStatus = AGESA_ERROR; + } + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xf8, BIT1 | BIT2, StdHeader); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c new file mode 100644 index 0000000000..82b234885f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c @@ -0,0 +1,357 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbLib.h" +#include "GnbTimerLib.h" +#include "GnbFamServices.h" +#include "GnbTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +GnbProcessTableRegisterRmw ( + IN GNB_HANDLE *GnbHandle, + IN GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol, + IN GNB_RMW_BLOCK *Data, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Process table + * + * @param[in] GnbHandle Gnb handle + * @param[in] Table Table pointer + * @param[in] Property Property + * @param[in] Flags Flags + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbProcessTable ( + IN GNB_HANDLE *GnbHandle, + IN GNB_TABLE *Table, + IN UINT32 Property, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *EntryPointer; + UINT64 Data; + UINT64 Temp; + UINT64 Mask; + UINT32 WriteAccFlags; + GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol; + CPU_LOGICAL_ID LogicalId; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property); + + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); + EntryPointer = (UINT8 *) Table; + WriteAccFlags = 0; + if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { + WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; + } + + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + while (*EntryPointer != GnbEntryTerminate) { + Data = 0; + Temp = 0; + switch (*EntryPointer) { + case GnbEntryWr: + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR); + break; + case GnbEntryPropertyWr: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) { + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR); + break; + case GnbEntryFullWr: + if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) { + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address, + &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value, + WriteAccFlags, + StdHeader + ); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR); + break; + case GnbEntryRmw: + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW); + break; + case GnbEntryPropertyRmw: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW); + break; + case GnbEntryRevRmw: + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Revision) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_REV_RMW); + break; + case GnbEntryFullRmw: + if ((Property & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) { + GnbProcessTableRegisterRmw ( + GnbHandle, + GnbRegisterAccessProtocol, + &((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Data, + WriteAccFlags, + StdHeader + ); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW); + break; + case GnbEntryPoll: + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL); + break; + case GnbEntryPropertyPoll: + if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) { + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL); + break; + case GnbEntryFullPoll: + if ((Property & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Property) != 0) { + if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) { + do { + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->RegisterSpaceType, + ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Address, + &Data, + 0, + StdHeader + ); + } while ((Data & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->CompareValue); + } + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_POLL); + break; + case GnbEntryCopy: + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress, + &Data, + 0, + StdHeader + ); + Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1; + Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask; + GnbRegisterAccessProtocol->Read ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, + &Temp, + 0, + StdHeader + ); + Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1; + Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset)); + Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset); + GnbRegisterAccessProtocol->Write ( + GnbHandle, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType, + ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress, + &Temp, + WriteAccFlags, + StdHeader + ); + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY); + break; + case GnbEntryStall: + if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) { + GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); + } else { + GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader); + } + EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL); + break; + default: + ASSERT (FALSE); + IDS_HDT_CONSOLE (NB_MISC, " ERROR!!! Register table parse\n"); + return AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Supporting function for register read modify write + * + * @param[in] GnbHandle Gnb handle + * @param[in] GnbRegisterAccessProtocol Register access protocol + * @param[in] Data Data pointer + * @param[in] Flags Flags + * @param[in] StdHeader Standard configuration header + */ + +VOID +STATIC +GnbProcessTableRegisterRmw ( + IN GNB_HANDLE *GnbHandle, + IN GNB_REGISTER_SERVICE *GnbRegisterAccessProtocol, + IN GNB_RMW_BLOCK *Data, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 Value; + Value = 0; + GnbRegisterAccessProtocol->Read ( + GnbHandle, + Data->RegisterSpaceType, + Data->Address, + &Value, + 0, + StdHeader + ); + Value = (Value & (~ (UINT64) Data->AndMask)) | Data->OrMask; + GnbRegisterAccessProtocol->Write ( + GnbHandle, + Data->RegisterSpaceType, + Data->Address, + &Value, + Flags, + StdHeader + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h new file mode 100644 index 0000000000..52693f4261 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h @@ -0,0 +1,238 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBTABLE_H_ +#define _GNBTABLE_H_ + +#include "GnbPcie.h" + +#pragma pack (push, 1) + +#define GNB_TABLE_FLAGS_FORCE_S3_SAVE 0x00000001ul + +typedef UINT8 GNB_TABLE; + +#define __DATA(x) x + +#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF +#define _DATA64(Data) _DATA32(Data & 0xfffffffful) , _DATA32(Data >> 32) + +/// Entry type +typedef enum { + GnbEntryWr, ///< Write register + GnbEntryPropertyWr, ///< Write register check property + GnbEntryFullWr, ///< Write Rgister check revision and property + GnbEntryRmw, ///< Read Modify Write register + GnbEntryPropertyRmw, ///< Read Modify Write register check property + GnbEntryRevRmw, ///< Read Modify Write register check revision + GnbEntryFullRmw, ///< Read Modify Write register check revision and property + GnbEntryPoll, ///< Poll register + GnbEntryPropertyPoll, ///< Poll register check property + GnbEntryFullPoll, ///< Poll register check property + GnbEntryCopy, ///< Copy field from one register to another + GnbEntryStall, ///< Copy field from one register to another + GnbEntryTerminate = 0xFF ///< Terminate table +} GNB_TABLE_ENTRY_TYPE; + +#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \ + GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_WR; + +#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \ + GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_PROPERTY_WR; + + +#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +///Read Modify Write data Block +typedef struct { + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< And Mask + UINT32 OrMask; ///< Or Mask +} GNB_RMW_BLOCK; + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_RMW; + +#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \ + GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 Value; ///< Value +} GNB_TABLE_ENTRY_FULL_WR; + + +#define GNB_ENTRY_PROPERTY_RMW(Property, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_PROPERTY_RMW; + +#define GNB_ENTRY_REV_RMW(Rev, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryRevRmw, _DATA64 (Rev), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT64 Revision; ///< revision + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_REV_RMW; + +#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \ + GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask) + +/// Read Modify Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + GNB_RMW_BLOCK Data; ///< Data +} GNB_TABLE_ENTRY_FULL_RMW; + +#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_POLL; + +#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_PROPERTY_POLL; + +#define GNB_ENTRY_FULL_POLL(Property, Revision, RegisterSpaceType, Address, AndMask, CompareValue) \ + GnbEntryFullPoll, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue) +/// Poll register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Property; ///< Property + UINT64 Revision; ///< Revision + UINT8 RegisterSpaceType; ///< Register space + UINT32 Address; ///< Register address + UINT32 AndMask; ///< End mask + UINT32 CompareValue; ///< Compare value +} GNB_TABLE_ENTRY_FULL_POLL; + +#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \ + GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth + +/// Copy register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT8 DestRegisterSpaceType; ///< Register space + UINT32 DestAddress; ///< Register address + UINT8 DestFieldOffset; ///< Field Offset + UINT8 DestFieldWidth; ///< Field Width + UINT8 SrcRegisterSpaceType; ///< Register space + UINT32 SrcAddress; ///< Register address + UINT8 SrcFieldOffset; ///< Field Offset + UINT8 SrcFieldWidth; ///< Field Width +} GNB_TABLE_ENTRY_COPY; + +#define GNB_ENTRY_STALL(Microsecond) \ + GnbEntryStall, _DATA32 (Microsecond) + +/// Write register entry +typedef struct { + UINT8 EntryType; ///< Entry type + UINT32 Microsecond; ///< Value +} GNB_TABLE_ENTRY_STALL; + +#define GNB_ENTRY_TERMINATE GnbEntryTerminate + +AGESA_STATUS +GnbProcessTable ( + IN GNB_HANDLE *GnbHandle, + IN GNB_TABLE *Table, + IN UINT32 Property, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c new file mode 100644 index 0000000000..7156f7e52d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c @@ -0,0 +1,388 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbUraServices.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +UINT8 RegisterDomainMap[] = { + 0x0, ///< Stub + 0x0, ///< Stub + 0x64, ///< 0x2 + 0x98, ///< 0x3 + 0xB8, ///< TYPE_D0F0xB8 + 0xFD ///< End +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Convert URA Token to register address and field location + * + * @param[in] UraToken Register of bit field identifier + * @param[in] UraTable Pointer to register token table + * @param[in, out] TokenInfo Pointer to URA_TOKEN_INFO structure + * + * @retval UraToken Token is defined + * @retval _UNUSED Token is undefined + * + */ +URA_TOKEN +STATIC +UraTranslateToken ( + IN URA_TOKEN UraToken, + IN URA_ENTRY *UraTable, + IN OUT URA_TOKEN_INFO *TokenInfo + ) +{ + URA_TOKEN_STRUCT Token; + URA_FIELD_16B_ENTRY *Field16; + URA_REGISTER_32B_ENTRY *Reg32; + URA_REGISTER_64B_ENTRY *Reg64; + + Token.Encode = UraToken; + Reg32 = NULL; + Reg64 = NULL; + Field16 = NULL; + + switch (Token.Parser.Type) { + // + // Parse 16 bit field encoding + // + case URA_TYPE_FIELD_16: + Field16 = (URA_FIELD_16B_ENTRY *) &(UraTable[Token.Parser.Index]); + TokenInfo->BfWidth = (UINT8) Field16->BfWidth; + TokenInfo->BfOffset = (UINT8) Field16->BfOffset; + while (Field16->Offset == 0) { + Token.Parser.Index -= 15; + Field16 = (URA_FIELD_16B_ENTRY *) &UraTable[Token.Parser.Index]; + } + + ASSERT (Field16->Offset != 0); + + if (Token.Parser.ParentType == URA_TOKEN_PARENT_TYPE_32) { + Token.Parser.Index -= (Field16->Offset - 1) * 2 + 2; + Reg32 = (URA_REGISTER_32B_ENTRY *) &UraTable[Token.Parser.Index]; + } else if (Token.Parser.ParentType == URA_TOKEN_PARENT_TYPE_64) { + Token.Parser.Index -= Field16->Offset + 3; + Reg64 = (URA_REGISTER_64B_ENTRY *) &(UraTable[Token.Parser.Index]); + } else { + ASSERT (FALSE); + return _UNUSED; + } + + TokenInfo->WholeRegAccess = FALSE; + break; + + // + // Parse 32 bit register encoding + // + case URA_TYPE_REGISTER_32: + Reg32 = (URA_REGISTER_32B_ENTRY *) &UraTable[Token.Parser.Index]; + if (Reg32->Address == _UNUSED) { + return _UNUSED; + } + TokenInfo->WholeRegAccess = TRUE; + break; + + // + // Parse 64 bit register encoding + // + case URA_TYPE_REGISTER_64: + Reg64 = (URA_REGISTER_64B_ENTRY *) &(UraTable[Token.Parser.Index]); + if (Reg64->DomainAddress == _UNUSED) { + return _UNUSED; + } + TokenInfo->WholeRegAccess = TRUE; + break; + + default: + ASSERT (FALSE); + } + + // Get register address + if ((Token.Parser.ParentType == URA_TOKEN_PARENT_TYPE_32) && (Reg32 != NULL)) { + TokenInfo->RegAddress = Reg32->Address; + TokenInfo->RegDomainType = 0; + } else if ((Token.Parser.ParentType == URA_TOKEN_PARENT_TYPE_64) && (Reg64 != NULL)) { + TokenInfo->RegAddress = (UINT32)Reg64->DomainAddress; + TokenInfo->RegDomainType = (UINT8)Reg64->DomainType; + } else { + ASSERT (FALSE); + return _UNUSED; + } + + TokenInfo->MethodType = Token.Parser.Selector; + + // Patch DomainType field + if (TokenInfo->MethodType == TYPE_GNB_INDIRECT_ACCESS) { + TokenInfo->RegDomainType = RegisterDomainMap[TokenInfo->RegDomainType]; + } + + TokenInfo->Flags = Token.Parser.S3Save; + TokenInfo->StreamSet = Token.Parser.StreamSet; + + return Token.Encode; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Standard configuration header + * @param[in] UraToken Context length + * @param[in, out] Value Pointer to Context + */ +VOID +GnbUraGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN OUT VOID *Value + ) +{ + AGESA_STATUS Status; + GNB_URA_SERVICE *GnbUraProtocol; + URA_TOKEN_INFO TokenInfo; + URA_ENTRY *UraTable; + UINT32 UraTableAddress; + + UraTable = NULL; + Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress); + UraTable = (URA_ENTRY *) ((UINTN)UraTableAddress); + UraToken = UraTranslateToken (UraToken, UraTable, &TokenInfo); + if (UraToken == _UNUSED) { + return; + } + + GnbUraProtocol->GnbUraGet (Device, &TokenInfo, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Standard configuration header + * @param[in] UraToken Ura token + * @param[in] Value Pointer to Context + */ +VOID +GnbUraSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN VOID *Value + ) +{ + AGESA_STATUS Status; + GNB_URA_SERVICE *GnbUraProtocol; + URA_TOKEN_INFO TokenInfo; + URA_ENTRY *UraTable; + UINT32 UraTableAddress; + + Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress); + UraTable = (URA_ENTRY *) ((UINTN)UraTableAddress); + UraToken = UraTranslateToken (UraToken, UraTable, &TokenInfo); + if (UraToken == _UNUSED) { + return; + } + + GnbUraProtocol->GnbUraSet (Device, &TokenInfo, Value); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Standard configuration header + * @param[in, out] UraTokenRegister Register token + * @param[in] UraTuple Pointer to Context + * @param[in, out] CombinedCount Token count + */ +VOID +GnbUraCombinedGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ) +{ + AGESA_STATUS Status; + GNB_URA_SERVICE *GnbUraProtocol; + URA_TOKEN_INFO TokenInfo; + URA_ENTRY *UraTable; + UINT32 UraTableAddress; + UINT32 RegValue; + UINT32 TempValue; + UINT32 FieldMask; + URA_TOKEN UraToken; + UINT32 Index; + + Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress); + UraTable = (URA_ENTRY *) ((UINTN)UraTableAddress); + UraTokenRegister = UraTranslateToken (UraTokenRegister, UraTable, &TokenInfo); + if (UraTokenRegister == _UNUSED) { + return; + } + + GnbUraProtocol->GnbUraGet (Device, &TokenInfo, &RegValue); + + Index = 0; + do { + UraToken = UraTuple[Index].Token; + UraToken = UraTranslateToken (UraToken, UraTable, &TokenInfo); + if (UraToken == _UNUSED) { + return; + } + + TempValue = RegValue; + TempValue = TempValue >> TokenInfo.BfOffset; + FieldMask = (((UINT32)1 << TokenInfo.BfWidth) - 1); + UraTuple[Index].Value = TempValue & FieldMask; + Index++; + } while (Index < CombinedCount); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Standard configuration header + * @param[in, out] UraTokenRegister Register token + * @param[in] UraTuple Pointer to Context + * @param[in, out] CombinedCount Token count + */ +VOID +GnbUraCombinedSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ) +{ + AGESA_STATUS Status; + GNB_URA_SERVICE *GnbUraProtocol; + URA_TOKEN_INFO TokenInfo; + URA_ENTRY *UraTable; + UINT32 UraTableAddress; + UINT32 RegValue; + UINT32 TempValue; + UINT32 FieldMask; + URA_TOKEN UraToken; + UINT32 Index; + + Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + + GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress); + UraTable = (URA_ENTRY *) ((UINTN)UraTableAddress); + UraTokenRegister = UraTranslateToken (UraTokenRegister, UraTable, &TokenInfo); + if (UraTokenRegister == _UNUSED) { + return; + } + + if (TokenInfo.StreamSet == 1) { + GnbUraProtocol->GnbUraStreamSet (Device, &TokenInfo, UraTuple, CombinedCount); + } else { + GnbUraProtocol->GnbUraGet (Device, &TokenInfo, &RegValue); + + Index = 0; + do { + UraToken = UraTuple[Index].Token; + UraToken = UraTranslateToken (UraToken, UraTable, &TokenInfo); + if (UraToken == _UNUSED) { + return; + } + FieldMask = (((UINT32)1 << TokenInfo.BfWidth) - 1); + TempValue = UraTuple[Index].Value & FieldMask; + RegValue &= ~(FieldMask << TokenInfo.BfOffset); + RegValue |= TempValue << TokenInfo.BfOffset; + Index++; + } while (Index < CombinedCount); + + UraTokenRegister = UraTranslateToken (UraTokenRegister, UraTable, &TokenInfo); + GnbUraProtocol->GnbUraSet (Device, &TokenInfo, &RegValue); + } +} |