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Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common')
16 files changed, 9212 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h new file mode 100644 index 0000000000..100ae03036 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87645 $ @e \$Date: 2013-02-06 13:08:17 -0600 (Wed, 06 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNB_H_ +#define _GNB_H_ + +#include "Ids.h" + +#pragma pack (push, 1) + +#define GNB_DEADLOOP() \ +{ \ + VOLATILE BOOLEAN k; \ + k = TRUE; \ + while (k) { \ + } \ +} +#ifdef IDSOPT_TRACING_ENABLED + #if (IDSOPT_TRACING_ENABLED == TRUE) + #define GNB_TRACE_ENABLE + #endif +#endif + + +#ifndef GNB_DEBUG_CODE + #ifdef GNB_TRACE_ENABLE + #define GNB_DEBUG_CODE(Code) Code + #else + #define GNB_DEBUG_CODE(Code) + #endif +#endif + +#ifndef MIN + #define MIN(x, y) (((x) > (y))? (y):(x)) +#endif + +#ifndef MAX + #define MAX(x, y) (((x) > (y))? (x):(y)) +#endif + +#define OFF 0 + +#define PVOID UINT32 + +#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a)) + +#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader) + +#define AGESA_STATUS_UPDATE(Current, Aggregated) \ +if (Current > Aggregated) { \ + Aggregated = Current; \ +} + +#ifndef offsetof + #define offsetof(s, m) (UINTN)&(((s *)0)->m) +#endif + + +//Table properties + +#define TABLE_PROPERTY_DEFAULT 0x00000000ul +#define TABLE_PROPERTY_IGFX_DISABLED 0x00000001ul +#define TABLE_PROPERTY_IOMMU_DISABLED 0x00000002ul +#define TABLE_PROPERTY_LCLK_DEEP_SLEEP 0x00000004ul +#define TABLE_PROPERTY_BAPM 0x00000100ul +#define TABLE_PROPERTY_NBDPM 0x00000800ul +#define TABLE_PROPERTY_LOADLINE_ENABLE 0x00001000ul +#define TABLE_PROPERTY_LHTC 0x00010000ul +#define TABLE_PROPERTY_SVI2 0x00020000ul + +//Register access flags Flags +#define GNB_REG_ACC_FLAG_S3SAVE 0x00000001ul + +// Gnb PCIe Master PLL +#define GNB_PCIE_MASTERPLL_A 0xA +#define GNB_PCIE_MASTERPLL_B 0xB +#define GNB_PCIE_MASTERPLL_C 0xC +#define GNB_PCIE_MASTERPLL_D 0xD + +/// LCLK DPM enable control +typedef enum { + LclkDpmDisabled, ///<LCLK DPM disabled + LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method +} LCLK_DPM_MODE; + + + + +/// Topology information +typedef struct { + BOOLEAN PhantomFunction; ///< PCIe topology have device with phantom function + BOOLEAN PcieToPciexBridge; ///< PCIe topology have device with Pcieto Pcix bridge +} GNB_TOPOLOGY_INFO; + + +/// GNB installable services +typedef enum { + GnbPcieFamConfigService, ///< PCIe config service + GnbPcieFamInitService, ///< PCIe Init service + GnbPcieFamDebugService, ///< PCIe Debug service + GnbRegisterAccessService, ///< GNB register access service + GnbIommuService, ///< GNB IOMMU config service + GnbUraService, ///< GNB Ura service + GfxFamService, ///< GFX Family service + GnbPcieMaxPayloadService, ///< GNB MaxPayload service + GnbFamTsService ///< GNB TimeStamp service +} GNB_SERVICE_ID; + +/// GNB service entry +typedef struct _GNB_SERVICE { + GNB_SERVICE_ID ServiceId; ///< Service ID + UINT64 Family; ///< CPU family + VOID *ServiceProtocol; ///< Service protocol + struct _GNB_SERVICE *NextService; ///< Pointer to next service +} GNB_SERVICE; + +/// GNB SMU Firmware Pointers +typedef struct _GNB_FW_PTRS { + VOID *FirmwareType1; ///< Pointer to Type 1 SMU Firmware + VOID *FirmwareType2; ///< Poitner to Type 2 SMU Firmware +} GNB_FW_PTRS; + + +#define GNB_STRINGIZE(x) #x +#define GNB_SERVICE_DEFINITIONS(x) GNB_STRINGIZE (Services/x/x.h) +#define GNB_MODULE_DEFINITIONS(x) GNB_STRINGIZE (Modules/x/x.h) +#define GNB_MODULE_INSTALL(x) GNB_STRINGIZE (Modules/x/x##Install.h) +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h new file mode 100644 index 0000000000..add550924b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h @@ -0,0 +1,99 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84159 $ @e \$Date: 2012-12-12 20:20:16 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + + +#ifndef _GNBF1TABLE_H_ +#define _GNBF1TABLE_H_ + +#pragma pack (push, 1) + +#define PP_F1_MAX_NUM_DPM_STATE 5 +#define PP_F1_MAX_NUM_SW_STATE 6 + +typedef struct { + UINT8 PPlayTableRev; ///< PP table revision + UINT8 PP_FUSE_ARRAY_V2_fld1[5]; + UINT8 PP_FUSE_ARRAY_V2_fld2[5]; + UINT8 PP_FUSE_ARRAY_V2_fld3; + UINT8 PP_FUSE_ARRAY_V2_fld4[6]; + UINT8 PP_FUSE_ARRAY_V2_fld5[5]; + UINT8 excel841_fld6[5]; ///< DispClk DID + UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID + UINT8 MainPllId; ///< Main PLL Id from fuses + UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 GpuBoostCap; ///< GPU boost cap + UINT32 PP_FUSE_ARRAY_V2_fld11; + UINT32 PP_FUSE_ARRAY_V2_fld12; + BOOLEAN PP_FUSE_ARRAY_V2_fld13; + UINT8 VceFlags[5]; ///< VCE Flags + UINT8 VceMclk; ///< MCLK for VCE + UINT8 PP_FUSE_ARRAY_V2_fld16[4]; + UINT8 EclkDid[5]; ///< Eclk DID + UINT8 HtcEn; ///< HTC Enabled + UINT8 HtcTmpLmt; ///< HTC Temperature Limit + UINT8 PP_FUSE_ARRAY_V2_fld20; + UINT8 PP_FUSE_ARRAY_V2_fld21; + UINT8 DisDllShutdownSR[4]; ///< DRAM Configuration Low [per DCT] + UINT8 MemClkFreq[4]; ///< DRAM Configuration High [per DCT] + UINT8 MemPhyPllPdMode[4]; ///< DRAM Controller Miscellaneous 2 [per DCT] + UINT8 M1MemClkFreq[4]; ///< Memory PState Control and Status [per DCT] + UINT8 PP_FUSE_ARRAY_V2_fld26[4]; + UINT8 PP_FUSE_ARRAY_V2_fld27[4]; + UINT8 PP_FUSE_ARRAY_V2_fld28[4]; + UINT8 PP_FUSE_ARRAY_V2_fld29[4]; + UINT8 PP_FUSE_ARRAY_V2_fld30[4]; + UINT8 PP_FUSE_ARRAY_V2_fld31[4]; + UINT8 PP_FUSE_ARRAY_V2_fld32[5]; + UINT8 PP_FUSE_ARRAY_V2_fld33[5]; + UINT8 PP_FUSE_ARRAY_V2_fld34[5]; + UINT8 PP_FUSE_ARRAY_V2_fld35[5]; + UINT8 PP_FUSE_ARRAY_V2_fld36; + UINT8 PP_FUSE_ARRAY_V2_fld37; + UINT8 PP_FUSE_ARRAY_V2_fld38; +} PP_F1_ARRAY_V2; + +#pragma pack (pop) + +#endif + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h new file mode 100644 index 0000000000..94510c32b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h @@ -0,0 +1,141 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBFAMSERVICES_H_ +#define _GNBFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" + +typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader +); + +/// Register Read/Write protocol +typedef struct { + F_GNB_REGISTER_ACCESS *Read; ///< Read Register + F_GNB_REGISTER_ACCESS *Write; ///< Write Register +} GNB_REGISTER_SERVICE; + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_GNBFMCREATEIVRSENTRY ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef BOOLEAN F_GNBFMCHECKIOMMUPRESENT ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GNB IOMMU services +typedef struct { + F_GNBFMCHECKIOMMUPRESENT *GnbFmCheckIommuPresent; ///< GnbFmCheckIommuPresent + F_GNBFMCREATEIVRSENTRY *GnbFmCreateIvrsEntry; ///< GnbFmCreateIvrsEntry +} GNB_FAM_IOMMU_SERVICES; + + +typedef UINT8 (F_PCIE_MAXPAYLOAD_SETTING) ( + IN PCIe_ENGINE_CONFIG *Engine +); + +/// MaxPayload service protocol +typedef struct { + F_PCIE_MAXPAYLOAD_SETTING *SetMaxPayload; ///< Write Register +} PCIE_MAXPAYLOAD_SERVICE; + + + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT32 F_GNBTIMESTAMP ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GNB Timestamp services +typedef struct { + F_GNBTIMESTAMP *GnbFmTimeStamp; ///< GnbFmTimeStamp +} GNB_FAM_TS_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h new file mode 100644 index 0000000000..d5c571bb3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h @@ -0,0 +1,348 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86709 $ @e \$Date: 2013-01-24 17:39:09 -0600 (Thu, 24 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFX_H_ +#define _GNBGFX_H_ + +#define DEVICE_DFP 0x1 +#define DEVICE_CRT 0x2 +#define DEVICE_LCD 0x3 + + +#define CONNECTOR_DISPLAYPORT_ENUM 0x3013 +#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 +#define CONNECTOR_VGA_ENUM 0x3005 +#define CONNECTOR_LVDS_ENUM 0x300E +#define CONNECTOR_eDP_ENUM 0x3014 +#define CONNECTOR_LVDS_eDP_ENUM 0x3016 +//DP to VGA: +#define ENCODER_DP2VGA_ENUM_ID1 0x2123 +//DP to LVDS: +#define ENCODER_DP2LVDS_ENUM_ID2 0x2223 +#define ENCODER_ALMOND_ENUM_ID1 0x2122 +#define ENCODER_NOT_PRESENT 0x0000 + +// no eDP->LVDS translator chip +#define eDP_TO_LVDS_RX_DISABLE 0x00 +// common eDP->LVDS translator chip without AMD SW init +#define eDP_TO_LVDS_COMMON_ID 0x01 +// Third party translator which requires AMD SW init +#define eDP_TO_LVDS_SWINIT_ID 0x02 + + +#define ATOM_DEVICE_CRT1_SUPPORT 0x0001 +#define ATOM_DEVICE_DFP1_SUPPORT 0x0008 +#define ATOM_DEVICE_DFP6_SUPPORT 0x0040 +#define ATOM_DEVICE_DFP2_SUPPORT 0x0080 +#define ATOM_DEVICE_DFP3_SUPPORT 0x0200 +#define ATOM_DEVICE_DFP4_SUPPORT 0x0400 +#define ATOM_DEVICE_DFP5_SUPPORT 0x0800 +#define ATOM_DEVICE_LCD1_SUPPORT 0x0002 + +/// Graphics card information structure +typedef struct { + UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information + UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information + UINT32 PciGfxCardBitmap; ///< All PCI graphics card information +} GFX_CARD_CARD_INFO; + +typedef enum { + iGpuVgaAdapter, ///< Configure iGPU as VGA adapter + iGpuVgaNonAdapter ///< Configure iGPU as non VGA adapter +} GFX_IGPU_VGA_MODE; + +/// UMA Steering Mode +typedef enum { + UMA_STEERING_ENUM0, + SystemTrafficOnion, ///< System traffic to onion + Onion, ///< Onion + UMA_STEERING_ENUM3, +} UMA_STEERING; + +/// User Options +typedef enum { + OptionDisabled, ///< Disabled + OptionEnabled ///< Enabled +} CONTROL_OPTION; + +/// GFX enable Policy +typedef enum { + GmcPowerGatingDisabled, ///< Disable Power gating + GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode + GmcPowerGatingWithStutter ///< GMC Power gating with Stutter mode +} GMC_POWER_GATING; + +/// Internal GFX mode +typedef enum { + GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode + GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1 +} GFX_CONTROLLER_MODE; + +/// Graphics Platform Configuration +typedef struct { + PVOID StdHeader; ///< Standard Header + PCI_ADDR GfxPciAddress; ///< Graphics PCI Address + UMA_INFO UmaInfo; ///< UMA Information + UINT64 GmmBase; ///< GMM Base + UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), + ///< essentially it enables function 1 of graphics device. + ///< @li 0 = HD Audio disable + ///< @li 1 = HD Audio enable + UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is + ///< characteristic specific to display panel which used by platform design. + ///< @li 0 = ABM support disabled + ///< @li 1 = ABM support enabled + UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. + UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. + ///< If equal to 0 backlight not controlled by iGPU. + UINT32 AmdPlatformType; ///< Platform type + UMA_STEERING UmaSteering; ///< UMA Steering + GFX_IGPU_VGA_MODE iGpuVgaMode; ///< iGPU VGA mode + BOOLEAN GmcClockGating; ///< Clock gating + BOOLEAN GmcLockRegisters; ///< GmcLock Registers + BOOLEAN GfxFusedOff; ///< Record if GFX is fused off. + GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating. + UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID + GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode + UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % + UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + UINT8 LvdsPowerOnSeqDigonToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToDigon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing. + UINT16 LvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported. + UINT32 LcdBitDepthControlValue; ///< The LCD bit depth control settings. + UINT8 Lvds24bbpPanelMode; ///< The LVDS 24 BBP mode. + LVDS_MISC_CONTROL LvdsMiscControl; ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; ///< Discrete GFX card info + UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % + BOOLEAN GnbRemoteDisplaySupport; ///< Wireless Display Enable + UINT8 LVDSVoltAdjust; ///< when ucLVDSMisc[5]=1, then this value will be programmed to register LVDS_CTRL_4 to adjust LVDS output voltage + DISPLAY_MISC_CONTROL DisplayMiscControl; ///< The Display misc control + DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType; ///< To indicate fixed voltage swing value + UINT8 MinAllowedBLLevel; ///< Minimum allowed LCD backlight level +} GFX_PLATFORM_CONFIG; + + +typedef UINT32 ULONG; +typedef UINT16 USHORT; +typedef UINT8 UCHAR; + +/// Driver interface header structure +typedef struct _ATOM_COMMON_TABLE_HEADER { + USHORT usStructureSize; ///< Structure size + UCHAR ucTableFormatRevision; ///< Format revision number + UCHAR ucTableContentRevision; ///< Contents revision number +} ATOM_COMMON_TABLE_HEADER; + +/// Link ping mapping for DP/eDP/LVDS +typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING { + UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DP_CONN_CHANNEL_MAPPING; + +/// Link ping mapping for DVI/HDMI +typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING { + UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DVI_CONN_CHANNEL_MAPPING; + + +/// External Display Path +typedef struct _EXT_DISPLAY_PATH { + USHORT usDeviceTag; ///< A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; ///< 16bit device ACPI id. + USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions + UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT + UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT + USHORT usExtEncoderObjId; ///< external encoder object id + union { ///< Lane mapping + UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + } ChannelMapping; + UCHAR ucChPNInvert; ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted + USHORT usCaps; ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1 + USHORT usReserved; ///< Reserved +} EXT_DISPLAY_PATH; + +/// External Display Connection Information +typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header + UCHAR ucGuid [16]; ///< Guid + EXT_DISPLAY_PATH sPath[7]; ///< External Display Path + UCHAR ucChecksum; ///< Checksum + UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID + UCHAR ucRemoteDisplayConfig; ///< Bit0=1:Enable Wireless Display through APU VCE HW function + UCHAR uceDPToLVDSRxId; ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Third party translator which require AMD SW init + UCHAR ucFixDPVoltageSwing; ///< The value match DPCD register DPx_LANE_SET defined in DP spec + UCHAR Reserved [3]; ///< Reserved +} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +/// DispClk to VID relation table +typedef struct _ATOM_CLK_VOLT_CAPABILITY { + ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz +} ATOM_CLK_VOLT_CAPABILITY; + +typedef struct _GnbGfx275_STRUCT { + ULONG GnbGfx275_STRUCT_fld0; + USHORT GnbGfx275_STRUCT_fld1; + USHORT GnbGfx275_STRUCT_fld2; +} GnbGfx275_STRUCT; + +/// TDP Configuration Bitfields +typedef struct _ATOM_TDP_CONFIG_BITS { + UINT32 uCTDP_Enable:2; ///< = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) + UINT32 uCTDP_Value:14; ///< Override value in tens of milli watts + UINT32 uTDP_Value:14; ///< Original TDP value in tens of milli watts + UINT32 uReserved:2; ///< Reserved +} ATOM_TDP_CONFIG_BITS; + +/// TDP Configuration Union +typedef union _ATOM_TDP_CONFIG { + ATOM_TDP_CONFIG_BITS TDP_config; ///< Field-wise access + ULONG TDP_config_all; ///< Access to all +} ATOM_TDP_CONFIG; + + +/// IntegrateSystemInfoTable is used for Kaveri & Kabini APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< + ULONG ulBootUpEngineClock; ///< + ULONG field2; ///< + ULONG ulBootUpUMAClock; ///< + ATOM_CLK_VOLT_CAPABILITY ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld4[4]; ///< + ULONG ulBootUpReqDisplayVector; ///< + ULONG ulVBIOSMisc; ///< + ULONG ulGPUCapInfo; ///< + ULONG ulReserved1; ///< + USHORT usRequestedPWMFreqInHz; ///< + UCHAR ucHtcTmpLmt; ///< + UCHAR ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11; ///< + ULONG ulReserved2; ///< + ULONG ulSystemConfig; ///< + ULONG ulCPUCapInfo; ///< + ULONG ulReserved3; ///< + USHORT usReserved1; ///< + USHORT usExtDispConnInfoOffset; ///< + USHORT usPanelRefreshRateRange; ///< + UCHAR ucMemoryType; ///< + UCHAR ucUMAChannelNumber; ///< + UCHAR strVBIOSMsg[40]; ///< + ULONG ulReserved[20]; ///< + GnbGfx275_STRUCT ATOM_INTEGRATED_SYSTEM_INFO_V1_8[5]; ///< + ULONG ulGMCRestoreResetTime; ///< + ULONG ulReserved4; ///< + ULONG ulIdleNClk; ///< + ULONG ulDDR_DLL_PowerUpTime; ///< + ULONG ulDDR_PLL_PowerUpTime; ///< + USHORT usPCIEClkSSPercentage; ///< + USHORT usPCIEClkSSType; ///< + USHORT usLvdsSSPercentage; ///< + USHORT usLvdsSSpreadRateIn10Hz; ///< + USHORT usHDMISSPercentage; ///< + USHORT usHDMISSpreadRateIn10Hz; ///< + USHORT usDVISSPercentage; ///< + USHORT usDVISSpreadRateIn10Hz; ///< + ULONG ulReserved5[5]; ///< + USHORT usMaxLVDSPclkFreqInSingleLink; ///< + UCHAR ucLvdsMisc; ///< + UCHAR ucLVDSVoltAdjust; ///< + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; ///< + UCHAR ucLVDSOffToOnDelay_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///< + UCHAR ucMinAllowedBL_Level; ///< + ULONG ulLCDBitDepthControlVal; ///< + ULONG ulNbpStateMemclkFreq[4]; ///< + ULONG ulReserved6; ///< + ULONG ulNbpStateNClkFreq[4]; ///< + USHORT usNBPStateVoltage[4]; ///< + USHORT usBootUpNBVoltage; ///< + USHORT usReserved2; ///< + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< +} ATOM_INTEGRATED_SYSTEM_INFO_V1_8; + +/// this Table is used for Kaveri/Kabini APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 { + ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition. + ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +} ATOM_FUSION_SYSTEM_INFO_V3; + +#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0) + +/// Define configuration values for ulGPUCapInfo +// BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use single PLL mode. +#define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE 0x01ul + +// BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode +#define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE 0x02ul + +// BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE 0x00ul +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE 0x08ul + +// BIT[4] - DFS bypass 0: Disable, 1: Enable +#define GPUCAPINFO_DFS_BYPASS_DISABLE 0x00ul +#define GPUCAPINFO_DFS_BYPASS_ENABLE 0x10ul + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h new file mode 100644 index 0000000000..b4160e6e87 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBGFXFAMSERVICES_H_ +#define _GNBGFXFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" + +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +typedef AGESA_STATUS F_GFXMAPENGINETODISPLAYPATH ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT32 F_GFXCALCULATECLOCK ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +typedef BOOLEAN F_GFXISVBIOSPOSTED ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID F_GFXDISABLECONTROLLER ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GFX Family services +typedef struct { + F_GFXMAPENGINETODISPLAYPATH *GfxMapEngineToDisplayPath; ///< GfxMapEngineToDisplayPath + F_GFXDISABLECONTROLLER *GfxDisableController; ///< GfxDisableController + F_GFXCALCULATECLOCK *GfxCalculateClock; ///< GfxCalculateClock + F_GFXISVBIOSPOSTED *GfxIsVbiosPosted; ///< GfxIsVbiosPosted; +} GFX_FAM_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h new file mode 100644 index 0000000000..c37c2148fa --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h @@ -0,0 +1,195 @@ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBIOMMU_H_ +#define _GNBIOMMU_H_ + +#pragma pack (push, 1) + + +/// IVRS block +typedef enum { + IvrsIvhdBlock = 0x10, ///< I/O Virtualization Hardware Definition Block + IvrsIvmdBlock = 0x20, ///< I/O Virtualization Memory Definition Block for all peripherals + IvrsIvmdBlockSingle = 0x21, ///< IVMD block for specified peripheral + IvrsIvmdBlockRange = 0x22, ///< IVMD block for peripheral range + IvrsIvhdrBlock = 0x40, ///< IVHDR (Relative) block + IvrsIvmdrBlock = 0x50, ///< IVMDR (Relative) block for all peripherals + IvrsIvmdrBlockSingle = 0x51 ///< IVMDR block for last IVHDR +} IVRS_BLOCK_TYPE; + +#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function) + +/// IVHD entry types +typedef enum { + IvhdEntryPadding = 0, ///< Table padding + IvhdEntrySelect = 2, ///< Select + IvhdEntryStartRange = 3, ///< Start Range + IvhdEntryEndRange = 4, ///< End Range + IvhdEntryAliasSelect = 66, ///< Alias select + IvhdEntryAliasStartRange = 67, ///< Alias start range + IvhdEntryExtendedSelect = 70, ///< Extended select + IvhdEntryExtendedStartRange = 71, ///< Extended Start range + IvhdEntrySpecialDevice = 72 ///< Special device +} IVHD_ENTRY_TYPE; + +/// Special device variety +typedef enum { + IvhdSpecialDeviceIoapic = 0x1, ///< IOAPIC + IvhdSpecialDeviceHpet = 0x2 ///< HPET +} IVHD_SPECIAL_DEVICE; + + +#define IVHD_FLAG_COHERENT BIT5 +#define IVHD_FLAG_IOTLBSUP BIT4 +#define IVHD_FLAG_ISOC BIT3 +#define IVHD_FLAG_RESPASSPW BIT2 +#define IVHD_FLAG_PASSPW BIT1 +#define IVHD_FLAG_PPRSUB BIT7 +#define IVHD_FLAG_PREFSUP BIT6 + +#define IVHD_EFR_XTSUP_OFFSET 0 +#define IVHD_EFR_NXSUP_OFFSET 1 +#define IVHD_EFR_GTSUP_OFFSET 2 +#define IVHD_EFR_GLXSUP_OFFSET 3 +#define IVHD_EFR_IASUP_OFFSET 5 +#define IVHD_EFR_GASUP_OFFSET 6 +#define IVHD_EFR_HESUP_OFFSET 7 +#define IVHD_EFR_PASMAX_OFFSET 8 +#define IVHD_EFR_PNCOUNTERS_OFFSET 13 +#define IVHD_EFR_PNBANKS_OFFSET 17 +#define IVHD_EFR_MSINUMPPR_OFFSET 23 +#define IVHD_EFR_GATS_OFFSET 28 +#define IVHD_EFR_HATS_OFFSET 30 + +#define IVINFO_HTATSRESV_MASK 0x00400000ul +#define IVINFO_VASIZE_MASK 0x003F8000ul +#define IVINFO_PASIZE_MASK 0x00007F00ul +#define IVINFO_GASIZE_MASK 0x000000E0ul + +#define IVHD_INFO_MSINUM_OFFSET 0 +#define IVHD_INFO_UNITID_OFFSET 8 + +#define IVMD_FLAG_EXCLUSION_RANGE BIT3 +#define IVMD_FLAG_IW BIT2 +#define IVMD_FLAG_IR BIT1 +#define IVMD_FLAG_UNITY BIT0 + +/// IVRS header +typedef struct { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 IvInfo; ///< IvInfo + UINT64 Reserved; ///< Reserved +} IOMMU_IVRS_HEADER; + +/// IVRS IVHD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 CapabilityOffset; ///< CapabilityOffset + UINT64 BaseAddress; ///< BaseAddress + UINT16 PciSegment; ///< Pci segment + UINT16 IommuInfo; ///< IOMMU info + UINT32 IommuEfr; ///< reserved +} IVRS_IVHD_ENTRY; + +/// IVHD generic entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings +} IVHD_GENERIC_ENTRY; + +///IVHD alias entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT8 Reserved; ///< Reserved + UINT16 AliasDeviceId; ///< Alias device id + UINT8 Reserved2; ///< Reserved +} IVHD_ALIAS_ENTRY; + +///IVHD extended entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT32 ExtSetting; ///< Extended settings +} IVHD_EXT_ENTRY; + +/// IVHD special entry +typedef struct { + UINT8 Type; ///< Type + UINT16 Reserved; ///< Reserved + UINT8 DataSetting; ///< Data settings + UINT8 Handle; ///< Handle + UINT16 AliasDeviceId; ///< Alis device id + UINT8 Variety; ///< Variety +} IVHD_SPECIAL_ENTRY; + +/// IVRS IVMD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 AuxiliaryData; ///< Auxiliary data + UINT64 Reserved; ///< Reserved (0000_0000_0000_0000) + UINT64 BlockStart; ///< IVMD start address + UINT64 BlockLength; ///< IVMD memory block length +} IVRS_IVMD_ENTRY; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c new file mode 100644 index 0000000000..4606d3d1a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c @@ -0,0 +1,111 @@ +/* $NoKeywords:$ */ + /** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Dispatch feature table + * + * + */ + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + CPU_LOGICAL_ID LogicalId; + + AgesaStatus = AGESA_SUCCESS; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + while (ConfigTable->GnbFeature != NULL) { + if ((ConfigTable->Type & LogicalId.Family) != 0) { + if (ConfigTable->TestPoint != 0) { + AGESA_TESTPOINT (ConfigTable->TestPoint, StdHeader); + } + Status = ConfigTable->GnbFeature (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + ConfigTable++; + } + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h new file mode 100644 index 0000000000..6d27c4b76b --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBFEATURES_H_ +#define _GNBLIBFEATURES_H_ + + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h new file mode 100644 index 0000000000..87a8b357c1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h @@ -0,0 +1,398 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe component definitions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** + +* +*/ + +#ifndef _GNBPCIE_H_ +#define _GNBPCIE_H_ + +#pragma pack (push, 1) + +#define MAX_NUMBER_OF_COMPLEXES 4 + +#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull +#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull +#define DESCRIPTOR_ALLOCATED 0x10000000ull +#define DESCRIPTOR_VIRTUAL 0x08000000ull +#define DESCRIPTOR_PLATFORM 0x04000000ull +#define DESCRIPTOR_COMPLEX 0x02000000ull +#define DESCRIPTOR_SILICON 0x01000000ull +#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull +#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull +#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull +#define DESCRIPTOR_DDI_ENGINE 0x00100000ull + +#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER) +#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) + +#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) + +#define UNUSED_LANE_ID 128 +//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) +//#define PCIE_LINK_L0_POOLING (60 * 1000) +//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) +//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) + +// Get lowest PHY lane on engine +#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0) +// Get highest PHY lane on engine +#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0) +// Get number of lanes on wrapper +#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) +// Check if virtual descriptor +#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE) +// Check if it is allocated descriptor +#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE) +// Check if it is last descriptor in list +#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE) +// Check if descriptor a PCIe engine +#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI engine +#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI wrapper +#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL) + +#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001ul +#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002ul +#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004ul +#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008ul +#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010ul +#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020ul +#define LANE_TYPE_PCIE_PHY 0x00000100ul +#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400ul +#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000ul +#define LANE_TYPE_DDI_PHY 0x00010000ul +#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000ul +#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000ul +#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000ul +#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL 0x00200000ul +#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL +#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL + +#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \ + LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \ + LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \ + LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \ + LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \ + LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) + +#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) + + +#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull +#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull +#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull +#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull +#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull +#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull +#define INIT_STATUS_DDI_ACTIVE 0x00000040ull +#define INIT_STATUS_ALLOCATED 0x00000080ull + +#define PCIE_PORT_GEN_CAP_BOOT 0x00000001ul +#define PCIE_PORT_GEN_CAP_MAX 0x00000002ul +#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010ul +#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000014ul +#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000018ul + +#define PCIE_POWERGATING_SKIP_CORE 0x00000001ul +#define PCIE_POWERGATING_SKIP_PHY 0x00000002ul + +/// PCIe Link Training State +typedef enum { + PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. + ///< PCIe device accessible after AmdEarlyInit complete + PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore + ///< PCIe device accessible after AmdPostInit complete. + ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. +} PCIE_TRAINING_ALGORITHM; + +/// PCIe Link Training State +typedef enum { + LinkStateResetAssert, ///< Assert port GPIO reset + LinkStateResetDuration, ///< Timeout for reset duration + LinkStateResetExit, ///< Deassert port GPIO reset + LinkTrainingResetTimeout, ///< Port GPIO reset timeout + LinkStateReleaseTraining, ///< Release link training + LinkStateDetectPresence, ///< Detect device presence + LinkStateDetecting, ///< Detect link training. + LinkStateBrokenLane, ///< Check and handle broken lane + LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised + LinkStateL0, ///< Device trained to L0 + LinkStateVcoNegotiation, ///< Check VCO negotiation complete + LinkStateRetrain, ///< Force retrain link. + LinkStateTrainingFail, ///< Link training fail + LinkStateTrainingSuccess, ///< Link training success + LinkStateGfxWorkaround, ///< GFX workaround + LinkStateCompliance, ///< Link in compliance mode + LinkStateDeviceNotPresent, ///< Link is not connected + LinkStateTrainingCompleted ///< Link training completed +} PCIE_LINK_TRAINING_STATE; + +/// PCIe Port Visibility +typedef enum { + UnhidePorts, ///< Command to unhide port + HidePorts, ///< Command to hide unused ports +} PCIE_PORT_VISIBILITY; + + +/// Table Register Entry +typedef struct { + UINT16 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_PORT_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_PORT_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_PORT_REGISTER_TABLE_HEADER; + +/// Table Register Entry +typedef struct { + UINT32 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_HOST_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_HOST_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_HOST_REGISTER_TABLE_HEADER; + +///Link ASPM info +typedef struct { + PCI_ADDR DownstreamPort; ///< PCI address of downstream port + PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm + PCI_ADDR UpstreamPort; ///< PCI address of upstream port + PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability + PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM + BOOLEAN BlackList; ///< Blacklist device +} PCIe_LINK_ASPM; + +///PCIe ASPM Latency Information +typedef struct { + UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us + UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us +} PCIe_ASPM_LATENCY_INFO; + +/// PCI address association +typedef struct { + UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion) + UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion) +} PCI_ADDR_LIST; + +/// The return status for GFX Card Workaround. +typedef enum { + GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready. + GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset. + GFX_WORKAROUND_SUCCESS ///< The service completed normally. +} GFX_WORKAROUND_STATUS; + +/// GFX workaround control +typedef enum { + GfxWorkaroundDisable, ///< GFX Workaround disabled + GfxWorkaroundEnable ///< GFX Workaround enabled +} GFX_WORKAROUND_CONTROL; + +/// PIF lane power state +typedef enum { + PifPowerStateL0, ///< + PifPowerStateLS1, ///< + PifPowerStateLS2, ///< + PifPowerStateOff = 0x7, ///< +} PCIE_PIF_POWER_STATE; + +/// PIF lane power control +typedef enum { + PowerDownPifs, ///< + PowerUpPifs ///< +} PCIE_PIF_POWER_CONTROL; + +///PLL rumup time +typedef enum { + NormalRampup, ///< + LongRampup, ///< +} PCIE_PLL_RAMPUP_TIME; + +typedef UINT16 PCIe_ENGINE_INIT_STATUS; + +/// PCIe port configuration info +typedef struct { + PCIe_PORT_DATA PortData; ///< Port data + UINT8 StartCoreLane; ///< Start Core Lane + UINT8 EndCoreLane; ///< End Core lane + UINT8 NativeDevNumber :5; ///< Native PCI device number of the port + UINT8 NativeFunNumber :3; ///< Native PCI function number of the port + UINT8 CoreId :4; ///< PCIe core ID + UINT8 PortId :4; ///< Port ID on wrapper + PCI_ADDR Address; ///< PCI address of the port + UINT8 State; ///< Training state + UINT8 PcieBridgeId:4; ///< IOC PCIe bridge ID + UINT16 UnitId:12; ///< Port start unit ID + UINT16 NumberOfUnitId:4; ///< Def number of unitIDs assigned to port + UINT8 GfxWrkRetryCount:4; ///< Number of retry for GFX workaround + UINT32 TimeStamp; ///< Time stamp used to during training process + UINT8 LogicalBridgeId; ///< Logical Bridge ID +} PCIe_PORT_CONFIG; + +///Descriptor header +typedef struct { + UINT32 DescriptorFlags; ///< Descriptor flags + UINT16 Parent; ///< Offset of parent descriptor + UINT16 Peer; ///< Offset of the peer descriptor + UINT16 Child; ///< Offset of the list of child descriptors +} PCIe_DESCRIPTOR_HEADER; + +/// DDI (Digital Display Interface) configuration info +typedef struct { + PCIe_DDI_DATA DdiData; ///< DDI Data + UINT8 DisplayPriorityIndex; ///< Display priority index + UINT8 ConnectorId; ///< Connector id determined by enumeration + UINT8 DisplayDeviceId; ///< Display device id determined by enumeration +} PCIe_DDI_CONFIG; + + +/// Engine configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor header + PCIe_ENGINE_DATA EngineData; ///< Engine Data + PCIe_ENGINE_INIT_STATUS InitStatus; ///< Initialization Status + UINT8 Scratch; ///< Scratch pad + union { + PCIe_PORT_CONFIG Port; ///< PCIe port configuration data + PCIe_DDI_CONFIG Ddi; ///< DDI configuration data + } Type; +} PCIe_ENGINE_CONFIG; + +/// Wrapper configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 WrapId; ///< Wrapper ID + UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper + UINT8 StartPhyLane; ///< Start PHY Lane + UINT8 EndPhyLane; ///< End PHY Lane + UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID + UINT8 EndPcieCoreId:4; ///< End PCIe Core ID + UINT8 NumberOfLanes; ///< Number of lanes + struct { + UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes + UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls + UINT8 ClkGating:1; ///< TXCLK gating + UINT8 LclkGating:1; ///< LCLK gating + UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down + UINT8 PllOffInL1:1; ///< PLL off in L1 + UINT8 AccessEncoding:1; ///< Reg access encoding + } Features; + UINT8 MasterPll; ///< Bitmap of master PLL +} PCIe_WRAPPER_CONFIG; + + +/// Silicon configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 SiliconId; ///< Gnb silicon(module) ID + UINT8 NodeId; ///< Node to which GNB connected + UINT8 LinkId; ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4 + PCI_ADDR Address; ///< PCI address of GNB host bridge +} PCIe_SILICON_CONFIG; + +typedef PCIe_SILICON_CONFIG GNB_HANDLE; + +/// Complex configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + UINT8 SocketId; ///< Processor socket ID +} PCIe_COMPLEX_CONFIG; + +/// PCIe platform configuration info +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descriptor Header + PVOID StdHeader; ///< Standard configuration header + UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. + UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us + UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us + UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// + UINT8 GfxCardWorkaround; ///< GFX Card Workaround + UINT8 PsppPolicy; ///< PSPP policy + UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) + PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex +} PCIe_PLATFORM_CONFIG; + +/// PCIe Engine Description +typedef struct { + UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor on wrapper + * @li @b Bit30 - Descriptor allocated for PCIe port or DDI + */ + PCIe_ENGINE_DATA EngineData; ///< Engine Data +} PCIe_ENGINE_DESCRIPTOR; + +/// PCIe Lane allocation descriptor +typedef struct { + UINT32 Flags; ///< Flags + UINT8 WrapId; ///< Wrapper ID + UINT8 EngineType; ///< Engine Type + UINT8 NumberOfEngines; ///< Number of engines to configure + UINT8 NumberOfConfigurations; ///< Number of possible configurations + UINT8 *ConfigTable; ///< Pointer to config table +} PCIe_LANE_ALLOC_DESCRIPTOR; + +/// Lane Control +typedef enum { + EnableLanes, ///< Enable Lanes + DisableLanes ///< Disable Lanes +} LANE_CONTROL; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h new file mode 100644 index 0000000000..6ec63993d3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h @@ -0,0 +1,242 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEFAMSERVICES_H_ +#define _GNBPCIEFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" + +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef VOID F_PCIEFMSETLINKSPEEDCAP ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/// PCIe config services +typedef struct { + F_PCIEFMGETCOMPLEXDATALENGTH *PcieFmGetComplexDataLength; ///< PcieFmGetComplexDataLength + F_PCIEFMBUILDCOMPLEXCONFIGURATION *PcieFmBuildComplexConfiguration; ///< PcieFmBuildComplexConfiguration + F_PCIEFMCONFIGUREENGINESLANEALLOCATION *PcieFmConfigureEnginesLaneAllocation; ///< PcieFmConfigureEnginesLaneAllocation + F_PCIEFMCHECKPORTPCIDEVICEMAPPING *PcieFmCheckPortPciDeviceMapping; ///< PcieFmCheckPortPciDeviceMapping + F_PCIEFMMAPPORTPCIADDRESS *PcieFmMapPortPciAddress; ///< PcieFmMapPortPciAddress + F_PCIEFMCHECKPORTPCIELANECANBEMUXED *PcieFmCheckPortPcieLaneCanBeMuxed; ///< PcieFmCheckPortPcieLaneCanBeMuxed + F_PCIEFMGETSBCONFIGINFO *PcieFmGetSbConfigInfo; ///< PcieFmGetSbConfigInfo +} PCIe_FAM_CONFIG_SERVICES; + +/// PCIe init services +typedef struct { + F_PCIEFMGETCORECONFIGURATIONVALUE *PcieFmGetCoreConfigurationValue; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMGETLINKSPEEDCAP *PcieFmGetLinkSpeedCap; ///< PcieFmGetLinkSpeedCap + F_PCIEFMGETNATIVEPHYLANEBITMAP *PcieFmGetNativePhyLaneBitmap; ///< PcieFmGetNativePhyLaneBitmap + F_PCIEFMSETLINKSPEEDCAP *PcieFmSetLinkSpeedCap; ///< PcieFmSetLinkSpeedCap +} PCIe_FAM_INIT_SERVICES; + +///PCIe debug services +typedef struct { + F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMDEBUGGETWRAPPERNAMESTRING *PcieFmDebugGetWrapperNameString; ///< PcieFmDebugGetWrapperNameString + F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING *PcieFmDebugGetCoreConfigurationString; ///< PcieFmDebugGetCoreConfigurationString +} PCIe_FAM_DEBUG_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h new file mode 100644 index 0000000000..b67058f291 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h @@ -0,0 +1,1557 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERSCOMMON_H_ +#define _GNBREGISTERSCOMMON_H_ + + +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xE4 0x5 +#define TYPE_DxF0 0x6 +#define TYPE_DxF0xE4 0x7 +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define D18F2x9C 0xe +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +// **** D0F0x00 Register Definition **** +// Address +#define D0F0x00_ADDRESS 0x0 + +// Type +#define D0F0x00_TYPE TYPE_D0F0 +// Field Data +#define D0F0x00_VendorID_OFFSET 0 +#define D0F0x00_VendorID_WIDTH 16 +#define D0F0x00_VendorID_MASK 0xffff +#define D0F0x00_DeviceID_OFFSET 16 +#define D0F0x00_DeviceID_WIDTH 16 +#define D0F0x00_DeviceID_MASK 0xffff0000 + +/// D0F0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x00_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 + +// Type +#define D0F0x04_TYPE TYPE_D0F0 +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_7_7_OFFSET 7 +#define D0F0x04_Reserved_7_7_WIDTH 1 +#define D0F0x04_Reserved_7_7_MASK 0x80 +#define D0F0x04_Reserved_19_10_OFFSET 10 +#define D0F0x04_Reserved_19_10_WIDTH 10 +#define D0F0x04_Reserved_19_10_MASK 0xffc00 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_19_10:10; ///< + UINT32 CapList:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x04_STRUCT; + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 + +// Type +#define D0F0x64_TYPE TYPE_D0F0 +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xffffffff + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_STRUCT; + + + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// Type +#define D0F0x90_TYPE TYPE_D0F0 +// Field Data +#define D0F0x90_Reserved_22_0_OFFSET 0 +#define D0F0x90_Reserved_22_0_WIDTH 23 +#define D0F0x90_Reserved_22_0_MASK 0x7fffff +#define D0F0x90_TopOfDram_OFFSET 23 +#define D0F0x90_TopOfDram_WIDTH 9 +#define D0F0x90_TopOfDram_MASK 0xff800000 + +/// D0F0x90 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 TopOfDram:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x90_STRUCT; + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xe0 + +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE0_PcieIndxAddr_OFFSET 0 +#define D0F0xE0_PcieIndxAddr_WIDTH 16 +#define D0F0xE0_PcieIndxAddr_MASK 0xffff +#define D0F0xE0_FrameType_OFFSET 16 +#define D0F0xE0_FrameType_WIDTH 8 +#define D0F0xE0_FrameType_MASK 0xff0000 +#define D0F0xE0_BlockSelect_OFFSET 24 +#define D0F0xE0_BlockSelect_WIDTH 8 +#define D0F0xE0_BlockSelect_MASK 0xff000000 + +/// D0F0xE0 +typedef union { + struct { ///< + UINT32 PcieIndxAddr:16; ///< + UINT32 FrameType:8 ; ///< + UINT32 BlockSelect:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE0_STRUCT; + + +// **** D18F3x15C Register Definition **** +// Address +#define D18F3x15C_ADDRESS 0x15c + +// Type +#define D18F3x15C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x15C_SclkVidLevel0_OFFSET 0 +#define D18F3x15C_SclkVidLevel0_WIDTH 7 +#define D18F3x15C_SclkVidLevel0_MASK 0x7f +#define D18F3x15C_Reserved_7_7_OFFSET 7 +#define D18F3x15C_Reserved_7_7_WIDTH 1 +#define D18F3x15C_Reserved_7_7_MASK 0x80 +#define D18F3x15C_SclkVidLevel1_OFFSET 8 +#define D18F3x15C_SclkVidLevel1_WIDTH 7 +#define D18F3x15C_SclkVidLevel1_MASK 0x7f00 +#define D18F3x15C_Reserved_15_15_OFFSET 15 +#define D18F3x15C_Reserved_15_15_WIDTH 1 +#define D18F3x15C_Reserved_15_15_MASK 0x8000 +#define D18F3x15C_SclkVidLevel2_OFFSET 16 +#define D18F3x15C_SclkVidLevel2_WIDTH 7 +#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000 +#define D18F3x15C_Reserved_23_23_OFFSET 23 +#define D18F3x15C_Reserved_23_23_WIDTH 1 +#define D18F3x15C_Reserved_23_23_MASK 0x800000 +#define D18F3x15C_SclkVidLevel3_OFFSET 24 +#define D18F3x15C_SclkVidLevel3_WIDTH 7 +#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000 +#define D18F3x15C_Reserved_31_31_OFFSET 31 +#define D18F3x15C_Reserved_31_31_WIDTH 1 +#define D18F3x15C_Reserved_31_31_MASK 0x80000000 + +/// D18F3x15C +typedef union { + struct { ///< + UINT32 SclkVidLevel0:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SclkVidLevel1:7 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 SclkVidLevel2:7 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 SclkVidLevel3:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x15C_STRUCT; + +// **** D18F3x17C Register Definition **** + + + +// **** DxF0x18 Register Definition **** +// Address +#define DxF0x18_ADDRESS 0x18 + +// Type +#define DxF0x18_TYPE TYPE_D4F0 +// **** DxF0x58 Register Definition **** +// Address + + + + +// **** D0F0x64_x0C Register Definition **** +// Address +#define D0F0x64_x0C_ADDRESS 0xc + +// Type +#define D0F0x64_x0C_TYPE TYPE_D0F0x64 + +/// D0F0x64_x0C +typedef union { + UINT32 Value; ///< +} D0F0x64_x0C_STRUCT; + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x19_TomEn_OFFSET 0 +#define D0F0x64_x19_TomEn_WIDTH 1 +#define D0F0x64_x19_TomEn_MASK 0x1 +#define D0F0x64_x19_Reserved_22_1_OFFSET 1 +#define D0F0x64_x19_Reserved_22_1_WIDTH 22 +#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe +#define D0F0x64_x19_Tom2_31_23__OFFSET 23 +#define D0F0x64_x19_Tom2_31_23__WIDTH 9 +#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 + +/// D0F0x64_x19 +typedef union { + struct { ///< + UINT32 TomEn:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 Tom2_31_23_:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x19_STRUCT; + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 +#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 +#define D0F0x64_x1A_Tom2_39_32__MASK 0xff +#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 +#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 +#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x1A +typedef union { + struct { ///< + UINT32 Tom2_39_32_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1A_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1d + +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1D_STRUCT; + + +// **** D0F0x64_x6A Register Definition **** +// Address +#define D0F0x64_x6A_ADDRESS 0x6a + +// Type +#define D0F0x64_x6A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x6A_VoltageForceEn_OFFSET 0 +#define D0F0x64_x6A_VoltageForceEn_WIDTH 1 +#define D0F0x64_x6A_VoltageForceEn_MASK 0x1 +#define D0F0x64_x6A_VoltageChangeEn_OFFSET 1 +#define D0F0x64_x6A_VoltageChangeEn_WIDTH 1 +#define D0F0x64_x6A_VoltageChangeEn_MASK 0x2 +#define D0F0x64_x6A_VoltageChangeReq_OFFSET 2 +#define D0F0x64_x6A_VoltageChangeReq_WIDTH 1 +#define D0F0x64_x6A_VoltageChangeReq_MASK 0x4 +#define D0F0x64_x6A_VoltageLevel_OFFSET 3 +#define D0F0x64_x6A_VoltageLevel_WIDTH 2 +#define D0F0x64_x6A_VoltageLevel_MASK 0x18 +#define D0F0x64_x6A_Reserved_31_5_OFFSET 5 +#define D0F0x64_x6A_Reserved_31_5_WIDTH 27 +#define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0 + +/// D0F0x64_x6A +typedef union { + struct { ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 VoltageLevel:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x6A_STRUCT; + +// **** D0F0x64_x6B Register Definition **** +// Address +#define D0F0x64_x6B_ADDRESS 0x6b + +// Type +#define D0F0x64_x6B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x6B_VoltageChangeAck_OFFSET 0 +#define D0F0x64_x6B_VoltageChangeAck_WIDTH 1 +#define D0F0x64_x6B_VoltageChangeAck_MASK 0x1 +#define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1 +#define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2 +#define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6 +#define D0F0x64_x6B_Reserved_31_3_OFFSET 3 +#define D0F0x64_x6B_Reserved_31_3_WIDTH 29 +#define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8 + +/// D0F0x64_x6B +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:2 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x6B_STRUCT; + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +// Type +#define D0F0x98_x06_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x06_Reserved_25_0_OFFSET 0 +#define D0F0x98_x06_Reserved_25_0_WIDTH 26 +#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 +#define D0F0x98_x06_Reserved_31_27_OFFSET 27 +#define D0F0x98_x06_Reserved_31_27_WIDTH 5 +#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x98_x06 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 UmiNpMemWrEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x06_STRUCT; + + +// **** D0F0x98_x2C Register Definition **** +// Address +#define D0F0x98_x2C_ADDRESS 0x2c + +// Type +#define D0F0x98_x2C_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 +#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 +#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 +#define D0F0x98_x2C_DynWakeEn_OFFSET 1 +#define D0F0x98_x2C_DynWakeEn_WIDTH 1 +#define D0F0x98_x2C_DynWakeEn_MASK 0x2 +#define D0F0x98_x2C_Reserved_15_2_OFFSET 2 +#define D0F0x98_x2C_Reserved_15_2_WIDTH 14 +#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc +#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 +#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 +#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 DynWakeEn:1 ; ///< + UINT32 Reserved_15_2:14; ///< + UINT32 WakeHysteresis:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x2C_STRUCT; + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3a + +// Type + + +// **** D0F0xE4_WRAP_0080 Register Definition **** +// Address +#define D0F0xE4_WRAP_0080_ADDRESS 0x80 + +// Type +#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf +#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 +#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 +#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_WRAP_0080 +typedef union { + struct { ///< + UINT32 StrapBifLinkConfig:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0080_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 + +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0800_STRUCT; + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +// **** D0F0xE4_WRAP_0903 Register Definition **** +// Address +#define D0F0xE4_WRAP_0903_ADDRESS 0x903 + +// Type +#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0903 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0903_STRUCT; + + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 + +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 Reserved_30_25:6 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Reserved_21_16:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_24_29:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 + +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 +// Field Data + +// **** D0F0xE4_WRAP_8023 Register Definition **** +// Address +#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 + +// Type +#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 +/// D0F0xE4_WRAP_8023 +typedef union { + UINT32 Value; ///< +} D0F0xE4_WRAP_8023_STRUCT; + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 + +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 +/// D0F0xE4_WRAP_8025 +typedef union { + UINT32 Value; ///< +} D0F0xE4_WRAP_8025_STRUCT; + + +// **** D0F0xE4_WRAP_8040 Register Definition **** +// Address +#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 + +// Type +#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 + + +// **** D0F0xE4_WRAP_8060 Register Definition **** +// Address +#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 + +// Type +#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 +#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xE4_WRAP_8060 +typedef union { + struct { ///< + UINT32 Reconfigure:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetComplete:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BifGlobalReset:1 ; ///< + UINT32 BifCalibrationReset:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8060_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000 +#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 +#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 EiCycleOffTime:3 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 +#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 +#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 +#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 +#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 b12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 Reserved_24_17:8 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_PIF_0013 Register Definition **** +// Address +#define D0F0xE4_PIF_0013_ADDRESS 0x13 + +// Type +#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0013 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0013_STRUCT; + + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf +#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 +#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 +#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_CORE_0011 +typedef union { + struct { ///< + UINT32 DynClkLatency:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0011_STRUCT; + + + + + + + + +// **** DxF0xE4_x70 Register Definition **** +// Address + + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 +#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 +#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 +#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1 ; ///< + UINT32 MasterPciePllB:1 ; ///< + UINT32 MasterPciePllC:1 ; ///< + UINT32 MasterPciePllD:1 ; ///< + UINT32 ClkDividerResetOverrideA:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxclkSelCoreOverride:1 ; ///< + UINT32 TxclkSelPifAOverride:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 +#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 +#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 +#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 +#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 +#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 +#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0x64_x51 Register Definition **** +// Address +#define D0F0x64_x51_ADDRESS 0x51 + +// Type +#define D0F0x64_x51_TYPE TYPE_D0F0x64 + + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET 1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH 3 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK 0xe +#define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET 4 +#define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH 3 +#define D0F0xE4_CORE_0010_Reserved_6_4_MASK 0x70 +#define D0F0xE4_CORE_0010_Reserved_8_8_OFFSET 8 +#define D0F0xE4_CORE_0010_Reserved_8_8_WIDTH 1 +#define D0F0xE4_CORE_0010_Reserved_8_8_MASK 0x100 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_15_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_15_13_WIDTH 3 +#define D0F0xE4_CORE_0010_Reserved_15_13_MASK 0xe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 LcHotPlugDelSel:3 ; ///< + UINT32 Reserved_6_4:3 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxUmiAdjPayloadSize:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :6 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + + +typedef union { + struct { ///< + UINT32 bit_0_0:1 ; ///< + UINT32 bit1:1 ; ///< + UINT32 bit2:1 ; ///< + UINT32 bit3:1 ; ///< + UINT32 bit4:1 ; ///< + UINT32 bit5:1 ; ///< + UINT32 bit6:1 ; ///< + UINT32 bit_7_7:1 ; ///< + UINT32 bit_9_8:2 ; ///< + UINT32 bit_10_10:1 ; ///< + UINT32 bit11:1 ; ///< + UINT32 bit12:1 ; ///< + UINT32 bit13:1 ; ///< + UINT32 bit14:1 ; ///< + UINT32 bit15:1 ; ///< + UINT32 bit16:1 ; ///< + UINT32 bit_17_17:1 ; ///< + UINT32 bit_19_18:2 ; ///< + UINT32 bit20:1 ; ///< + UINT32 bit_21_21:1 ; ///< + UINT32 bit_23_22:2 ; ///< + UINT32 bit24:1 ; ///< + UINT32 bit_25_25:1 ; ///< + UINT32 bit_27_26:2 ; ///< + UINT32 bit_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GNBREGCOMMON_STR1_STRUCT; + + + + +// **** D0F0xE4_PHY_6006 Register Definition **** +// Address +#define D0F0xE4_PHY_6006_ADDRESS 0x6006 + +// Type +#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 +#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 +#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff +#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET 16 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK 0xff0000 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET 24 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK 0xff000000 + +/// D0F0xE4_PHY_6006 +typedef union { + struct { ///< + UINT32 TxMarginNom:8 ; ///< + UINT32 DeemphGen1Nom:8 ; ///< + UINT32 Deemph35Gen2Nom:8 ; ///< + UINT32 Deemph60Gen2Nom:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6006_STRUCT; + +// **** GMMx00 Register Definition **** +// Address +#define GMMx00_ADDRESS 0x0 + +// Type +#define GMMx00_TYPE TYPE_GMM +// Field Data +#define GMMx00_Offset_OFFSET 0 +#define GMMx00_Offset_WIDTH 31 +#define GMMx00_Offset_MASK 0x7fffffff +#define GMMx00_Aper_OFFSET 31 +#define GMMx00_Aper_WIDTH 1 +#define GMMx00_Aper_MASK 0x80000000 + +/// GMMx00 +typedef union { + struct { ///< + UINT32 Offset:31; ///< + UINT32 Aper:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx00_STRUCT; + +// **** GMMx04 Register Definition **** +// Address +#define GMMx04_ADDRESS 0x4 + +// Type +#define GMMx04_TYPE TYPE_GMM +// Field Data +#define GMMx04_Data_OFFSET 0 +#define GMMx04_Data_WIDTH 32 +#define GMMx04_Data_MASK 0xffffffff + +/// GMMx04 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx04_STRUCT; + + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f +#define D0F0xE4_WRAP_8016_Reserved_7_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_7_6_WIDTH 2 +#define D0F0xE4_WRAP_8016_Reserved_7_6_MASK 0xc0 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_OFFSET 8 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_WIDTH 1 +#define D0F0xE4_WRAP_8016_CalibDoneSelPifA_MASK 0x100 +#define D0F0xE4_WRAP_8016_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8016_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8016_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8016_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8016_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8016_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8016_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_OFFSET 12 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_WIDTH 1 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngage_MASK 0x1000 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_OFFSET 13 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_WIDTH 1 +#define D0F0xE4_WRAP_8016_Gen1OnlyEngaged_MASK 0x2000 +#define D0F0xE4_WRAP_8016_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8016_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8016_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CalibDoneSelPifA:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Gen1OnlyEngage:1 ; ///< + UINT32 Gen1OnlyEngaged:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h new file mode 100644 index 0000000000..4458039349 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h @@ -0,0 +1,1445 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87271 $ @e \$Date: 2013-01-31 10:11:23 -0600 (Thu, 31 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERS_CV2_H_ +#define _GNBREGISTERS_CV2_H_ + +#define SMC_MSG_FIRMWARE_AUTH 0 + +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif + +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif + +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + + +// **** D0F0xFC_x01 Register Definition **** +// Address +#define D0F0xFC_x01_ADDRESS 0x01 + +// **** D0F0xFC_x02 Register Definition **** +// Address +#define D0F0xFC_x02_ADDRESS 0x02 + +// **** D0F0xFC_x10 Register Definition **** +// Address +#define D0F0xFC_x10_ADDRESS 0x10 +// Type +#define D0F0xFC_x10_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x10_BrExtIntrGrp_OFFSET 0 +#define D0F0xFC_x10_BrExtIntrGrp_WIDTH 3 +#define D0F0xFC_x10_BrExtIntrGrp_MASK 0x7 +#define D0F0xFC_x10_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x10_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x10_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x10_BrExtIntrSwz_OFFSET 4 +#define D0F0xFC_x10_BrExtIntrSwz_WIDTH 2 +#define D0F0xFC_x10_BrExtIntrSwz_MASK 0x30 +#define D0F0xFC_x10_Reserved_15_6_OFFSET 6 +#define D0F0xFC_x10_Reserved_15_6_WIDTH 10 +#define D0F0xFC_x10_Reserved_15_6_MASK 0xFFC0 +#define D0F0xFC_x10_BrIntIntrMap_OFFSET 16 +#define D0F0xFC_x10_BrIntIntrMap_WIDTH 5 +#define D0F0xFC_x10_BrIntIntrMap_MASK 0x1F0000 +#define D0F0xFC_x10_Reserved_31_21_OFFSET 21 +#define D0F0xFC_x10_Reserved_31_21_WIDTH 11 +#define D0F0xFC_x10_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0xFC_x10 +typedef union { + struct { ///< + UINT32 BrExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 BrExtIntrSwz:2; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 BrIntIntrMap:5; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x10_STRUCT; + +// **** D0F0xB8 Register Definition **** +// Address +#define D0F0xB8_ADDRESS 0xb8 + +// **** DxF0xE4_xC1 Register Definition **** +// Address +#define D2FxxE4_xC1_ADDRESS 0xc1 + +// Type +#define D2FxxE4_xC1_TYPE TYPE_D4F0xE4 +// Field Data + +#define D2FxxE4_xC1_StrapReverseLanes_OFFSET 0 +#define D2FxxE4_xC1_StrapReverseLanes_WIDTH 1 +#define D2FxxE4_xC1_StrapReverseLanes_MASK 0x1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_OFFSET 1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_WIDTH 1 +#define D2FxxE4_xC1_StrapE2EPrefixEn_MASK 0x2 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_OFFSET 2 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_WIDTH 1 +#define D2FxxE4_xC1_StrapExtendedFmtSupported_MASK 0x4 +#define D2FxxE4_xC1_Reserved_31_3_OFFSET 3 +#define D2FxxE4_xC1_Reserved_31_3_WIDTH 29 +#define D2FxxE4_xC1_Reserved_31_3_MASK 0xfffffff8 + +// Type +// Address +#define D0F0xE4_WRAP_0046_ADDRESS 0x46 + +// Address +#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 + + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + + +// Type +#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET 0 +#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH 1 +#define D0F0xE4_WRAP_8040_OwnSlice_MASK 0x1 + + +// **** D0F0xBC_x1F630 Register Definition **** +// Address +#define D0F0xBC_x1F630_ADDRESS 0x1f630 + +// Type +#define D0F0xBC_x1F630_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK 0x00ff00 + + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xFC00 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8011_Bitfield_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7E0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_WRAP_8011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6; ///< + UINT32 TxclkPermGateEven:1; ///< + UINT32 TxclkDynGateEnable:1; ///< + UINT32 TxclkPermStop:1; ///< + UINT32 TxclkRegsGateEnable:1; ///< + UINT32 TxclkRegsGateLatency:6; ///< + UINT32 Bitfield_16_16:1; ///< + UINT32 TxclkPermGateLatency:6; ///< + UINT32 Reserved_23_23:1; ///< + UINT32 TxclkLcntGateEnable:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8011_STRUCT; + + + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 + +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf + + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 +#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 :3 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D2FxxE4_xA4 Register Definition **** +// Address +#define D2FxxE4_xA4_ADDRESS 0xa4 + +// Type +#define D2FxxE4_xA4_TYPE TYPE_D4F0xE4 +// Field Data +#define D2FxxE4_xA4_LcGen2EnStrap_OFFSET 0 +#define D2FxxE4_xA4_LcGen2EnStrap_WIDTH 1 +#define D2FxxE4_xA4_LcGen2EnStrap_MASK 0x1 +#define D2FxxE4_xA4_Reserved_5_1_OFFSET 1 +#define D2FxxE4_xA4_Reserved_5_1_WIDTH 5 +#define D2FxxE4_xA4_Reserved_5_1_MASK 0x3e +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_OFFSET 6 +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 +#define D2FxxE4_xA4_LcForceDisSwSpeedChange_MASK 0x40 +#define D2FxxE4_xA4_Reserved_8_7_OFFSET 7 +#define D2FxxE4_xA4_Reserved_8_7_WIDTH 2 +#define D2FxxE4_xA4_Reserved_8_7_MASK 0x180 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_OFFSET 9 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 +#define D2FxxE4_xA4_LcInitiateLinkSpeedChange_MASK 0x200 +#define D2FxxE4_xA4_Reserved_11_10_OFFSET 10 +#define D2FxxE4_xA4_Reserved_11_10_WIDTH 2 +#define D2FxxE4_xA4_Reserved_11_10_MASK 0xc00 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 12 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 +#define D2FxxE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x1000 +#define D2FxxE4_xA4_Reserved_18_13_OFFSET 13 +#define D2FxxE4_xA4_Reserved_18_13_WIDTH 6 +#define D2FxxE4_xA4_Reserved_18_13_MASK 0x7e000 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_OFFSET 19 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 +#define D2FxxE4_xA4_LcOtherSideSupportsGen2_MASK 0x80000 +#define D2FxxE4_xA4_Reserved_26_20_OFFSET 20 +#define D2FxxE4_xA4_Reserved_26_20_WIDTH 7 +#define D2FxxE4_xA4_Reserved_26_20_MASK 0x7f00000 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 27 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 +#define D2FxxE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x8000000 +#define D2FxxE4_xA4_Reserved_31_28_OFFSET 28 +#define D2FxxE4_xA4_Reserved_31_28_WIDTH 4 +#define D2FxxE4_xA4_Reserved_31_28_MASK 0xf0000000 + +/// D2FxxE4_xA4 +typedef union { + struct { ///< + UINT32 LcGen2EnStrap:1 ; ///< + UINT32 Reserved_5_1:5 ; ///< + UINT32 LcForceDisSwSpeedChange:1 ; ///< + UINT32 Reserved_8_7:2 ; ///< + UINT32 LcInitiateLinkSpeedChange:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 LcSpeedChangeAttemptFailed:1 ; ///< + UINT32 Reserved_18_13:6 ; ///< + UINT32 LcOtherSideSupportsGen2:1 ; ///< + UINT32 Reserved_26_20:7 ; ///< + UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D2FxxE4_xA4_STRUCT; + + +// **** D2FxxE4_xC0 Register Definition **** +// Address +#define D2FxxE4_xC0_ADDRESS 0xc0 + +// Type +#define D2FxxE4_xC0_TYPE TYPE_D4F0xE4 +// Field Data +#define D2FxxE4_xC0_Reserved_12_0_OFFSET 0 +#define D2FxxE4_xC0_Reserved_12_0_WIDTH 13 +#define D2FxxE4_xC0_Reserved_12_0_MASK 0x1fff +#define D2FxxE4_xC0_StrapForceCompliance_OFFSET 13 +#define D2FxxE4_xC0_StrapForceCompliance_WIDTH 1 +#define D2FxxE4_xC0_StrapForceCompliance_MASK 0x2000 +#define D2FxxE4_xC0_Reserved_14_14_OFFSET 14 +#define D2FxxE4_xC0_Reserved_14_14_WIDTH 1 +#define D2FxxE4_xC0_Reserved_14_14_MASK 0x4000 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define D2FxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define D2FxxE4_xC0_Reserved_31_16_OFFSET 16 +#define D2FxxE4_xC0_Reserved_31_16_WIDTH 16 +#define D2FxxE4_xC0_Reserved_31_16_MASK 0xffff0000 + +/// D2FxxE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D2FxxE4_xC0_STRUCT; + + +// **** D2Fxx88 Register Definition **** +// Address +#define D2Fxx88_ADDRESS 0x88 + +// Type +#define D2Fxx88_TYPE TYPE_D4F0 +// Field Data +#define D2Fxx88_TargetLinkSpeed_OFFSET 0 +#define D2Fxx88_TargetLinkSpeed_WIDTH 4 +#define D2Fxx88_TargetLinkSpeed_MASK 0xf +#define D2Fxx88_EnterCompliance_OFFSET 4 +#define D2Fxx88_EnterCompliance_WIDTH 1 +#define D2Fxx88_EnterCompliance_MASK 0x10 +#define D2Fxx88_HwAutonomousSpeedDisable_OFFSET 5 +#define D2Fxx88_HwAutonomousSpeedDisable_WIDTH 1 +#define D2Fxx88_HwAutonomousSpeedDisable_MASK 0x20 +#define D2Fxx88_SelectableDeemphasis_OFFSET 6 +#define D2Fxx88_SelectableDeemphasis_WIDTH 1 +#define D2Fxx88_SelectableDeemphasis_MASK 0x40 +#define D2Fxx88_XmitMargin_OFFSET 7 +#define D2Fxx88_XmitMargin_WIDTH 3 +#define D2Fxx88_XmitMargin_MASK 0x380 +#define D2Fxx88_EnterModCompliance_OFFSET 10 +#define D2Fxx88_EnterModCompliance_WIDTH 1 +#define D2Fxx88_EnterModCompliance_MASK 0x400 +#define D2Fxx88_ComplianceSOS_OFFSET 11 +#define D2Fxx88_ComplianceSOS_WIDTH 1 +#define D2Fxx88_ComplianceSOS_MASK 0x800 +#define D2Fxx88_ComplianceDeemphasis_OFFSET 12 +#define D2Fxx88_ComplianceDeemphasis_WIDTH 1 +#define D2Fxx88_ComplianceDeemphasis_MASK 0x1000 +#define D2Fxx88_Reserved_15_13_OFFSET 13 +#define D2Fxx88_Reserved_15_13_WIDTH 3 +#define D2Fxx88_Reserved_15_13_MASK 0xe000 +#define D2Fxx88_CurDeemphasisLevel_OFFSET 16 +#define D2Fxx88_CurDeemphasisLevel_WIDTH 1 +#define D2Fxx88_CurDeemphasisLevel_MASK 0x10000 +#define D2Fxx88_Reserved_31_17_OFFSET 17 +#define D2Fxx88_Reserved_31_17_WIDTH 15 +#define D2Fxx88_Reserved_31_17_MASK 0xfffe0000 + +/// D2Fxx88 +typedef union { + struct { ///< + UINT32 TargetLinkSpeed:4 ; ///< + UINT32 EnterCompliance:1 ; ///< + UINT32 HwAutonomousSpeedDisable:1 ; ///< + UINT32 SelectableDeemphasis:1 ; ///< + UINT32 XmitMargin:3 ; ///< + UINT32 EnterModCompliance:1 ; ///< + UINT32 ComplianceSOS:1 ; ///< + UINT32 ComplianceDeemphasis:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 CurDeemphasisLevel:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D2Fxx88_STRUCT; + + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +/* + * Needed by GnbNbInitLibV4.c + */ + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + + + + + +/// D0F0xBC_x80010000 +typedef union { +UINT32 Value; ///< +} GRC1_STRUCT; + + + + + + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_8_1:8 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxSbAdjPayloadSize:3 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3a + + +// **** D18F0x110 Register Definition **** +// Address +#define D18F0x110_ADDRESS 0x110 + + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 + +/* + * Needed by GnbNbInitLibV4.c - end + */ + +/* + * Needed by GnbIommuScratch.c + */ + + + + +/* + * Needed by GnbIommuScratch.c - end + */ + +/* + * Needed by GnbIoapic.c + */ + + +// **** D0F0xF8 Register Definition **** +// Address +#define D0F0xF8_ADDRESS 0xf8 + +// **** D0F0xFC_x00 Register Definition **** +// Address +#define D0F0xFC_x00_ADDRESS 0x0 + +// Type +#define D0F0xFC_x00_TYPE TYPE_D0F0xFC +// Field Data +#define D0F0xFC_x00_IoapicEnable_OFFSET 0 +#define D0F0xFC_x00_IoapicEnable_WIDTH 1 +#define D0F0xFC_x00_IoapicEnable_MASK 0x01 +#define D0F0xFC_x00_Reserved_1_1_OFFSET 2 +#define D0F0xFC_x00_Reserved_1_1_WIDTH 1 +#define D0F0xFC_x00_Reserved_1_1_MASK 0x02 +#define D0F0xFC_x00_IoapicIdExtEn_OFFSET 3 +#define D0F0xFC_x00_IoapicIdExtEn_WIDTH 1 +#define D0F0xFC_x00_IoapicIdExtEn_MASK 0x04 +#define D0F0xFC_x00_Reserved_3_3_OFFSET 4 +#define D0F0xFC_x00_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x00_Reserved_3_3_MASK 0x08 +#define D0F0xFC_x00_IoapicSbFeatureEn_OFFSET 4 +#define D0F0xFC_x00_IoapicSbFeatureEn_WIDTH 1 +#define D0F0xFC_x00_IoapicSbFeatureEn_MASK 0x10 +#define D0F0xFC_x00_Reserved_31_5_OFFSET 5 +#define D0F0xFC_x00_Reserved_31_5_WIDTH 27 +#define D0F0xFC_x00_Reserved_31_5_MASK 0xffffffe0 + +/// D0F0xFC_x00 +typedef union { + struct { ///< + UINT32 IoapicEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 IoapicIdExtEn:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 IoapicSbFeatureEn:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xFC_x00_STRUCT; + +/* + * Needed by GnbIoapic.c - end + */ + +/* + * Needed by GnbPcieInitLibV5 + */ + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + + +// **** D0F0xCC_x01 Register Definition **** +// Address +#define D0F0xCC_x01_ADDRESS 0x1 + +// Type +#define D0F0xCC_x01_TYPE TYPE_D0F0xCC +// Field Data +#define D0F0xCC_x01_BridgeDis_OFFSET 0 +#define D0F0xCC_x01_BridgeDis_WIDTH 1 +#define D0F0xCC_x01_BridgeDis_MASK 0x1 +#define D0F0xCC_x01_Reserved_1_1_OFFSET 1 +#define D0F0xCC_x01_Reserved_1_1_WIDTH 1 +#define D0F0xCC_x01_Reserved_1_1_MASK 0x2 +#define D0F0xCC_x01_CfgDis_OFFSET 2 +#define D0F0xCC_x01_CfgDis_WIDTH 1 +#define D0F0xCC_x01_CfgDis_MASK 0x4 +#define D0F0xCC_x01_P2pDis_OFFSET 3 +#define D0F0xCC_x01_P2pDis_WIDTH 1 +#define D0F0xCC_x01_P2pDis_MASK 0x8 +#define D0F0xCC_x01_Reserved_15_4_OFFSET 4 +#define D0F0xCC_x01_Reserved_15_4_WIDTH 12 +#define D0F0xCC_x01_Reserved_15_4_MASK 0xfff0 +#define D0F0xCC_x01_ExtDevPlug_OFFSET 16 +#define D0F0xCC_x01_ExtDevPlug_WIDTH 1 +#define D0F0xCC_x01_ExtDevPlug_MASK 0x10000 +#define D0F0xCC_x01_ExtDevCsrEn_OFFSET 17 +#define D0F0xCC_x01_ExtDevCsrEn_WIDTH 1 +#define D0F0xCC_x01_ExtDevCsrEn_MASK 0x20000 +#define D0F0xCC_x01_CsrEnable_OFFSET 18 +#define D0F0xCC_x01_CsrEnable_WIDTH 1 +#define D0F0xCC_x01_CsrEnable_MASK 0x40000 +#define D0F0xCC_x01_SetPowEn_OFFSET 20 +#define D0F0xCC_x01_SetPowEn_WIDTH 1 +#define D0F0xCC_x01_SetPowEn_MASK 0x100000 +#define D0F0xCC_x01_Reserved_22_21_OFFSET 21 +#define D0F0xCC_x01_Reserved_22_21_WIDTH 2 +#define D0F0xCC_x01_Reserved_22_21_MASK 0x600000 +#define D0F0xCC_x01_ApicEnable_OFFSET 23 +#define D0F0xCC_x01_ApicEnable_WIDTH 1 +#define D0F0xCC_x01_ApicEnable_MASK 0x800000 +#define D0F0xCC_x01_ApicRange_OFFSET 24 +#define D0F0xCC_x01_ApicRange_WIDTH 8 +#define D0F0xCC_x01_ApicRange_MASK 0xff000000 + +/// D0F0xCC_x1 +typedef union { + struct { ///< + UINT32 BridgeDis:1 ; ///< + UINT32 Reserved_1_1:2 ; ///< + UINT32 CfgDis:1 ; ///< + UINT32 P2pDis:1 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 ExtDevPlug:1 ; ///< + UINT32 ExtDevCsrEn:1 ; ///< + UINT32 CsrEnable:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_22_21:2 ; ///< + UINT32 ApicEnable:1 ; ///< + UINT32 ApicRange:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xCC_x01_STRUCT; + + +// **** D0F0xC8 Register Definition **** +// Address +#define D0F0xC8_ADDRESS 0xc8 + +// Type +#define D0F0xC8_TYPE TYPE_D0F0 +// Field Data +#define D0F0xC8_NB_DEV_IND_ADDR_OFFSET 0 +#define D0F0xC8_NB_DEV_IND_ADDR_WIDTH 7 +#define D0F0xC8_NB_DEV_IND_ADDR_MASK 0x7F +#define D0F0xC8_Reserved_15_7_OFFSET 7 +#define D0F0xC8_Reserved_15_7_WIDTH 9 +#define D0F0xC8_Reserved_15_7_MASK 0xFF80 +#define D0F0xC8_NB_DEV_IND_SEL_OFFSET 16 +#define D0F0xC8_NB_DEV_IND_SEL_WIDTH 8 +#define D0F0xC8_NB_DEV_IND_SEL_MASK 0xFF0000 +#define D0F0xC8_Reserved_31_24_OFFSET 24 +#define D0F0xC8_Reserved_31_24_WIDTH 8 +#define D0F0xC8_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xC8 +typedef union { + struct { ///< + UINT32 NB_DEV_IND_ADDR:7; ///< + UINT32 Reserved_15_7:9; ///< + UINT32 NB_DEV_IND_SEL:8; ///< + UINT32 Reserved_31_24:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xC8_STRUCT; + + + +#ifdef _GNBPCIEINITLIBV4_H_ + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGateDigCEnable:1 ; ///< + UINT32 DdiGateDigDEnable:1 ; ///< + UINT32 SpareRegRw:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +#endif + +#ifdef _GNBPCIEINITLIBV5_H_ // KV version of WRAP_8014 + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Type +#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_OFFSET 2 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifa1xGateEnable_MASK 0x4 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_OFFSET 3 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifb1xGateEnable_MASK 0x8 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_OFFSET 4 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifc1xGateEnable_MASK 0x10 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_OFFSET 5 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiPifd1xGateEnable_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_11_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_WIDTH 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_MASK 0xfc0 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET 14 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK 0x4000 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET 15 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK 0x8000 +#define D0F0xE4_WRAP_8014_Reserved_19_16_OFFSET 16 +#define D0F0xE4_WRAP_8014_Reserved_19_16_WIDTH 4 +#define D0F0xE4_WRAP_8014_Reserved_19_16_MASK 0xf0000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3 +#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xe00000 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigaGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_OFFSET 25 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigbGateEnable_MASK 0x2000000 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_OFFSET 26 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigcGateEnable_MASK 0x4000000 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_OFFSET 27 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiDigdGateEnable_MASK 0x8000000 +#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28 +#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4 +#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiPifa1xGateEnable:1 ; ///< + UINT32 DdiPifb1xGateEnable:1 ; ///< + UINT32 DdiPifc1xGateEnable:1 ; ///< + UINT32 DdiPifd1xGateEnable:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdiDigaGateEnable:1 ; ///< + UINT32 DdiDigbGateEnable:1 ; ///< + UINT32 DdiDigcGateEnable:1 ; ///< + UINT32 DdiDigdGateEnable:1 ; ///< + UINT32 SpareRegRw:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8029 Register Definition **** +// Address +#define D0F0xE4_WRAP_8029_ADDRESS 0x8029 +// Type +#define D0F0xE4_WRAP_8029_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8029_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8029_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8029_LaneEnable_MASK 0xFFFF +#define D0F0xE4_WRAP_8029_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_WRAP_8029 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8029_STRUCT; + +#endif + +#ifdef _GNBPCIETRAININGV2_H_ + +// **** DxFxx68 Register Definition **** +// Address +#define DxFxx68_ADDRESS 0x68 +// Type +#define DxFxx68_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx68_PmControl_OFFSET 0 +#define DxFxx68_PmControl_WIDTH 2 +#define DxFxx68_PmControl_MASK 0x3 +#define DxFxx68_Reserved_2_2_OFFSET 2 +#define DxFxx68_Reserved_2_2_WIDTH 1 +#define DxFxx68_Reserved_2_2_MASK 0x4 +#define DxFxx68_ReadCplBoundary_OFFSET 3 +#define DxFxx68_ReadCplBoundary_WIDTH 1 +#define DxFxx68_ReadCplBoundary_MASK 0x8 +#define DxFxx68_LinkDis_OFFSET 4 +#define DxFxx68_LinkDis_WIDTH 1 +#define DxFxx68_LinkDis_MASK 0x10 +#define DxFxx68_RetrainLink_OFFSET 5 +#define DxFxx68_RetrainLink_WIDTH 1 +#define DxFxx68_RetrainLink_MASK 0x20 +#define DxFxx68_CommonClockCfg_OFFSET 6 +#define DxFxx68_CommonClockCfg_WIDTH 1 +#define DxFxx68_CommonClockCfg_MASK 0x40 +#define DxFxx68_ExtendedSync_OFFSET 7 +#define DxFxx68_ExtendedSync_WIDTH 1 +#define DxFxx68_ExtendedSync_MASK 0x80 +#define DxFxx68_ClockPowerManagementEn_OFFSET 8 +#define DxFxx68_ClockPowerManagementEn_WIDTH 1 +#define DxFxx68_ClockPowerManagementEn_MASK 0x100 +#define DxFxx68_HWAutonomousWidthDisable_OFFSET 9 +#define DxFxx68_HWAutonomousWidthDisable_WIDTH 1 +#define DxFxx68_HWAutonomousWidthDisable_MASK 0x200 +#define DxFxx68_LinkBWManagementEn_OFFSET 10 +#define DxFxx68_LinkBWManagementEn_WIDTH 1 +#define DxFxx68_LinkBWManagementEn_MASK 0x400 +#define DxFxx68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxFxx68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxFxx68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxFxx68_Reserved_15_12_OFFSET 12 +#define DxFxx68_Reserved_15_12_WIDTH 4 +#define DxFxx68_Reserved_15_12_MASK 0xF000 +#define DxFxx68_LinkSpeed_OFFSET 16 +#define DxFxx68_LinkSpeed_WIDTH 4 +#define DxFxx68_LinkSpeed_MASK 0xF0000 +#define DxFxx68_NegotiatedLinkWidth_OFFSET 20 +#define DxFxx68_NegotiatedLinkWidth_WIDTH 6 +#define DxFxx68_NegotiatedLinkWidth_MASK 0x3F00000 +#define DxFxx68_Reserved_26_26_OFFSET 26 +#define DxFxx68_Reserved_26_26_WIDTH 1 +#define DxFxx68_Reserved_26_26_MASK 0x4000000 +#define DxFxx68_LinkTraining_OFFSET 27 +#define DxFxx68_LinkTraining_WIDTH 1 +#define DxFxx68_LinkTraining_MASK 0x8000000 +#define DxFxx68_SlotClockCfg_OFFSET 28 +#define DxFxx68_SlotClockCfg_WIDTH 1 +#define DxFxx68_SlotClockCfg_MASK 0x10000000 +#define DxFxx68_DlActive_OFFSET 29 +#define DxFxx68_DlActive_WIDTH 1 +#define DxFxx68_DlActive_MASK 0x20000000 +#define DxFxx68_LinkBWManagementStatus_OFFSET 30 +#define DxFxx68_LinkBWManagementStatus_WIDTH 1 +#define DxFxx68_LinkBWManagementStatus_MASK 0x40000000 +#define DxFxx68_LinkAutonomousBWStatus_OFFSET 31 +#define DxFxx68_LinkAutonomousBWStatus_WIDTH 1 +#define DxFxx68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxFxx68 +typedef union { + struct { ///< + UINT32 PmControl:2; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 ReadCplBoundary:1; ///< + UINT32 LinkDis:1; ///< + UINT32 RetrainLink:1; ///< + UINT32 CommonClockCfg:1; ///< + UINT32 ExtendedSync:1; ///< + UINT32 ClockPowerManagementEn:1; ///< + UINT32 HWAutonomousWidthDisable:1; ///< + UINT32 LinkBWManagementEn:1; ///< + UINT32 LinkAutonomousBWIntEn:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 LinkSpeed:4; ///< + UINT32 NegotiatedLinkWidth:6; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 LinkTraining:1; ///< + UINT32 SlotClockCfg:1; ///< + UINT32 DlActive:1; ///< + UINT32 LinkBWManagementStatus:1; ///< + UINT32 LinkAutonomousBWStatus:1; ///< + + } Field; + + UINT32 Value; +} DxFxx68_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_0800_STRUCT; + +// **** DxFxx128 Register Definition **** +// Address +#define DxFxx128_ADDRESS 0x128 +// Type +#define DxFxx128_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx128_Reserved_15_0_OFFSET 0 +#define DxFxx128_Reserved_15_0_WIDTH 16 +#define DxFxx128_Reserved_15_0_MASK 0xFFFF +#define DxFxx128_PortArbTableStatus_OFFSET 16 +#define DxFxx128_PortArbTableStatus_WIDTH 1 +#define DxFxx128_PortArbTableStatus_MASK 0x10000 +#define DxFxx128_VcNegotiationPending_OFFSET 17 +#define DxFxx128_VcNegotiationPending_WIDTH 1 +#define DxFxx128_VcNegotiationPending_MASK 0x20000 +#define DxFxx128_Reserved_31_18_OFFSET 18 +#define DxFxx128_Reserved_31_18_WIDTH 14 +#define DxFxx128_Reserved_31_18_MASK 0xFFFC0000 + +/// DxFxx128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1; ///< + UINT32 VcNegotiationPending:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} DxFxx128_STRUCT; + +// **** DxFxx18 Register Definition **** +// Address +#define DxFxx18_ADDRESS 0x18 +// Type +#define DxFxx18_TYPE TYPE_D2F1 + +// **** DxFxx20 Register Definition **** +// Address +#define DxFxx20_ADDRESS 0x20 +// Type +#define DxFxx20_TYPE TYPE_D2F1 + +// **** DxFxx24 Register Definition **** +// Address +#define DxFxx24_ADDRESS 0x24 +// Type +#define DxFxx24_TYPE TYPE_D2F1 + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 +// Type +#define D0F0x04_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_19_3_OFFSET 3 +#define D0F0x04_Reserved_19_3_WIDTH 17 +#define D0F0x04_Reserved_19_3_MASK 0xFFFF8 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_Reserved_31_21_OFFSET 21 +#define D0F0x04_Reserved_31_21_WIDTH 11 +#define D0F0x04_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1; ///< + UINT32 MemAccessEn:1; ///< + UINT32 BusMasterEn:1; ///< + UINT32 Reserved_19_3:17; ///< + UINT32 CapList:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0x04_STRUCT; + +#endif + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_X2Lane98_OFFSET 4 +#define D0F0xE4_PIF_0011_X2Lane98_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane98_MASK 0x10 +#define D0F0xE4_PIF_0011_X2Lane1110_OFFSET 5 +#define D0F0xE4_PIF_0011_X2Lane1110_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1110_MASK 0x20 +#define D0F0xE4_PIF_0011_X2Lane1312_OFFSET 6 +#define D0F0xE4_PIF_0011_X2Lane1312_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1312_MASK 0x40 +#define D0F0xE4_PIF_0011_X2Lane1514_OFFSET 7 +#define D0F0xE4_PIF_0011_X2Lane1514_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1514_MASK 0x80 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_X4Lane118_OFFSET 10 +#define D0F0xE4_PIF_0011_X4Lane118_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane118_MASK 0x400 +#define D0F0xE4_PIF_0011_X4Lane1512_OFFSET 11 +#define D0F0xE4_PIF_0011_X4Lane1512_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane1512_MASK 0x800 +#define D0F0xE4_PIF_0011_Reserved_15_12_OFFSET 12 +#define D0F0xE4_PIF_0011_Reserved_15_12_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_15_12_MASK 0xf000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_X8Lane158_OFFSET 17 +#define D0F0xE4_PIF_0011_X8Lane158_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane158_MASK 0x20000 +#define D0F0xE4_PIF_0011_Reserved_19_18_OFFSET 18 +#define D0F0xE4_PIF_0011_Reserved_19_18_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_19_18_MASK 0xc0000 +#define D0F0xE4_PIF_0011_X16Lane150_OFFSET 20 +#define D0F0xE4_PIF_0011_X16Lane150_WIDTH 1 +#define D0F0xE4_PIF_0011_X16Lane150_MASK 0x100000 +#define D0F0xE4_PIF_0011_Reserved_24_21_OFFSET 21 +#define D0F0xE4_PIF_0011_Reserved_24_21_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_24_21_MASK 0x1e00000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 X2Lane98:1 ; ///< + UINT32 X2Lane1110:1 ; ///< + UINT32 X2Lane1312:1 ; ///< + UINT32 X2Lane1514:1 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 X4Lane118:1 ; ///< + UINT32 X4Lane1512:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 X8Lane158:1 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 X16Lane150:1 ; ///< + UINT32 Reserved_24_21:4 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + + +// **** D0F0xE4_PIF_0017 Register Definition **** +// Address +#define D0F0xE4_PIF_0017_ADDRESS 0x17 + +// Type +#define D0F0xE4_PIF_0017_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0017_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0017_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0017_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0017_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0017_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0017_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0017_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0017_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0017_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0017_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0017_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0017_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0017_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0017_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0017_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0017_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0017 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0017_STRUCT; + + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Bitfield_6_6_MASK 0x40 +#define D0F0xE4_CORE_00B0_Reserved_31_7_OFFSET 7 +#define D0F0xE4_CORE_00B0_Reserved_31_7_WIDTH 25 +#define D0F0xE4_CORE_00B0_Reserved_31_7_MASK 0xffffff80 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 StrapF0AerEn:1 ; ///< + UINT32 Bitfield_6_6:1 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; +typedef union { + struct { ///< + UINT32 Bitfield_0_0:1; ///< + UINT32 Bitfield_1_1:1 ; ///< + UINT32 Reserved_15_2:14; ///< + UINT32 Bitfield_16_16:1; ///< + UINT32 Bitfield_17_17:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} GRC2_STRUCT; + + + +#endif + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h new file mode 100644 index 0000000000..a469eb35a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h @@ -0,0 +1,3954 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88282 $ @e \$Date: 2013-02-19 11:20:56 -0600 (Tue, 19 Feb 2013) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +#ifndef _GNBREGISTERSKB_H_ +#define _GNBREGISTERSKB_H_ +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xBC 0x4 +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_D18F4 0xe +#define TYPE_D18F5 0xf +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define TYPE_D18F2x9C_dct0 0x13 +#define TYPE_D18F2x9C_dct0_mp0 0x14 +#define TYPE_D18F2x9C_dct0_mp1 0x15 +#define TYPE_D18F2x9C_dct1 0x16 +#define TYPE_D18F2x9C_dct1_mp0 0x17 +#define TYPE_D18F2x9C_dct1_mp1 0x18 +#define TYPE_D18F2_dct0 0x19 +#define TYPE_D18F2_dct1 0x1a +#define TYPE_D18F2_dct0_mp0 0x1b +#define TYPE_D18F2_dct0_mp1 0x1c +#define TYPE_D1F1 0x1d +#define TYPE_D18F2_dct1_mp0 0x1e +#define TYPE_D18F2_dct1_mp1 0x1f +#define TYPE_CGIND 0x20 +#define TYPE_SMU_MSG 0x21 +#define TYPE_D0F0xD4 0x22 +#define TYPE_D18F0 0x24 + +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + +#define INVALID_SMU_MSG 0xFF +#define SMU_MSG_TYPE TYPE_SMU_MSG +#define SMC_MSG_TEST INVALID_SMU_MSG // 1 +#define SMC_MSG_PHY_LN_OFF INVALID_SMU_MSG // 2 +#define SMC_MSG_PHY_LN_ON INVALID_SMU_MSG // 3 +#define SMC_MSG_DDI_PHY_OFF INVALID_SMU_MSG // 4 +#define SMC_MSG_DDI_PHY_ON INVALID_SMU_MSG // 5 +#define SMC_MSG_CASCADE_PLL_OFF INVALID_SMU_MSG // 6 +#define SMC_MSG_CASCADE_PLL_ON INVALID_SMU_MSG // 7 +#define SMC_MSG_PWR_OFF_x16 INVALID_SMU_MSG // 8 +#define SMC_MSG_FLUSH_DATA_CACHE INVALID_SMU_MSG // 10 +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE INVALID_SMU_MSG // 11 +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 12 +#define SMC_MSG_RECONFIGURE_SB 25 +#define SMC_MSG_UPDATE_BAPM INVALID_SMU_MSG // 26 +#define SMC_MSG_PCIE_PLLSWITCH INVALID_SMU_MSG // 27 +#define SMC_MSG_FORCE_LCLK_DPM_STATE INVALID_SMU_MSG // 28 +#define SMC_MSG_UNFORCE_LCLK_DPM_STATE INVALID_SMU_MSG // 29 +#define SMC_MSG_LCLK_DPM_ENABLE 30 +#define SMC_MSG_LCLK_DPM_DISABLE 31 +#define SMC_MSG_DDI_PHY_IDLE INVALID_SMU_MSG // 34 +#define SMC_MSG_DDI_PHY_BUSY INVALID_SMU_MSG // 35 +#define SMC_MSG_DSMU INVALID_SMU_MSG // 36 +#define SMC_MSG_NBDPM_DISABLE INVALID_SMU_MSG // 37 +#define SMC_MSG_NBDPM_FORCENOMINAL INVALID_SMU_MSG // 38 +#define SMC_MSG_NBDPM_FORCEPERFORMANCE INVALID_SMU_MSG // 39 +#define SMC_MSG_NBDPM_UNFORCE INVALID_SMU_MSG // 40 +#define SMC_MSG_RESET INVALID_SMU_MSG // 41 +#define SMC_MSG_AVS_ENABLE INVALID_SMU_MSG // 42 +#define SMC_MSG_AVS_DISABLE INVALID_SMU_MSG // 43 +#define SMC_MSG_LPMX_ENABLE INVALID_SMU_MSG // 44 +#define SMC_MSG_LPMX_DISABLE INVALID_SMU_MSG // 45 +#define SMC_MSG_TDC_LIMIT_DISABLE 47 +#define SMC_MSG_BAPM_DISABLE 49 +#define SMC_MSG_TDP_LIMIT_ENABLE INVALID_SMU_MSG // 50 +#define SMC_MSG_TDP_LIMIT_DISABLE INVALID_SMU_MSG // 51 +#define SMC_MSG_SPMI_ENABLE INVALID_SMU_MSG // 52 +#define SMC_MSG_SPMI_DISABLE INVALID_SMU_MSG // 53 +#define SMC_MSG_SPMI_TEST INVALID_SMU_MSG // 54 +#define SMC_MSG_EXT_API INVALID_SMU_MSG // 55 +#define SMC_MSG_THERMAL_CNTL_DISABLE 57 +#define SMC_MSG_VDDNB_REQUEST 58 +#define SMC_MSG_VOLTAGE_CNTL_ENABLE 59 +#define SMC_MSG_VOLTAGE_CNTL_DISABLE 60 +#define SMC_MSG_NBDPM_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MCARB_UPDATE_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MCARB_UPDATE_DISABLE INVALID_SMU_MSG +#define SMC_MSG_LHTC_LIMIT_DISABLE 71 +#define SMC_MSG_PWR_OFF_IOMMU INVALID_SMU_MSG +#define SMC_MSG_PWR_ON_IOMMU INVALID_SMU_MSG +#define SMC_MSG_MONITOR_PORT80_ENABLE INVALID_SMU_MSG +#define SMC_MSG_MONITOR_PORT80_DISABLE INVALID_SMU_MSG +#define SMC_MSG_LCLKDPM_SETENABLEMASK INVALID_SMU_MSG +#define SMC_MSG_READ_SCS 80 +#define SMC_MSG_ENABLE_PKGPWRLIMIT 81 +#define SMC_MSG_DISABLE_PKGPWRLIMIT 82 +#define SMC_MSG_ENABLE_ALLCLK_MONITOR 83 +#define SMC_MSG_DISABLE_ALLCLK_MONITOR INVALID_SMU_MSG +#define SMC_MSG_LHTC_LIMIT_SetLimit 90 // 0x5A + +#define L1_SEL_PPD 0 +#define L1_SEL_BIF 1 +#define L1_SEL_INTGEN 2 + +// **** D18F0x110 Register Definition **** +// Address +#define D18F0x110_ADDRESS 0x110 + +// Type +#define D18F0x110_TYPE TYPE_D18F0 + +// **** D18F1x44 Register Definition **** +// Address +#define D18F1x44_ADDRESS 0x44 +// Type +#define D18F1x44_TYPE TYPE_D18F1 + +// Field Data +#define D18F1x44_DstNode_OFFSET 0 +#define D18F1x44_DstNode_WIDTH 3 +#define D18F1x44_DstNode_MASK 0x7 +#define D18F1x44_Reserved_7_3_OFFSET 3 +#define D18F1x44_Reserved_7_3_WIDTH 5 +#define D18F1x44_Reserved_7_3_MASK 0xF8 +#define D18F1x44_Reserved_10_8_OFFSET 8 +#define D18F1x44_Reserved_10_8_WIDTH 3 +#define D18F1x44_Reserved_10_8_MASK 0x700 +#define D18F1x44_Reserved_15_11_OFFSET 11 +#define D18F1x44_Reserved_15_11_WIDTH 5 +#define D18F1x44_Reserved_15_11_MASK 0xF800 +#define D18F1x44_DramLimit_39_24_OFFSET 16 +#define D18F1x44_DramLimit_39_24_WIDTH 16 +#define D18F1x44_DramLimit_39_24_MASK 0xFFFF0000 + +/// D18F1x44 +typedef union { + struct { ///< + UINT32 DstNode:3; ///< + UINT32 Reserved_7_3:5; ///< + UINT32 Reserved_10_8:3; ///< + UINT32 Reserved_15_11:5; ///< + UINT32 DramLimit_39_24:16; ///< + + } Field; + + UINT32 Value; +} D18F1x44_STRUCT; + + + +// **** D18F2x90_dct0 Register Definition **** +// Address +#define D18F2x90_dct0_ADDRESS 0x90 +// Type +#define D18F2x90_dct0_TYPE TYPE_D18F2 + +// Field Data +#define D18F2x90_dct0_ExitSelfRef_OFFSET 1 +#define D18F2x90_dct0_ExitSelfRef_WIDTH 1 +#define D18F2x90_dct0_ExitSelfRef_MASK 0x2 +#define D18F2x90_dct0_Reserved_7_2_OFFSET 2 +#define D18F2x90_dct0_Reserved_7_2_WIDTH 6 +#define D18F2x90_dct0_Reserved_7_2_MASK 0xfc +#define D18F2x90_dct0_Reserved_8_8_OFFSET 8 +#define D18F2x90_dct0_Reserved_8_8_WIDTH 1 +#define D18F2x90_dct0_Reserved_8_8_MASK 0x100 +#define D18F2x90_dct0_Reserved_10_9_OFFSET 9 +#define D18F2x90_dct0_Reserved_10_9_WIDTH 2 +#define D18F2x90_dct0_Reserved_10_9_MASK 0x600 +#define D18F2x90_dct0_Reserved_11_11_OFFSET 11 +#define D18F2x90_dct0_Reserved_11_11_WIDTH 1 +#define D18F2x90_dct0_Reserved_11_11_MASK 0x800 +#define D18F2x90_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x90_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x90_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x90_dct0_UnbuffDimm_OFFSET 16 +#define D18F2x90_dct0_UnbuffDimm_WIDTH 1 +#define D18F2x90_dct0_UnbuffDimm_MASK 0x10000 +#define D18F2x90_dct0_UnbuffDimm_VALUE 0x1 +#define D18F2x90_dct0_EnterSelfRef_OFFSET 17 +#define D18F2x90_dct0_EnterSelfRef_WIDTH 1 +#define D18F2x90_dct0_EnterSelfRef_MASK 0x20000 +#define D18F2x90_dct0_PendRefPayback_OFFSET 18 +#define D18F2x90_dct0_PendRefPayback_WIDTH 1 +#define D18F2x90_dct0_PendRefPayback_MASK 0x40000 +#define D18F2x90_dct0_PendRefPayback_VALUE 0x0 +#define D18F2x90_dct0_DimmEccEn_OFFSET 19 +#define D18F2x90_dct0_DimmEccEn_WIDTH 1 +#define D18F2x90_dct0_DimmEccEn_MASK 0x80000 +#define D18F2x90_dct0_DynPageCloseEn_OFFSET 20 +#define D18F2x90_dct0_DynPageCloseEn_WIDTH 1 +#define D18F2x90_dct0_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_dct0_IdleCycLowLimit_OFFSET 21 +#define D18F2x90_dct0_IdleCycLowLimit_WIDTH 2 +#define D18F2x90_dct0_IdleCycLowLimit_MASK 0x600000 +#define D18F2x90_dct0_ForceAutoPchg_OFFSET 23 +#define D18F2x90_dct0_ForceAutoPchg_WIDTH 1 +#define D18F2x90_dct0_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_dct0_StagRefEn_OFFSET 24 +#define D18F2x90_dct0_StagRefEn_WIDTH 1 +#define D18F2x90_dct0_StagRefEn_MASK 0x1000000 +#define D18F2x90_dct0_StagRefEn_VALUE 0x1 +#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET 25 +#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH 1 +#define D18F2x90_dct0_PendRefPaybackS3En_MASK 0x2000000 +#define D18F2x90_dct0_PendRefPaybackS3En_VALUE 0x1 +#define D18F2x90_dct0_Reserved_26_26_OFFSET 26 +#define D18F2x90_dct0_Reserved_26_26_WIDTH 1 +#define D18F2x90_dct0_Reserved_26_26_MASK 0x4000000 +#define D18F2x90_dct0_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_dct0_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_dct0_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_dct0_IdleCycLimit_OFFSET 28 +#define D18F2x90_dct0_IdleCycLimit_WIDTH 4 +#define D18F2x90_dct0_IdleCycLimit_MASK 0xf0000000 +#define D18F2x90_dct0_IdleCycLimit_VALUE 0x8 + +/// D18F2x90_dct0 +typedef union { + struct { ///< + UINT32 ExitSelfRef:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_10_9:2 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 UnbuffDimm:1 ; ///< + UINT32 EnterSelfRef:1 ; ///< + UINT32 PendRefPayback:1 ; ///< + UINT32 DimmEccEn:1 ; ///< + UINT32 DynPageCloseEn:1 ; ///< + UINT32 IdleCycLowLimit:2 ; ///< + UINT32 ForceAutoPchg:1 ; ///< + UINT32 StagRefEn:1 ; ///< + UINT32 PendRefPaybackS3En:1 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 DisDllShutdownSR:1 ; ///< + UINT32 IdleCycLimit:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x90_dct0_STRUCT; + + +// **** D18F2x94_dct0 Register Definition **** +// Address +#define D18F2x94_dct0_ADDRESS 0x94 +// Type +#define D18F2x94_dct0_TYPE TYPE_D18F2_dct0 + +// Field Data +#define D18F2x94_dct0_MemClkFreq_OFFSET 0 +#define D18F2x94_dct0_MemClkFreq_WIDTH 5 +#define D18F2x94_dct0_MemClkFreq_MASK 0x1f +#define D18F2x94_dct0_Reserved_6_5_OFFSET 5 +#define D18F2x94_dct0_Reserved_6_5_WIDTH 2 +#define D18F2x94_dct0_Reserved_6_5_MASK 0x60 +#define D18F2x94_dct0_MemClkFreqVal_OFFSET 7 +#define D18F2x94_dct0_MemClkFreqVal_WIDTH 1 +#define D18F2x94_dct0_MemClkFreqVal_MASK 0x80 +#define D18F2x94_dct0_Reserved_9_8_OFFSET 8 +#define D18F2x94_dct0_Reserved_9_8_WIDTH 2 +#define D18F2x94_dct0_Reserved_9_8_MASK 0x300 +#define D18F2x94_dct0_ZqcsInterval_OFFSET 10 +#define D18F2x94_dct0_ZqcsInterval_WIDTH 2 +#define D18F2x94_dct0_ZqcsInterval_MASK 0xc00 +#define D18F2x94_dct0_RDqsEn_OFFSET 12 +#define D18F2x94_dct0_RDqsEn_WIDTH 1 +#define D18F2x94_dct0_RDqsEn_MASK 0x1000 +#define D18F2x94_dct0_Reserved_13_13_OFFSET 13 +#define D18F2x94_dct0_Reserved_13_13_WIDTH 1 +#define D18F2x94_dct0_Reserved_13_13_MASK 0x2000 +#define D18F2x94_dct0_DisDramInterface_OFFSET 14 +#define D18F2x94_dct0_DisDramInterface_WIDTH 1 +#define D18F2x94_dct0_DisDramInterface_MASK 0x4000 +#define D18F2x94_dct0_PowerDownEn_OFFSET 15 +#define D18F2x94_dct0_PowerDownEn_WIDTH 1 +#define D18F2x94_dct0_PowerDownEn_MASK 0x8000 +#define D18F2x94_dct0_PowerDownMode_OFFSET 16 +#define D18F2x94_dct0_PowerDownMode_WIDTH 1 +#define D18F2x94_dct0_PowerDownMode_MASK 0x10000 +#define D18F2x94_dct0_PowerDownMode_VALUE 0x1 +#define D18F2x94_dct0_Reserved_17_17_OFFSET 17 +#define D18F2x94_dct0_Reserved_17_17_WIDTH 1 +#define D18F2x94_dct0_Reserved_17_17_MASK 0x20000 +#define D18F2x94_dct0_Reserved_18_18_OFFSET 18 +#define D18F2x94_dct0_Reserved_18_18_WIDTH 1 +#define D18F2x94_dct0_Reserved_18_18_MASK 0x40000 +#define D18F2x94_dct0_Reserved_19_19_OFFSET 19 +#define D18F2x94_dct0_Reserved_19_19_WIDTH 1 +#define D18F2x94_dct0_Reserved_19_19_MASK 0x80000 +#define D18F2x94_dct0_SlowAccessMode_OFFSET 20 +#define D18F2x94_dct0_SlowAccessMode_WIDTH 1 +#define D18F2x94_dct0_SlowAccessMode_MASK 0x100000 +#define D18F2x94_dct0_FreqChgInProg_OFFSET 21 +#define D18F2x94_dct0_FreqChgInProg_WIDTH 1 +#define D18F2x94_dct0_FreqChgInProg_MASK 0x200000 +#define D18F2x94_dct0_BankSwizzleMode_OFFSET 22 +#define D18F2x94_dct0_BankSwizzleMode_WIDTH 1 +#define D18F2x94_dct0_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_dct0_ProcOdtDis_OFFSET 23 +#define D18F2x94_dct0_ProcOdtDis_WIDTH 1 +#define D18F2x94_dct0_ProcOdtDis_MASK 0x800000 +#define D18F2x94_dct0_DcqBypassMax_OFFSET 24 +#define D18F2x94_dct0_DcqBypassMax_WIDTH 5 +#define D18F2x94_dct0_DcqBypassMax_MASK 0x1f000000 +#define D18F2x94_dct0_Reserved_30_29_OFFSET 29 +#define D18F2x94_dct0_Reserved_30_29_WIDTH 2 +#define D18F2x94_dct0_Reserved_30_29_MASK 0x60000000 +#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET 31 +#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH 1 +#define D18F2x94_dct0_DphyMemPsSelEn_MASK 0x80000000 +#define D18F2x94_dct0_DphyMemPsSelEn_VALUE 0x1 + +/// D18F2x94_dct0 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 RDqsEn:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 FreqChgInProg:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:5 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 DphyMemPsSelEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_dct0_STRUCT; + +#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET 16 +#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH 2 + +// **** D18F2x2E0_dct0 Register Definition **** +// Address +#define D18F2x2E0_dct0_ADDRESS 0x2e0 + +// Type +#define D18F2x2E0_dct0_TYPE TYPE_D18F2 +// Field Data + +#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET 24 +#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH 5 + +/// D18F2x2E0_dct0 +typedef union { + struct { ///< + UINT32 Reserved_1:1 ; ///< + UINT32 Reserved_19_1:19; ///< + UINT32 Reserved_22_20:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 M1MemClkFreq:5 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E0_dct0_STRUCT; + +// **** D18F4x110 Register Definition **** +// Address +#define D18F4x110_ADDRESS 0x110 + +// Type +#define D18F4x110_TYPE TYPE_D18F4 +// Field Data +#define D18F4x110_CSampleTimer_OFFSET 0 +#define D18F4x110_CSampleTimer_WIDTH 12 +#define D18F4x110_CSampleTimer_MASK 0xfff +#define D18F4x110_CSampleTimer_VALUE 0x2 +#define D18F4x110_FastCSampleTimer_OFFSET 12 +#define D18F4x110_FastCSampleTimer_WIDTH 1 +#define D18F4x110_FastCSampleTimer_MASK 0x1000 +#define D18F4x110_MinResTmr_OFFSET 13 +#define D18F4x110_MinResTmr_WIDTH 8 +#define D18F4x110_MinResTmr_MASK 0x1fe000 +#define D18F4x110_Reserved_31_21_OFFSET 21 +#define D18F4x110_Reserved_31_21_WIDTH 11 +#define D18F4x110_Reserved_31_21_MASK 0xffe00000 + +/// D18F4x110 +typedef union { + struct { ///< + UINT32 CSampleTimer:12; ///< + UINT32 FastCSampleTimer:1 ; ///< + UINT32 MinResTmr:8 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x110_STRUCT; + +// **** D18F5xE0 Register Definition **** +// Address +#define D18F5xE0_ADDRESS 0xe0 + +// Type +#define D18F5xE0_TYPE TYPE_D18F5 +// Field Data +#define D18F5xE0_RunAvgRange_OFFSET 0 +#define D18F5xE0_RunAvgRange_WIDTH 4 +#define D18F5xE0_RunAvgRange_MASK 0xf +#define D18F5xE0_RunAvgRange_VALUE 0x2 +#define D18F5xE0_Reserved_31_4_OFFSET 4 +#define D18F5xE0_Reserved_31_4_WIDTH 28 +#define D18F5xE0_Reserved_31_4_MASK 0xfffffff0 + +/// D18F5xE0 +typedef union { + struct { ///< + UINT32 RunAvgRange:4 ; ///< + UINT32 Reserved_31_4:28 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5xE0_STRUCT; + +// **** D18F5x160 Register Definition **** +// Address +#define D18F5x160_ADDRESS 0x160 + +// Type +#define D18F5x160_TYPE TYPE_D18F5 +#define D18F5x160_NbPstateEn_OFFSET 0 +#define D18F5x160_NbPstateEn_WIDTH 1 + +#define D18F5x160_MemPstate_OFFSET 18 +#define D18F5x160_MemPstate_WIDTH 1 +#define D18F5x160_NbFid_OFFSET 1 +#define D18F5x160_NbFid_WIDTH 6 +#define D18F5x160_NbDid_OFFSET 7 +#define D18F5x160_NbDid_WIDTH 1 +#define D18F5x160_NbVid_6_0_OFFSET 10 +#define D18F5x160_NbVid_6_0_WIDTH 7 +#define D18F5x160_NbVid_7_OFFSET 21 +#define D18F5x160_NbVid_7_WIDTH 1 + +#define D18F5x160_NbVid_7__OFFSET 21 +#define D18F5x160_NbVid_7__WIDTH 1 + +/// D18F5x160 +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x160_STRUCT; + +// **** D18F5x164 Register Definition **** +// Address +#define D18F5x164_ADDRESS 0x164 + +// Type +#define D18F5x164_TYPE TYPE_D18F5 +#define D18F5x164_NbPstateEn_OFFSET 0 +#define D18F5x164_NbPstateEn_WIDTH 1 +#define D18F5x164_MemPstate_OFFSET 18 +#define D18F5x164_MemPstate_WIDTH 1 +#define D18F5x164_NbFid_OFFSET 1 +#define D18F5x164_NbFid_WIDTH 6 +#define D18F5x164_NbDid_OFFSET 7 +#define D18F5x164_NbDid_WIDTH 1 +#define D18F5x164_NbVid_6_0_OFFSET 10 +#define D18F5x164_NbVid_6_0_WIDTH 7 +#define D18F5x164_NbVid_7_OFFSET 21 +#define D18F5x164_NbVid_7_WIDTH 1 + +// **** D18F5x168 Register Definition **** +// Address +#define D18F5x168_ADDRESS 0x168 + +// Type +#define D18F5x168_TYPE TYPE_D18F5 +#define D18F5x168_NbPstateEn_OFFSET 0 +#define D18F5x168_NbPstateEn_WIDTH 1 +#define D18F5x168_NbFid_OFFSET 1 +#define D18F5x168_NbFid_WIDTH 6 +#define D18F5x168_NbDid_OFFSET 7 +#define D18F5x168_NbDid_WIDTH 1 +#define D18F5x168_NbVid_6_0_OFFSET 10 +#define D18F5x168_NbVid_6_0_WIDTH 7 +#define D18F5x168_MemPstate_OFFSET 18 +#define D18F5x168_MemPstate_WIDTH 1 +#define D18F5x168_NbVid_7_OFFSET 21 +#define D18F5x168_NbVid_7_WIDTH 1 + +// **** D18F5x16C Register Definition **** +// Address +#define D18F5x16C_ADDRESS 0x16c + +// Type +#define D18F5x16C_TYPE TYPE_D18F5 +#define D18F5x16C_NbPstateEn_OFFSET 0 +#define D18F5x16C_NbPstateEn_WIDTH 1 +#define D18F5x16C_NbFid_OFFSET 1 +#define D18F5x16C_NbFid_WIDTH 6 +#define D18F5x16C_NbDid_OFFSET 7 +#define D18F5x16C_NbDid_WIDTH 1 +#define D18F5x16C_NbVid_6_0_OFFSET 10 +#define D18F5x16C_NbVid_6_0_WIDTH 7 +#define D18F5x16C_MemPstate_OFFSET 18 +#define D18F5x16C_MemPstate_WIDTH 1 +#define D18F5x16C_NbVid_7_OFFSET 21 +#define D18F5x16C_NbVid_7_WIDTH 1 + +// **** D18F5x170 Register Definition **** +// Address +#define D18F5x170_ADDRESS 0x170 + +// Type +#define D18F5x170_TYPE TYPE_D18F5 +// Field Data +#define D18F5x170_NbPstateMaxVal_OFFSET 0 +#define D18F5x170_NbPstateMaxVal_WIDTH 2 +#define D18F5x170_NbPstateMaxVal_MASK 0x3 +#define D18F5x170_Reserved_2_2_OFFSET 2 +#define D18F5x170_Reserved_2_2_WIDTH 1 +#define D18F5x170_Reserved_2_2_MASK 0x4 +#define D18F5x170_NbPstateLo_OFFSET 3 +#define D18F5x170_NbPstateLo_WIDTH 2 +#define D18F5x170_NbPstateLo_MASK 0x18 +#define D18F5x170_Reserved_5_5_OFFSET 5 +#define D18F5x170_Reserved_5_5_WIDTH 1 +#define D18F5x170_Reserved_5_5_MASK 0x20 +#define D18F5x170_NbPstateHi_OFFSET 6 +#define D18F5x170_NbPstateHi_WIDTH 2 +#define D18F5x170_NbPstateHi_MASK 0xc0 +#define D18F5x170_Reserved_8_8_OFFSET 8 +#define D18F5x170_Reserved_8_8_WIDTH 1 +#define D18F5x170_Reserved_8_8_MASK 0x100 +#define D18F5x170_NbPstateThreshold_OFFSET 9 +#define D18F5x170_NbPstateThreshold_WIDTH 4 +#define D18F5x170_NbPstateThreshold_MASK 0x1e00 +#define D18F5x170_Reserved_12_12_OFFSET 12 +#define D18F5x170_Reserved_12_12_WIDTH 1 +#define D18F5x170_Reserved_12_12_MASK 0x1000 +#define D18F5x170_NbPstateDisOnP0_OFFSET 13 +#define D18F5x170_NbPstateDisOnP0_WIDTH 1 +#define D18F5x170_NbPstateDisOnP0_MASK 0x2000 +#define D18F5x170_SwNbPstateLoDis_OFFSET 14 +#define D18F5x170_SwNbPstateLoDis_WIDTH 1 +#define D18F5x170_SwNbPstateLoDis_MASK 0x4000 +#define D18F5x170_Reserved_22_15_OFFSET 15 +#define D18F5x170_Reserved_22_15_WIDTH 8 +#define D18F5x170_Reserved_22_15_MASK 0x3f8000 +#define D18F5x170_NbPstateGnbSlowDis_OFFSET 23 +#define D18F5x170_NbPstateGnbSlowDis_WIDTH 1 +#define D18F5x170_NbPstateGnbSlowDis_MASK 0x800000 +#define D18F5x170_NbPstateLoRes_OFFSET 24 +#define D18F5x170_NbPstateLoRes_WIDTH 3 +#define D18F5x170_NbPstateLoRes_MASK 0x7000000 +#define D18F5x170_NbPstateHiRes_OFFSET 27 +#define D18F5x170_NbPstateHiRes_WIDTH 3 +#define D18F5x170_NbPstateHiRes_MASK 0x38000000 +#define D18F5x170_NbPstateFidVidSbcEn_OFFSET 30 +#define D18F5x170_NbPstateFidVidSbcEn_WIDTH 1 +#define D18F5x170_NbPstateFidVidSbcEn_MASK 0x40000000 +#define D18F5x170_MemPstateDis_OFFSET 31 +#define D18F5x170_MemPstateDis_WIDTH 1 +#define D18F5x170_MemPstateDis_MASK 0x80000000 + +/// D18F5x170 +typedef union { + struct { ///< + UINT32 NbPstateMaxVal:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NbPstateLo:2 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 NbPstateHi:2 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 NbPstateThreshold:4 ; ///< + UINT32 NbPstateDisOnP0:1 ; ///< + UINT32 SwNbPstateLoDis:1 ; ///< + UINT32 Reserved_22_15:8 ; ///< + UINT32 NbPstateGnbSlowDis:1 ; ///< + UINT32 NbPstateLoRes:3 ; ///< + UINT32 NbPstateHiRes:3 ; ///< + UINT32 NbPstateFidVidSbcEn:1 ; ///< + UINT32 MemPstateDis:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x170_STRUCT; + +// **** D18F2x118 Register Definition **** +// Address +#define D18F2x118_ADDRESS 0x118 +// Type +#define D18F2x118_TYPE TYPE_D18F2 + +// Field Data +#define D18F2x118_MctPriCpuRd_OFFSET 0 +#define D18F2x118_MctPriCpuRd_WIDTH 2 +#define D18F2x118_MctPriCpuRd_MASK 0x3 +#define D18F2x118_MctPriCpuWr_OFFSET 2 +#define D18F2x118_MctPriCpuWr_WIDTH 2 +#define D18F2x118_MctPriCpuWr_MASK 0xC +#define D18F2x118_MctPriIsocRd_OFFSET 4 +#define D18F2x118_MctPriIsocRd_WIDTH 2 +#define D18F2x118_MctPriIsocRd_MASK 0x30 +#define D18F2x118_MctPriIsocWr_OFFSET 6 +#define D18F2x118_MctPriIsocWr_WIDTH 2 +#define D18F2x118_MctPriIsocWr_MASK 0xC0 +#define D18F2x118_MctPriDefault_OFFSET 8 +#define D18F2x118_MctPriDefault_WIDTH 2 +#define D18F2x118_MctPriDefault_MASK 0x300 +#define D18F2x118_MctPriWr_OFFSET 10 +#define D18F2x118_MctPriWr_WIDTH 2 +#define D18F2x118_MctPriWr_MASK 0xC00 +#define D18F2x118_MctPriIsoc_OFFSET 12 +#define D18F2x118_MctPriIsoc_WIDTH 2 +#define D18F2x118_MctPriIsoc_MASK 0x3000 +#define D18F2x118_MctPriTrace_OFFSET 14 +#define D18F2x118_MctPriTrace_WIDTH 2 +#define D18F2x118_MctPriTrace_MASK 0xC000 +#define D18F2x118_MctPriScrub_OFFSET 16 +#define D18F2x118_MctPriScrub_WIDTH 2 +#define D18F2x118_MctPriScrub_MASK 0x30000 +#define D18F2x118_CC6SaveEn_OFFSET 18 +#define D18F2x118_CC6SaveEn_WIDTH 1 +#define D18F2x118_CC6SaveEn_MASK 0x40000 +#define D18F2x118_LockDramCfg_OFFSET 19 +#define D18F2x118_LockDramCfg_WIDTH 1 +#define D18F2x118_LockDramCfg_MASK 0x80000 +#define D18F2x118_McqMedPriByPassMax_OFFSET 20 +#define D18F2x118_McqMedPriByPassMax_WIDTH 3 +#define D18F2x118_McqMedPriByPassMax_MASK 0x700000 +#define D18F2x118_Reserved_23_23_OFFSET 23 +#define D18F2x118_Reserved_23_23_WIDTH 1 +#define D18F2x118_Reserved_23_23_MASK 0x800000 +#define D18F2x118_McqHiPriByPassMax_OFFSET 24 +#define D18F2x118_McqHiPriByPassMax_WIDTH 3 +#define D18F2x118_McqHiPriByPassMax_MASK 0x7000000 +#define D18F2x118_Reserved_27_27_OFFSET 27 +#define D18F2x118_Reserved_27_27_WIDTH 1 +#define D18F2x118_Reserved_27_27_MASK 0x8000000 +#define D18F2x118_MctVarPriCntLmt_OFFSET 28 +#define D18F2x118_MctVarPriCntLmt_WIDTH 4 +#define D18F2x118_MctVarPriCntLmt_MASK 0xF0000000 + +/// D18F2x118 +typedef union { + struct { ///< + UINT32 MctPriCpuRd:2; ///< + UINT32 MctPriCpuWr:2; ///< + UINT32 MctPriIsocRd:2; ///< + UINT32 MctPriIsocWr:2; ///< + UINT32 MctPriDefault:2; ///< + UINT32 MctPriWr:2; ///< + UINT32 MctPriIsoc:2; ///< + UINT32 MctPriTrace:2; ///< + UINT32 MctPriScrub:2; ///< + UINT32 CC6SaveEn:1; ///< + UINT32 LockDramCfg:1; ///< + UINT32 McqMedPriByPassMax:3; ///< + UINT32 Reserved_23_23:1; ///< + UINT32 McqHiPriByPassMax:3; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 MctVarPriCntLmt:4; ///< + + } Field; + + UINT32 Value; +} D18F2x118_STRUCT; + + +// **** D18F3x44 Register Definition **** +// Address +#define D18F3x44_ADDRESS 0x44 + +// Type +#define D18F3x44_TYPE TYPE_D18F3 +// Field Data +#define D18F3x44_Reserved_0_0_OFFSET 0 +#define D18F3x44_Reserved_0_0_WIDTH 1 +#define D18F3x44_Reserved_0_0_MASK 0x1 +#define D18F3x44_CpuRdDatErrEn_OFFSET 1 +#define D18F3x44_CpuRdDatErrEn_WIDTH 1 +#define D18F3x44_CpuRdDatErrEn_MASK 0x2 +#define D18F3x44_SyncFloodOnDramUcEcc_OFFSET 2 +#define D18F3x44_SyncFloodOnDramUcEcc_WIDTH 1 +#define D18F3x44_SyncFloodOnDramUcEcc_MASK 0x4 +#define D18F3x44_SyncFloodOnDramUcEcc_VALUE 0x1 +#define D18F3x44_SyncPktGenDis_OFFSET 3 +#define D18F3x44_SyncPktGenDis_WIDTH 1 +#define D18F3x44_SyncPktGenDis_MASK 0x8 +#define D18F3x44_SyncPktGenDis_VALUE 0x0 +#define D18F3x44_SyncPktPropDis_OFFSET 4 +#define D18F3x44_SyncPktPropDis_WIDTH 1 +#define D18F3x44_SyncPktPropDis_MASK 0x10 +#define D18F3x44_SyncPktPropDis_VALUE 0x0 +#define D18F3x44_IoMstAbortDis_OFFSET 5 +#define D18F3x44_IoMstAbortDis_WIDTH 1 +#define D18F3x44_IoMstAbortDis_MASK 0x20 +#define D18F3x44_CpuErrDis_OFFSET 6 +#define D18F3x44_CpuErrDis_WIDTH 1 +#define D18F3x44_CpuErrDis_MASK 0x40 +#define D18F3x44_CpuErrDis_VALUE 0x1 +#define D18F3x44_IoErrDis_OFFSET 7 +#define D18F3x44_IoErrDis_WIDTH 1 +#define D18F3x44_IoErrDis_MASK 0x80 +#define D18F3x44_WDTDis_OFFSET 8 +#define D18F3x44_WDTDis_WIDTH 1 +#define D18F3x44_WDTDis_MASK 0x100 +#define D18F3x44_WDTCntSel_2_0__OFFSET 9 +#define D18F3x44_WDTCntSel_2_0__WIDTH 3 +#define D18F3x44_WDTCntSel_2_0__MASK 0xe00 +#define D18F3x44_WDTBaseSel_OFFSET 12 +#define D18F3x44_WDTBaseSel_WIDTH 2 +#define D18F3x44_WDTBaseSel_MASK 0x3000 +#define D18F3x44_GenLinkSel_OFFSET 14 +#define D18F3x44_GenLinkSel_WIDTH 2 +#define D18F3x44_GenLinkSel_MASK 0xc000 +#define D18F3x44_GenCrcErrByte0_OFFSET 16 +#define D18F3x44_GenCrcErrByte0_WIDTH 1 +#define D18F3x44_GenCrcErrByte0_MASK 0x10000 +#define D18F3x44_GenCrcErrByte1_OFFSET 17 +#define D18F3x44_GenCrcErrByte1_WIDTH 1 +#define D18F3x44_GenCrcErrByte1_MASK 0x20000 +#define D18F3x44_GenSubLinkSel_OFFSET 18 +#define D18F3x44_GenSubLinkSel_WIDTH 2 +#define D18F3x44_GenSubLinkSel_MASK 0xc0000 +#define D18F3x44_SyncFloodOnWDT_OFFSET 20 +#define D18F3x44_SyncFloodOnWDT_WIDTH 1 +#define D18F3x44_SyncFloodOnWDT_MASK 0x100000 +#define D18F3x44_SyncFloodOnWDT_VALUE 0x1 +#define D18F3x44_SyncFloodOnAnyUcErr_OFFSET 21 +#define D18F3x44_SyncFloodOnAnyUcErr_WIDTH 1 +#define D18F3x44_SyncFloodOnAnyUcErr_MASK 0x200000 +#define D18F3x44_SyncFloodOnAnyUcErr_VALUE 0x1 +#define D18F3x44_DramEccEn_OFFSET 22 +#define D18F3x44_DramEccEn_WIDTH 1 +#define D18F3x44_DramEccEn_MASK 0x400000 +#define D18F3x44_ChipKillEccCap_OFFSET 23 +#define D18F3x44_ChipKillEccCap_WIDTH 1 +#define D18F3x44_ChipKillEccCap_MASK 0x800000 +#define D18F3x44_IoRdDatErrEn_OFFSET 24 +#define D18F3x44_IoRdDatErrEn_WIDTH 1 +#define D18F3x44_IoRdDatErrEn_MASK 0x1000000 +#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET 25 +#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH 1 +#define D18F3x44_DisPciCfgCpuErrRsp_MASK 0x2000000 +#define D18F3x44_FlagMcaCorrErr_OFFSET 26 +#define D18F3x44_FlagMcaCorrErr_WIDTH 1 +#define D18F3x44_FlagMcaCorrErr_MASK 0x4000000 +#define D18F3x44_NbMcaToMstCpuEn_OFFSET 27 +#define D18F3x44_NbMcaToMstCpuEn_WIDTH 1 +#define D18F3x44_NbMcaToMstCpuEn_MASK 0x8000000 +#define D18F3x44_NbMcaToMstCpuEn_VALUE 0x1 +#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET 28 +#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisTgtAbortCpuErrRsp_MASK 0x10000000 +#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET 29 +#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisMstAbortCpuErrRsp_MASK 0x20000000 +#define D18F3x44_SyncFloodOnDramAdrParErr_OFFSET 30 +#define D18F3x44_SyncFloodOnDramAdrParErr_WIDTH 1 +#define D18F3x44_SyncFloodOnDramAdrParErr_MASK 0x40000000 +#define D18F3x44_SyncFloodOnDramAdrParErr_VALUE 0x1 +#define D18F3x44_NbMcaLogEn_OFFSET 31 +#define D18F3x44_NbMcaLogEn_WIDTH 1 +#define D18F3x44_NbMcaLogEn_MASK 0x80000000 + +/// D18F3x44 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 CpuRdDatErrEn:1 ; ///< + UINT32 SyncFloodOnDramUcEcc:1 ; ///< + UINT32 SyncPktGenDis:1 ; ///< + UINT32 SyncPktPropDis:1 ; ///< + UINT32 IoMstAbortDis:1 ; ///< + UINT32 CpuErrDis:1 ; ///< + UINT32 IoErrDis:1 ; ///< + UINT32 WDTDis:1 ; ///< + UINT32 WDTCntSel_2_0_:3 ; ///< + UINT32 WDTBaseSel:2 ; ///< + UINT32 GenLinkSel:2 ; ///< + UINT32 GenCrcErrByte0:1 ; ///< + UINT32 GenCrcErrByte1:1 ; ///< + UINT32 GenSubLinkSel:2 ; ///< + UINT32 SyncFloodOnWDT:1 ; ///< + UINT32 SyncFloodOnAnyUcErr:1 ; ///< + UINT32 DramEccEn:1 ; ///< + UINT32 ChipKillEccCap:1 ; ///< + UINT32 IoRdDatErrEn:1 ; ///< + UINT32 DisPciCfgCpuErrRsp:1 ; ///< + UINT32 FlagMcaCorrErr:1 ; ///< + UINT32 NbMcaToMstCpuEn:1 ; ///< + UINT32 DisTgtAbortCpuErrRsp:1 ; ///< + UINT32 DisMstAbortCpuErrRsp:1 ; ///< + UINT32 SyncFloodOnDramAdrParErr:1 ; ///< + UINT32 NbMcaLogEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x44_STRUCT; + +// **** D18F3x64 Register Definition **** +// Address +#define D18F3x64_ADDRESS 0x64 + +// Type +#define D18F3x64_TYPE TYPE_D18F3 +// Field Data +#define D18F3x64_HtcEn_OFFSET 0 +#define D18F3x64_HtcEn_WIDTH 1 +#define D18F3x64_HtcEn_MASK 0x1 +#define D18F3x64_HtcEn_VALUE 0x0 +#define D18F3x64_HtcAct_OFFSET 4 +#define D18F3x64_HtcAct_WIDTH 1 +#define D18F3x64_HtcAct_MASK 0x10 +#define D18F3x64_HtcActSts_OFFSET 5 +#define D18F3x64_HtcActSts_WIDTH 1 +#define D18F3x64_HtcActSts_MASK 0x20 +#define D18F3x64_PslApicHiEn_OFFSET 6 +#define D18F3x64_PslApicHiEn_WIDTH 1 +#define D18F3x64_PslApicHiEn_MASK 0x40 +#define D18F3x64_PslApicLoEn_OFFSET 7 +#define D18F3x64_PslApicLoEn_WIDTH 1 +#define D18F3x64_PslApicLoEn_MASK 0x80 +#define D18F3x64_HtcTmpLmt_OFFSET 16 +#define D18F3x64_HtcTmpLmt_WIDTH 7 +#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 +#define D18F3x64_HtcSlewSel_OFFSET 23 +#define D18F3x64_HtcSlewSel_WIDTH 1 +#define D18F3x64_HtcSlewSel_MASK 0x800000 +#define D18F3x64_HtcHystLmt_OFFSET 24 +#define D18F3x64_HtcHystLmt_WIDTH 4 +#define D18F3x64_HtcHystLmt_MASK 0xf000000 +#define D18F3x64_HtcPstateLimit_OFFSET 28 +#define D18F3x64_HtcPstateLimit_WIDTH 3 +#define D18F3x64_HtcPstateLimit_MASK 0x70000000 +#define D18F3x64_Reserved_31_31_OFFSET 31 +#define D18F3x64_Reserved_31_31_WIDTH 1 +#define D18F3x64_Reserved_31_31_MASK 0x80000000 + +/// D18F3x64 +typedef union { + struct { ///< + UINT32 HtcEn:1 ; ///< + UINT32 bit1:1; + UINT32 bit2:1; + UINT32 Reserved_3_3:1 ; ///< + UINT32 HtcAct:1 ; ///< + UINT32 HtcActSts:1 ; ///< + UINT32 PslApicHiEn:1 ; ///< + UINT32 PslApicLoEn:1 ; ///< + UINT32 bit10_8:3; + UINT32 Reserved_11_11:1 ; ///< + UINT32 bit14_12:3 ; + UINT32 Reserved_15_15:1 ; ///< + UINT32 HtcTmpLmt:7 ; ///< + UINT32 HtcSlewSel:1 ; ///< + UINT32 HtcHystLmt:4 ; ///< + UINT32 HtcPstateLimit:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x64_STRUCT; + + +// **** D18F3xA0 Register Definition **** +// Address +#define D18F3xA0_ADDRESS 0xa0 + +// Type +#define D18F3xA0_TYPE TYPE_D18F3 +// Field Data +#define D18F3xA0_PsiVid_6_0__OFFSET 0 +#define D18F3xA0_PsiVid_6_0__WIDTH 7 +#define D18F3xA0_PsiVid_6_0__MASK 0x7f +#define D18F3xA0_PsiVidEn_OFFSET 7 +#define D18F3xA0_PsiVidEn_WIDTH 1 +#define D18F3xA0_PsiVidEn_MASK 0x80 +#define D18F3xA0_PsiVid_7__OFFSET 8 +#define D18F3xA0_PsiVid_7__WIDTH 1 +#define D18F3xA0_PsiVid_7__MASK 0x100 +#define D18F3xA0_Reserved_9_9_OFFSET 9 +#define D18F3xA0_Reserved_9_9_WIDTH 1 +#define D18F3xA0_Reserved_9_9_MASK 0x200 +#define D18F3xA0_IdleExitEn_OFFSET 10 +#define D18F3xA0_IdleExitEn_WIDTH 1 +#define D18F3xA0_IdleExitEn_MASK 0x400 +#define D18F3xA0_PllLockTime_OFFSET 11 +#define D18F3xA0_PllLockTime_WIDTH 3 +#define D18F3xA0_PllLockTime_MASK 0x3800 +#define D18F3xA0_PllLockTime_VALUE 0x1 +#define D18F3xA0_Svi2HighFreqSel_OFFSET 14 +#define D18F3xA0_Svi2HighFreqSel_WIDTH 1 +#define D18F3xA0_Svi2HighFreqSel_MASK 0x4000 +#define D18F3xA0_Svi2HighFreqSel_VALUE 0x1 +#define D18F3xA0_ConfigId_OFFSET 16 +#define D18F3xA0_ConfigId_WIDTH 12 +#define D18F3xA0_ConfigId_MASK 0xfff0000 +#define D18F3xA0_Reserved_29_29_OFFSET 29 +#define D18F3xA0_Reserved_29_29_WIDTH 1 +#define D18F3xA0_Reserved_29_29_MASK 0x20000000 +#define D18F3xA0_CofVidProg_OFFSET 31 +#define D18F3xA0_CofVidProg_WIDTH 1 +#define D18F3xA0_CofVidProg_MASK 0x80000000 + +/// D18F3xA0 +typedef union { + struct { ///< + UINT32 PsiVid_6_0_:7 ; ///< + UINT32 PsiVidEn:1 ; ///< + UINT32 PsiVid_7_:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 IdleExitEn:1 ; ///< + UINT32 PllLockTime:3 ; ///< + UINT32 Svi2HighFreqSel:1 ; ///< + UINT32 :1 ; ///< + UINT32 ConfigId:12; ///< + UINT32 :1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 :1 ; ///< + UINT32 CofVidProg:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xA0_STRUCT; + + +// **** D18F3xA8 Register Definition **** +// Address +#define D18F3xA8_ADDRESS 0xA8 +// Type +#define D18F3xA8_TYPE TYPE_D18F3 + +// Field Data +#define D18F3xA8_Reserved_28_0_OFFSET 0 +#define D18F3xA8_Reserved_28_0_WIDTH 29 +#define D18F3xA8_Reserved_28_0_MASK 0x1FFFFFFF +#define D18F3xA8_PopDownPstate_OFFSET 29 +#define D18F3xA8_PopDownPstate_WIDTH 3 +#define D18F3xA8_PopDownPstate_MASK 0xE0000000 + +/// D18F3xA8 +typedef union { + struct { ///< + UINT32 Reserved_28_0:29; ///< + UINT32 PopDownPstate:3; ///< + + } Field; + + UINT32 Value; +} D18F3xA8_STRUCT; + +// **** D18F5x12C Register Definition **** +// Address +#define D18F5x12C_ADDRESS 0x12C +// Type +#define D18F5x12C_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x12C_CoreOffsetTrim_OFFSET 0 +#define D18F5x12C_CoreOffsetTrim_WIDTH 2 +#define D18F5x12C_CoreOffsetTrim_MASK 0x3 +#define D18F5x12C_CoreLoadLineTrim_OFFSET 2 +#define D18F5x12C_CoreLoadLineTrim_WIDTH 3 +#define D18F5x12C_CoreLoadLineTrim_MASK 0x1C +#define D18F5x12C_CorePsi1En_OFFSET 5 +#define D18F5x12C_CorePsi1En_WIDTH 1 +#define D18F5x12C_CorePsi1En_MASK 0x20 +#define D18F5x12C_RAZ_29_7_OFFSET 7 +#define D18F5x12C_RAZ_29_7_WIDTH 23 +#define D18F5x12C_RAZ_29_7_MASK 0x3FFFFF80 +#define D18F5x12C_WaitVidCompDis_OFFSET 30 +#define D18F5x12C_WaitVidCompDis_WIDTH 1 +#define D18F5x12C_WaitVidCompDis_MASK 0x40000000 +#define D18F5x12C_Svi2CmdBusy_OFFSET 31 +#define D18F5x12C_Svi2CmdBusy_WIDTH 1 +#define D18F5x12C_Svi2CmdBusy_MASK 0x80000000 + +/// D18F5x12C +typedef union { + struct { ///< + UINT32 CoreOffsetTrim:2; ///< + UINT32 CoreLoadLineTrim:3; ///< + UINT32 CorePsi1En:1; ///< + UINT32 :1; ///< + UINT32 RAZ_29_7:23; ///< + UINT32 WaitVidCompDis:1; ///< + UINT32 Svi2CmdBusy:1; ///< + + } Field; + + UINT32 Value; +} D18F5x12C_STRUCT; + +// **** D18F5x178 Register Definition **** +// Address +#define D18F5x178_ADDRESS 0x178 +// Type +#define D18F5x178_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x178_Reserved_1_0_OFFSET 0 +#define D18F5x178_Reserved_1_0_WIDTH 2 +#define D18F5x178_Reserved_1_0_MASK 0x3 +#define D18F5x178_CstateFusionDis_OFFSET 2 +#define D18F5x178_CstateFusionDis_WIDTH 1 +#define D18F5x178_CstateFusionDis_MASK 0x4 +#define D18F5x178_CstateThreeWayHsEn_OFFSET 3 +#define D18F5x178_CstateThreeWayHsEn_WIDTH 1 +#define D18F5x178_CstateThreeWayHsEn_MASK 0x8 +#define D18F5x178_Reserved_17_4_OFFSET 4 +#define D18F5x178_Reserved_17_4_WIDTH 14 +#define D18F5x178_Reserved_17_4_MASK 0x3FFF0 +#define D18F5x178_CstateFusionHsDis_OFFSET 18 +#define D18F5x178_CstateFusionHsDis_WIDTH 1 +#define D18F5x178_CstateFusionHsDis_MASK 0x40000 +#define D18F5x178_SwGfxDis_OFFSET 19 +#define D18F5x178_SwGfxDis_WIDTH 1 +#define D18F5x178_SwGfxDis_MASK 0x80000 +#define D18F5x178_Reserved_31_20_OFFSET 20 +#define D18F5x178_Reserved_31_20_WIDTH 12 +#define D18F5x178_Reserved_31_20_MASK 0xFFF00000 + +/// D18F5x178 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 CstateFusionDis:1; ///< + UINT32 CstateThreeWayHsEn:1; ///< + UINT32 Reserved_17_4:14; ///< + UINT32 CstateFusionHsDis:1; ///< + UINT32 SwGfxDis:1; ///< + UINT32 Reserved_31_20:12; ///< + + } Field; + + UINT32 Value; +} D18F5x178_STRUCT; + +// **** D18F5x188 Register Definition **** +// Address +#define D18F5x188_ADDRESS 0x188 +// Type +#define D18F5x188_TYPE TYPE_D18F5 + +// Field Data +#define D18F5x188_NbOffsetTrim_OFFSET 0 +#define D18F5x188_NbOffsetTrim_WIDTH 2 +#define D18F5x188_NbOffsetTrim_MASK 0x3 +#define D18F5x188_NbLoadLineTrim_OFFSET 2 +#define D18F5x188_NbLoadLineTrim_WIDTH 3 +#define D18F5x188_NbLoadLineTrim_MASK 0x1C +#define D18F5x188_NbPsi1_OFFSET 5 +#define D18F5x188_NbPsi1_WIDTH 1 +#define D18F5x188_NbPsi1_MASK 0x20 +#define D18F5x188_RAZ_31_7_OFFSET 7 +#define D18F5x188_RAZ_31_7_WIDTH 25 +#define D18F5x188_RAZ_31_7_MASK 0xFFFFFF80 + +/// D18F5x188 +typedef union { + struct { ///< + UINT32 NbOffsetTrim:2; ///< + UINT32 NbLoadLineTrim:3; ///< + UINT32 NbPsi1:1; ///< + UINT32 :1; ///< + UINT32 RAZ_31_7:25; ///< + + } Field; + + UINT32 Value; +} D18F5x188_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 +// Type +#define D0F0x04_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_Reserved_19_3_OFFSET 3 +#define D0F0x04_Reserved_19_3_WIDTH 17 +#define D0F0x04_Reserved_19_3_MASK 0xFFFF8 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_Reserved_31_21_OFFSET 21 +#define D0F0x04_Reserved_31_21_WIDTH 11 +#define D0F0x04_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1; ///< + UINT32 MemAccessEn:1; ///< + UINT32 BusMasterEn:1; ///< + UINT32 Reserved_19_3:17; ///< + UINT32 CapList:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0x04_STRUCT; + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 +// Type +#define D0F0x64_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xFFFFFFFF + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0x64_STRUCT; + +// **** DxF0x3C Register Definition **** +// Address +#define DxF0x3C_ADDRESS 0x3c + +// Type +#define DxF0x3C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x3C_IntLine_OFFSET 0 +#define DxF0x3C_IntLine_WIDTH 8 +#define DxF0x3C_IntLine_MASK 0xff +#define DxF0x3C_IntPin_OFFSET 8 +#define DxF0x3C_IntPin_WIDTH 3 +#define DxF0x3C_IntPin_MASK 0x700 +#define DxF0x3C_IntPinR_OFFSET 11 +#define DxF0x3C_IntPinR_WIDTH 5 +#define DxF0x3C_IntPinR_MASK 0xf800 +#define DxF0x3C_ParityResponseEn_OFFSET 16 +#define DxF0x3C_ParityResponseEn_WIDTH 1 +#define DxF0x3C_ParityResponseEn_MASK 0x10000 +#define DxF0x3C_SerrEn_OFFSET 17 +#define DxF0x3C_SerrEn_WIDTH 1 +#define DxF0x3C_SerrEn_MASK 0x20000 +#define DxF0x3C_IsaEn_OFFSET 18 +#define DxF0x3C_IsaEn_WIDTH 1 +#define DxF0x3C_IsaEn_MASK 0x40000 +#define DxF0x3C_VgaEn_OFFSET 19 +#define DxF0x3C_VgaEn_WIDTH 1 +#define DxF0x3C_VgaEn_MASK 0x80000 +#define DxF0x3C_Vga16En_OFFSET 20 +#define DxF0x3C_Vga16En_WIDTH 1 +#define DxF0x3C_Vga16En_MASK 0x100000 +#define DxF0x3C_MasterAbortMode_OFFSET 21 +#define DxF0x3C_MasterAbortMode_WIDTH 1 +#define DxF0x3C_MasterAbortMode_MASK 0x200000 +#define DxF0x3C_SecondaryBusReset_OFFSET 22 +#define DxF0x3C_SecondaryBusReset_WIDTH 1 +#define DxF0x3C_SecondaryBusReset_MASK 0x400000 +#define DxF0x3C_FastB2BCap_OFFSET 23 +#define DxF0x3C_FastB2BCap_WIDTH 1 +#define DxF0x3C_FastB2BCap_MASK 0x800000 +#define DxF0x3C_Reserved_31_24_OFFSET 24 +#define DxF0x3C_Reserved_31_24_WIDTH 8 +#define DxF0x3C_Reserved_31_24_MASK 0xff000000 + +/// DxF0x3C +typedef union { + struct { ///< + UINT32 IntLine:8 ; ///< + UINT32 IntPin:3 ; ///< + UINT32 IntPinR:5 ; ///< + UINT32 ParityResponseEn:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 IsaEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 MasterAbortMode:1 ; ///< + UINT32 SecondaryBusReset:1 ; ///< + UINT32 FastB2BCap:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x3C_STRUCT; + +// **** DxF0x58 Register Definition **** +// Address +#define DxF0x58_ADDRESS 0x58 + +// Type +#define DxF0x58_TYPE TYPE_D4F0 +// Field Data +#define DxF0x58_CapID_OFFSET 0 +#define DxF0x58_CapID_WIDTH 8 +#define DxF0x58_CapID_MASK 0xff +#define DxF0x58_NextPtr_OFFSET 8 +#define DxF0x58_NextPtr_WIDTH 8 +#define DxF0x58_NextPtr_MASK 0xff00 +#define DxF0x58_Version_OFFSET 16 +#define DxF0x58_Version_WIDTH 4 +#define DxF0x58_Version_MASK 0xf0000 +#define DxF0x58_DeviceType_OFFSET 20 +#define DxF0x58_DeviceType_WIDTH 4 +#define DxF0x58_DeviceType_MASK 0xf00000 +#define DxF0x58_SlotImplemented_OFFSET 24 +#define DxF0x58_SlotImplemented_WIDTH 1 +#define DxF0x58_SlotImplemented_MASK 0x1000000 +#define DxF0x58_IntMessageNum_OFFSET 25 +#define DxF0x58_IntMessageNum_WIDTH 5 +#define DxF0x58_IntMessageNum_MASK 0x3e000000 +#define DxF0x58_Reserved_31_30_OFFSET 30 +#define DxF0x58_Reserved_31_30_WIDTH 2 +#define DxF0x58_Reserved_31_30_MASK 0xc0000000 + +/// DxF0x58 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:4 ; ///< + UINT32 DeviceType:4 ; ///< + UINT32 SlotImplemented:1 ; ///< + UINT32 IntMessageNum:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x58_STRUCT; + +// **** DxFxx68 Register Definition **** +// Address +#define DxFxx68_ADDRESS 0x68 +// Type +#define DxFxx68_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx68_PmControl_OFFSET 0 +#define DxFxx68_PmControl_WIDTH 2 +#define DxFxx68_PmControl_MASK 0x3 +#define DxFxx68_Reserved_2_2_OFFSET 2 +#define DxFxx68_Reserved_2_2_WIDTH 1 +#define DxFxx68_Reserved_2_2_MASK 0x4 +#define DxFxx68_ReadCplBoundary_OFFSET 3 +#define DxFxx68_ReadCplBoundary_WIDTH 1 +#define DxFxx68_ReadCplBoundary_MASK 0x8 +#define DxFxx68_LinkDis_OFFSET 4 +#define DxFxx68_LinkDis_WIDTH 1 +#define DxFxx68_LinkDis_MASK 0x10 +#define DxFxx68_RetrainLink_OFFSET 5 +#define DxFxx68_RetrainLink_WIDTH 1 +#define DxFxx68_RetrainLink_MASK 0x20 +#define DxFxx68_CommonClockCfg_OFFSET 6 +#define DxFxx68_CommonClockCfg_WIDTH 1 +#define DxFxx68_CommonClockCfg_MASK 0x40 +#define DxFxx68_ExtendedSync_OFFSET 7 +#define DxFxx68_ExtendedSync_WIDTH 1 +#define DxFxx68_ExtendedSync_MASK 0x80 +#define DxFxx68_ClockPowerManagementEn_OFFSET 8 +#define DxFxx68_ClockPowerManagementEn_WIDTH 1 +#define DxFxx68_ClockPowerManagementEn_MASK 0x100 +#define DxFxx68_HWAutonomousWidthDisable_OFFSET 9 +#define DxFxx68_HWAutonomousWidthDisable_WIDTH 1 +#define DxFxx68_HWAutonomousWidthDisable_MASK 0x200 +#define DxFxx68_LinkBWManagementEn_OFFSET 10 +#define DxFxx68_LinkBWManagementEn_WIDTH 1 +#define DxFxx68_LinkBWManagementEn_MASK 0x400 +#define DxFxx68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxFxx68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxFxx68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxFxx68_Reserved_15_12_OFFSET 12 +#define DxFxx68_Reserved_15_12_WIDTH 4 +#define DxFxx68_Reserved_15_12_MASK 0xF000 +#define DxFxx68_LinkSpeed_OFFSET 16 +#define DxFxx68_LinkSpeed_WIDTH 4 +#define DxFxx68_LinkSpeed_MASK 0xF0000 +#define DxFxx68_NegotiatedLinkWidth_OFFSET 20 +#define DxFxx68_NegotiatedLinkWidth_WIDTH 6 +#define DxFxx68_NegotiatedLinkWidth_MASK 0x3F00000 +#define DxFxx68_Reserved_26_26_OFFSET 26 +#define DxFxx68_Reserved_26_26_WIDTH 1 +#define DxFxx68_Reserved_26_26_MASK 0x4000000 +#define DxFxx68_LinkTraining_OFFSET 27 +#define DxFxx68_LinkTraining_WIDTH 1 +#define DxFxx68_LinkTraining_MASK 0x8000000 +#define DxFxx68_SlotClockCfg_OFFSET 28 +#define DxFxx68_SlotClockCfg_WIDTH 1 +#define DxFxx68_SlotClockCfg_MASK 0x10000000 +#define DxFxx68_DlActive_OFFSET 29 +#define DxFxx68_DlActive_WIDTH 1 +#define DxFxx68_DlActive_MASK 0x20000000 +#define DxFxx68_LinkBWManagementStatus_OFFSET 30 +#define DxFxx68_LinkBWManagementStatus_WIDTH 1 +#define DxFxx68_LinkBWManagementStatus_MASK 0x40000000 +#define DxFxx68_LinkAutonomousBWStatus_OFFSET 31 +#define DxFxx68_LinkAutonomousBWStatus_WIDTH 1 +#define DxFxx68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxFxx68 +typedef union { + struct { ///< + UINT32 PmControl:2; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 ReadCplBoundary:1; ///< + UINT32 LinkDis:1; ///< + UINT32 RetrainLink:1; ///< + UINT32 CommonClockCfg:1; ///< + UINT32 ExtendedSync:1; ///< + UINT32 ClockPowerManagementEn:1; ///< + UINT32 HWAutonomousWidthDisable:1; ///< + UINT32 LinkBWManagementEn:1; ///< + UINT32 LinkAutonomousBWIntEn:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 LinkSpeed:4; ///< + UINT32 NegotiatedLinkWidth:6; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 LinkTraining:1; ///< + UINT32 SlotClockCfg:1; ///< + UINT32 DlActive:1; ///< + UINT32 LinkBWManagementStatus:1; ///< + UINT32 LinkAutonomousBWStatus:1; ///< + + } Field; + + UINT32 Value; +} DxFxx68_STRUCT; + +// **** D0F0x7C Register Definition **** +// Address +#define D0F0x7C_ADDRESS 0x7C +// Type +#define D0F0x7C_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x7C_ForceIntGfxDisable_OFFSET 0 +#define D0F0x7C_ForceIntGfxDisable_WIDTH 1 +#define D0F0x7C_ForceIntGfxDisable_MASK 0x1 +#define D0F0x7C_Reserved_31_1_OFFSET 1 +#define D0F0x7C_Reserved_31_1_WIDTH 31 +#define D0F0x7C_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0x7C +typedef union { + struct { ///< + UINT32 ForceIntGfxDisable:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0x7C_STRUCT; + +// **** D0F0x98 Register Definition **** +// Address +#define D0F0x98_ADDRESS 0x98 +// Type +#define D0F0x98_TYPE TYPE_D0F0 + +// Field Data +#define D0F0x98_OrbIndData_OFFSET 0 +#define D0F0x98_OrbIndData_WIDTH 32 +#define D0F0x98_OrbIndData_MASK 0xFFFFFFFF + +/// D0F0x98 +typedef union { + struct { ///< + UINT32 OrbIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0x98_STRUCT; + +// **** D0F0xBC Register Definition **** +// Address +#define D0F0xBC_ADDRESS 0xBC +// Type +#define D0F0xBC_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xBC_NbSmuIndData_OFFSET 0 +#define D0F0xBC_NbSmuIndData_WIDTH 32 +#define D0F0xBC_NbSmuIndData_MASK 0xFFFFFFFF + +/// D0F0xBC +typedef union { + struct { ///< + UINT32 NbSmuIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xBC_STRUCT; + +// **** D0F0xC8 Register Definition **** +// Address +#define D0F0xC8_ADDRESS 0xC8 +// Type +#define D0F0xC8_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xC8_NbDevIndAddr_OFFSET 0 +#define D0F0xC8_NbDevIndAddr_WIDTH 7 +#define D0F0xC8_NbDevIndAddr_MASK 0x7F +#define D0F0xC8_Reserved_15_7_OFFSET 7 +#define D0F0xC8_Reserved_15_7_WIDTH 9 +#define D0F0xC8_Reserved_15_7_MASK 0xFF80 +#define D0F0xC8_NbDevIndSel_OFFSET 16 +#define D0F0xC8_NbDevIndSel_WIDTH 8 +#define D0F0xC8_NbDevIndSel_MASK 0xFF0000 +#define D0F0xC8_Reserved_31_24_OFFSET 24 +#define D0F0xC8_Reserved_31_24_WIDTH 8 +#define D0F0xC8_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xC8 +typedef union { + struct { ///< + UINT32 NbDevIndAddr:7; ///< + UINT32 Reserved_15_7:9; ///< + UINT32 NbDevIndSel:8; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xC8_STRUCT; + +// **** D0F0xCC Register Definition **** +// Address +#define D0F0xCC_ADDRESS 0xCC +// Type +#define D0F0xCC_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xCC_NbDevIndData_OFFSET 0 +#define D0F0xCC_NbDevIndData_WIDTH 32 +#define D0F0xCC_NbDevIndData_MASK 0xFFFFFFFF + +/// D0F0xCC +typedef union { + struct { ///< + UINT32 NbDevIndData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xCC_STRUCT; + +// **** D0F0xE4 Register Definition **** +// Address +#define D0F0xE4_ADDRESS 0xE4 +// Type +#define D0F0xE4_TYPE TYPE_D0F0 + +// Field Data +#define D0F0xE4_PcieIndxData_OFFSET 0 +#define D0F0xE4_PcieIndxData_WIDTH 32 +#define D0F0xE4_PcieIndxData_MASK 0xFFFFFFFF + +/// D0F0xE4 +typedef union { + struct { ///< + UINT32 PcieIndxData:32; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_STRUCT; + +// **** DxFxxE4_x6A Register Definition **** +// Address +#define DxFxxE4_x6A_ADDRESS 0x6A +// Type +#define DxFxxE4_x6A_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_x6A_ErrReportingDis_OFFSET 0 +#define DxFxxE4_x6A_ErrReportingDis_WIDTH 1 +#define DxFxxE4_x6A_ErrReportingDis_MASK 0x1 + +// **** DxFxxE4_xA2 Register Definition **** +// Address +#define DxFxxE4_xA2_ADDRESS 0xA2 +// Type +#define DxFxxE4_xA2_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA2_LcLinkWidth_OFFSET 0 +#define DxFxxE4_xA2_LcLinkWidth_WIDTH 3 +#define DxFxxE4_xA2_LcLinkWidth_MASK 0x7 +#define DxFxxE4_xA2_Reserved_3_3_OFFSET 3 +#define DxFxxE4_xA2_Reserved_3_3_WIDTH 1 +#define DxFxxE4_xA2_Reserved_3_3_MASK 0x8 +#define DxFxxE4_xA2_LcLinkWidthRd_OFFSET 4 +#define DxFxxE4_xA2_LcLinkWidthRd_WIDTH 3 +#define DxFxxE4_xA2_LcLinkWidthRd_MASK 0x70 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 +#define DxFxxE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 +#define DxFxxE4_xA2_LcReconfigNow_OFFSET 8 +#define DxFxxE4_xA2_LcReconfigNow_WIDTH 1 +#define DxFxxE4_xA2_LcReconfigNow_MASK 0x100 +#define DxFxxE4_xA2_LcRenegotiationSupport_OFFSET 9 +#define DxFxxE4_xA2_LcRenegotiationSupport_WIDTH 1 +#define DxFxxE4_xA2_LcRenegotiationSupport_MASK 0x200 +#define DxFxxE4_xA2_LcRenegotiateEn_OFFSET 10 +#define DxFxxE4_xA2_LcRenegotiateEn_WIDTH 1 +#define DxFxxE4_xA2_LcRenegotiateEn_MASK 0x400 +#define DxFxxE4_xA2_LcShortReconfigEn_OFFSET 11 +#define DxFxxE4_xA2_LcShortReconfigEn_WIDTH 1 +#define DxFxxE4_xA2_LcShortReconfigEn_MASK 0x800 +#define DxFxxE4_xA2_LcUpconfigureSupport_OFFSET 12 +#define DxFxxE4_xA2_LcUpconfigureSupport_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigureSupport_MASK 0x1000 +#define DxFxxE4_xA2_LcUpconfigureDis_OFFSET 13 +#define DxFxxE4_xA2_LcUpconfigureDis_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigureDis_MASK 0x2000 +#define DxFxxE4_xA2_Reserved_19_14_OFFSET 14 +#define DxFxxE4_xA2_Reserved_19_14_WIDTH 6 +#define DxFxxE4_xA2_Reserved_19_14_MASK 0xFC000 +#define DxFxxE4_xA2_LcUpconfigCapable_OFFSET 20 +#define DxFxxE4_xA2_LcUpconfigCapable_WIDTH 1 +#define DxFxxE4_xA2_LcUpconfigCapable_MASK 0x100000 +#define DxFxxE4_xA2_LcDynLanesPwrState_OFFSET 21 +#define DxFxxE4_xA2_LcDynLanesPwrState_WIDTH 2 +#define DxFxxE4_xA2_LcDynLanesPwrState_MASK 0x600000 +#define DxFxxE4_xA2_Reserved_31_23_OFFSET 23 +#define DxFxxE4_xA2_Reserved_31_23_WIDTH 9 +#define DxFxxE4_xA2_Reserved_31_23_MASK 0xFF800000 + +/// DxFxxE4_xA2 +typedef union { + struct { ///< + UINT32 LcLinkWidth:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 LcLinkWidthRd:3; ///< + UINT32 LcReconfigArcMissingEscape:1; ///< + UINT32 LcReconfigNow:1; ///< + UINT32 LcRenegotiationSupport:1; ///< + UINT32 LcRenegotiateEn:1; ///< + UINT32 LcShortReconfigEn:1; ///< + UINT32 LcUpconfigureSupport:1; ///< + UINT32 LcUpconfigureDis:1; ///< + UINT32 Reserved_19_14:6; ///< + UINT32 LcUpconfigCapable:1; ///< + UINT32 LcDynLanesPwrState:2; ///< + UINT32 Reserved_31_23:9; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA2_STRUCT; + +// **** DxFxx128 Register Definition **** +// Address +#define DxFxx128_ADDRESS 0x128 +// Type +#define DxFxx128_TYPE TYPE_D2F1 + +// Field Data +#define DxFxx128_Reserved_15_0_OFFSET 0 +#define DxFxx128_Reserved_15_0_WIDTH 16 +#define DxFxx128_Reserved_15_0_MASK 0xFFFF +#define DxFxx128_PortArbTableStatus_OFFSET 16 +#define DxFxx128_PortArbTableStatus_WIDTH 1 +#define DxFxx128_PortArbTableStatus_MASK 0x10000 +#define DxFxx128_VcNegotiationPending_OFFSET 17 +#define DxFxx128_VcNegotiationPending_WIDTH 1 +#define DxFxx128_VcNegotiationPending_MASK 0x20000 +#define DxFxx128_Reserved_31_18_OFFSET 18 +#define DxFxx128_Reserved_31_18_WIDTH 14 +#define DxFxx128_Reserved_31_18_MASK 0xFFFC0000 + +/// DxFxx128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1; ///< + UINT32 VcNegotiationPending:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} DxFxx128_STRUCT; + +// **** D0F0x64_x0D Register Definition **** +// Address +#define D0F0x64_x0D_ADDRESS 0xD +// Type +#define D0F0x64_x0D_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET 0 +#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH 1 +#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK 0x1 +#define D0F0x64_x0D_Reserved_30_1_OFFSET 1 +#define D0F0x64_x0D_Reserved_30_1_WIDTH 30 +#define D0F0x64_x0D_Reserved_30_1_MASK 0x7FFFFFFE +#define D0F0x64_x0D_IommuDis_OFFSET 31 +#define D0F0x64_x0D_IommuDis_WIDTH 1 +#define D0F0x64_x0D_IommuDis_MASK 0x80000000 + +/// D0F0x64_x0D +typedef union { + struct { ///< + UINT32 PciDev0Fn2RegEn:1; ///< + UINT32 Reserved_30_1:30; ///< + UINT32 IommuDis:1; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x0D_STRUCT; + +// **** D0F0x64_x16 Register Definition **** +// Address +#define D0F0x64_x16_ADDRESS 0x16 + +// Type +#define D0F0x64_x16_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x16_AerUrMsgEn_OFFSET 0 +#define D0F0x64_x16_AerUrMsgEn_WIDTH 1 +#define D0F0x64_x16_AerUrMsgEn_MASK 0x1 +#define D0F0x64_x16_Reserved_31_1_OFFSET 1 +#define D0F0x64_x16_Reserved_31_1_WIDTH 31 +#define D0F0x64_x16_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x64_x16 +typedef union { + struct { ///< + UINT32 AerUrMsgEn:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x16_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1D +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x1D_Reserved_0_0_OFFSET 0 +#define D0F0x64_x1D_Reserved_0_0_WIDTH 1 +#define D0F0x64_x1D_Reserved_0_0_MASK 0x1 +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xFFFFFFF0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 VgaEn:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Vga16En:1; ///< + UINT32 Reserved_31_4:28; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x1D_STRUCT; + +// **** D0F0x64_x22 Register Definition **** +// Address +#define D0F0x64_x22_ADDRESS 0x22 +// Type +#define D0F0x64_x22_TYPE TYPE_D0F0x64 + + +// **** D0F0x64_x23 Register Definition **** +// Address +#define D0F0x64_x23_ADDRESS 0x23 +// Type +#define D0F0x64_x23_TYPE TYPE_D0F0x64 + + +// **** D0F0x64_x30 Register Definition **** +// Address +#define D0F0x64_x30_ADDRESS 0x30 +// Type +#define D0F0x64_x30_TYPE TYPE_D0F0x64 + +// Field Data +#define D0F0x64_x30_DevFnMap_OFFSET 0 +#define D0F0x64_x30_DevFnMap_WIDTH 8 +#define D0F0x64_x30_DevFnMap_MASK 0xFF +#define D0F0x64_x30_Reserved_31_8_OFFSET 8 +#define D0F0x64_x30_Reserved_31_8_WIDTH 24 +#define D0F0x64_x30_Reserved_31_8_MASK 0xFFFFFF00 + +/// D0F0x64_x30 +typedef union { + struct { ///< + UINT32 DevFnMap:8; ///< + UINT32 Reserved_31_8:24; ///< + + } Field; + + UINT32 Value; +} D0F0x64_x30_STRUCT; + +// **** D0F0x64_x46 Register Definition **** +// Address +#define D0F0x64_x46_ADDRESS 0x46 +// Type +#define D0F0x64_x46_TYPE TYPE_D0F0x64 + + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + +// **** D0F0x98_x07 Register Definition **** +// Address +#define D0F0x98_x07_ADDRESS 0x7 +// Type +#define D0F0x98_x07_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x07_IocBwOptEn_OFFSET 0 +#define D0F0x98_x07_IocBwOptEn_WIDTH 1 +#define D0F0x98_x07_IocBwOptEn_MASK 0x1 +#define D0F0x98_x07_IocWrROMapDis_OFFSET 1 +#define D0F0x98_x07_IocWrROMapDis_WIDTH 1 +#define D0F0x98_x07_IocWrROMapDis_MASK 0x2 +#define D0F0x98_x07_IocRdROMapDis_OFFSET 2 +#define D0F0x98_x07_IocRdROMapDis_WIDTH 1 +#define D0F0x98_x07_IocRdROMapDis_MASK 0x4 +#define D0F0x98_x07_Reserved_3_3_OFFSET 3 +#define D0F0x98_x07_Reserved_3_3_WIDTH 1 +#define D0F0x98_x07_Reserved_3_3_MASK 0x8 +#define D0F0x98_x07_IommuBwOptEn_OFFSET 4 +#define D0F0x98_x07_IommuBwOptEn_WIDTH 1 +#define D0F0x98_x07_IommuBwOptEn_MASK 0x10 +#define D0F0x98_x07_Reserved_5_5_OFFSET 5 +#define D0F0x98_x07_Reserved_5_5_WIDTH 1 +#define D0F0x98_x07_Reserved_5_5_MASK 0x20 +#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET 6 +#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH 1 +#define D0F0x98_x07_DmaReqRespPassPWMode_MASK 0x40 +#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET 7 +#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH 1 +#define D0F0x98_x07_IommuIsocPassPWMode_MASK 0x80 +#define D0F0x98_x07_Reserved_14_8_OFFSET 8 +#define D0F0x98_x07_Reserved_14_8_WIDTH 7 +#define D0F0x98_x07_Reserved_14_8_MASK 0x7F00 +#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 +#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 +#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 +#define D0F0x98_x07_SyncFloodOnParityErr_OFFSET 16 +#define D0F0x98_x07_SyncFloodOnParityErr_WIDTH 1 +#define D0F0x98_x07_SyncFloodOnParityErr_MASK 0x10000 +#define D0F0x98_x07_Reserved_30_17_OFFSET 17 +#define D0F0x98_x07_Reserved_30_17_WIDTH 14 +#define D0F0x98_x07_Reserved_30_17_MASK 0x7FFE0000 +#define D0F0x98_x07_SMUCsrIsocEn_OFFSET 31 +#define D0F0x98_x07_SMUCsrIsocEn_WIDTH 1 +#define D0F0x98_x07_SMUCsrIsocEn_MASK 0x80000000 + +/// D0F0x98_x07 +typedef union { + struct { ///< + UINT32 IocBwOptEn:1; ///< + UINT32 IocWrROMapDis:1; ///< + UINT32 IocRdROMapDis:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 IommuBwOptEn:1; ///< + UINT32 Reserved_5_5:1; ///< + UINT32 DmaReqRespPassPWMode:1; ///< + UINT32 IommuIsocPassPWMode:1; ///< + UINT32 Reserved_14_8:7; ///< + UINT32 DropZeroMaskWrEn:1; ///< + UINT32 SyncFloodOnParityErr:1; ///< + UINT32 Reserved_30_17:14; ///< + UINT32 SMUCsrIsocEn:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x07_STRUCT; + +// **** D0F0x98_x08 Register Definition **** +// Address +#define D0F0x98_x08_ADDRESS 0x8 +// Type +#define D0F0x98_x08_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x08_NpWrrLenA_OFFSET 0 +#define D0F0x98_x08_NpWrrLenA_WIDTH 8 +#define D0F0x98_x08_NpWrrLenA_MASK 0xFF +#define D0F0x98_x08_NpWrrLenB_OFFSET 8 +#define D0F0x98_x08_NpWrrLenB_WIDTH 8 +#define D0F0x98_x08_NpWrrLenB_MASK 0xFF00 +#define D0F0x98_x08_NpWrrLenC_OFFSET 16 +#define D0F0x98_x08_NpWrrLenC_WIDTH 8 +#define D0F0x98_x08_NpWrrLenC_MASK 0xFF0000 +#define D0F0x98_x08_Reserved_31_24_OFFSET 24 +#define D0F0x98_x08_Reserved_31_24_WIDTH 8 +#define D0F0x98_x08_Reserved_31_24_MASK 0xFF000000 + +/// D0F0x98_x08 +typedef union { + struct { ///< + UINT32 NpWrrLenA:8; ///< + UINT32 NpWrrLenB:8; ///< + UINT32 NpWrrLenC:8; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x08_STRUCT; + +// **** D0F0x98_x0C Register Definition **** +// Address +#define D0F0x98_x0C_ADDRESS 0xC +// Type +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 +#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenA_MASK 0xFF +#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 +#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenB_MASK 0xFF00 +#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 +#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 +#define D0F0x98_x0C_Reserved_29_16_MASK 0x3FFF0000 +#define D0F0x98_x0C_Reserved_31_31_OFFSET 31 +#define D0F0x98_x0C_Reserved_31_31_WIDTH 1 +#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x0C +typedef union { + struct { ///< + UINT32 GcmWrrLenA:8; ///< + UINT32 GcmWrrLenB:8; ///< + UINT32 Reserved_29_16:14; ///< + UINT32 Reserved_30_30:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x0C_STRUCT; + +// **** D0F0x98_x1E Register Definition **** +// Address +#define D0F0x98_x1E_ADDRESS 0x1E +// Type +#define D0F0x98_x1E_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 +#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 +#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 +#define D0F0x98_x1E_HiPriEn_OFFSET 1 +#define D0F0x98_x1E_HiPriEn_WIDTH 1 +#define D0F0x98_x1E_HiPriEn_MASK 0x2 +#define D0F0x98_x1E_Reserved_23_2_OFFSET 2 +#define D0F0x98_x1E_Reserved_23_2_WIDTH 22 +#define D0F0x98_x1E_Reserved_23_2_MASK 0xFFFFFC +#define D0F0x98_x1E_RxErrStatusDelay_OFFSET 24 +#define D0F0x98_x1E_RxErrStatusDelay_WIDTH 8 +#define D0F0x98_x1E_RxErrStatusDelay_MASK 0xFF000000 + +/// D0F0x98_x1E +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 HiPriEn:1; ///< + UINT32 Reserved_23_2:22; ///< + UINT32 RxErrStatusDelay:8; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x1E_STRUCT; + +// **** D0F0x98_x28 Register Definition **** +// Address +#define D0F0x98_x28_ADDRESS 0x28 +// Type +#define D0F0x98_x28_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x28_Reserved_0_0_OFFSET 0 +#define D0F0x98_x28_Reserved_0_0_WIDTH 1 +#define D0F0x98_x28_Reserved_0_0_MASK 0x1 +#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 +#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 +#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 +#define D0F0x98_x28_Reserved_31_2_OFFSET 2 +#define D0F0x98_x28_Reserved_31_2_WIDTH 30 +#define D0F0x98_x28_Reserved_31_2_MASK 0xFFFFFFFC + +/// D0F0x98_x28 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 ForceCoherentIntr:1; ///< + UINT32 Reserved_31_2:30; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x28_STRUCT; + +// **** D0F0x98_x2C Register Definition **** +// Address +#define D0F0x98_x2C_ADDRESS 0x2C +// Type +#define D0F0x98_x2C_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 +#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 +#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 +#define D0F0x98_x2C_DynWakeEn_OFFSET 1 +#define D0F0x98_x2C_DynWakeEn_WIDTH 1 +#define D0F0x98_x2C_DynWakeEn_MASK 0x2 +#define D0F0x98_x2C_CgttLclkOverride_OFFSET 2 +#define D0F0x98_x2C_CgttLclkOverride_WIDTH 1 +#define D0F0x98_x2C_CgttLclkOverride_MASK 0x4 +#define D0F0x98_x2C_Reserved_8_3_OFFSET 3 +#define D0F0x98_x2C_Reserved_8_3_WIDTH 6 +#define D0F0x98_x2C_Reserved_8_3_MASK 0x1F8 +#define D0F0x98_x2C_SBDmaActiveMask_OFFSET 9 +#define D0F0x98_x2C_SBDmaActiveMask_WIDTH 1 +#define D0F0x98_x2C_SBDmaActiveMask_MASK 0x200 +#define D0F0x98_x2C_Reserved_15_10_OFFSET 10 +#define D0F0x98_x2C_Reserved_15_10_WIDTH 6 +#define D0F0x98_x2C_Reserved_15_10_MASK 0xFC00 +#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 +#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 +#define D0F0x98_x2C_WakeHysteresis_MASK 0xFFFF0000 + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 DynWakeEn:1; ///< + UINT32 CgttLclkOverride:1; ///< + UINT32 Reserved_8_3:6; ///< + UINT32 SBDmaActiveMask:1; ///< + UINT32 Reserved_15_10:6; ///< + UINT32 WakeHysteresis:16; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x2C_STRUCT; + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3A +// Type +#define D0F0x98_x3A_TYPE TYPE_D0F0x98 + +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x49_Reserved_23_0_OFFSET 0 +#define D0F0x98_x49_Reserved_23_0_WIDTH 24 +#define D0F0x98_x49_Reserved_23_0_MASK 0xFFFFFF +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1; ///< + UINT32 SoftOverrideClk5:1; ///< + UINT32 SoftOverrideClk4:1; ///< + UINT32 SoftOverrideClk3:1; ///< + UINT32 SoftOverrideClk2:1; ///< + UINT32 SoftOverrideClk1:1; ///< + UINT32 SoftOverrideClk0:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4A +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 + +// Field Data +#define D0F0x98_x4A_Reserved_23_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_23_0_WIDTH 24 +#define D0F0x98_x4A_Reserved_23_0_MASK 0xFFFFFF +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1; ///< + UINT32 SoftOverrideClk5:1; ///< + UINT32 SoftOverrideClk4:1; ///< + UINT32 SoftOverrideClk3:1; ///< + UINT32 SoftOverrideClk2:1; ///< + UINT32 SoftOverrideClk1:1; ///< + UINT32 SoftOverrideClk0:1; ///< + UINT32 Reserved_31_31:1; ///< + + } Field; + + UINT32 Value; +} D0F0x98_x4A_STRUCT; + + + + + + + + + + + +/// D0F0xBC_x3FA04 +typedef union { + struct { ///< + UINT32 Bitfield_15_0:16; ///< + UINT32 Bitfield_31_16:16; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4753_STRUCT; + +// **** D0F0xE4_PHY_0004 Register Definition **** +// Address +#define D0F0xE4_PHY_0004_ADDRESS 0x0004 +// Type +#define D0F0xE4_PHY_0004_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_0004_Reserved_15_0_OFFSET 0 +#define D0F0xE4_PHY_0004_Reserved_15_0_WIDTH 16 +#define D0F0xE4_PHY_0004_Reserved_15_0_MASK 0xFFFF +#define D0F0xE4_PHY_0004_CfgIdleDetTh_OFFSET 16 +#define D0F0xE4_PHY_0004_CfgIdleDetTh_WIDTH 2 +#define D0F0xE4_PHY_0004_CfgIdleDetTh_MASK 0x30000 +#define D0F0xE4_PHY_0004_Reserved_31_18_OFFSET 18 +#define D0F0xE4_PHY_0004_Reserved_31_18_WIDTH 14 +#define D0F0xE4_PHY_0004_Reserved_31_18_MASK 0xFFFC0000 + +/// D0F0xE4_PHY_0004 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 CfgIdleDetTh:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_0004_STRUCT; + +// **** D0F0xE4_PHY_4440 Register Definition **** +// Address +#define D0F0xE4_PHY_4440_ADDRESS 0x4440 +// Type +#define D0F0xE4_PHY_4440_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_4440_Reserved_12_0_OFFSET 0 +#define D0F0xE4_PHY_4440_Reserved_12_0_WIDTH 13 +#define D0F0xE4_PHY_4440_Reserved_12_0_MASK 0x1FFF +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_OFFSET 13 +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_WIDTH 2 +#define D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK 0x6000 +#define D0F0xE4_PHY_4440_Reserved_31_15_OFFSET 15 +#define D0F0xE4_PHY_4440_Reserved_31_15_WIDTH 17 +#define D0F0xE4_PHY_4440_Reserved_31_15_MASK 0xFFFF1000 + +/// D0F0xE4_PHY_4440 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 PllDbgRoIPFDResetCntrl:2 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_4440_STRUCT; + +// **** D0F0xE4_PHY_4450 Register Definition **** +// Address +#define D0F0xE4_PHY_4450_ADDRESS 0x4450 +// Type +#define D0F0xE4_PHY_4450_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_OFFSET 0 +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_WIDTH 8 +#define D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_MASK 0xFF +#define D0F0xE4_PHY_4450_Reserved_29_8_OFFSET 8 +#define D0F0xE4_PHY_4450_Reserved_29_8_WIDTH 22 +#define D0F0xE4_PHY_4450_Reserved_29_8_MASK 0x3FFFFF00 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_OFFSET 30 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_WIDTH 1 +#define D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_MASK 0x40000000 +#define D0F0xE4_PHY_4450_Reserved_31_31_OFFSET 31 +#define D0F0xE4_PHY_4450_Reserved_31_31_WIDTH 1 +#define D0F0xE4_PHY_4450_Reserved_31_31_MASK 0x80000000 + +/// D0F0xE4_PHY_4450 +typedef union { + struct { ///< + UINT32 PllCfgROBWCntrlOvrdVal0:8 ; ///< + UINT32 Reserved_29_8:22; ///< + UINT32 PllCfgROVTOIBiasCntrlOvrdVal0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; + UINT32 Value; +} D0F0xE4_PHY_4450_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_0800_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24; + + } Field; + + UINT32 Value; +} GnbRegistersKB4915_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4940_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4965_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB4990_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 bit_31_24:8; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB5015_STRUCT; + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xFC00 +#define D0F0xE4_WRAP_8011_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8011_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7E0000 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Bitfield_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_WRAP_8011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6; ///< + UINT32 TxclkPermGateEven:1; ///< + UINT32 TxclkDynGateEnable:1; ///< + UINT32 TxclkPermStop:1; ///< + UINT32 TxclkRegsGateEnable:1; ///< + UINT32 TxclkRegsGateLatency:6; ///< + UINT32 Reserved_16_16:1; ///< + UINT32 TxclkPermGateLatency:6; ///< + UINT32 Bitfield_23_23:1; ///< + UINT32 TxclkLcntGateEnable:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3F +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3F00 +#define D0F0xE4_WRAP_8012_Reserved_31_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_31_14_WIDTH 18 +#define D0F0xE4_WRAP_8012_Reserved_31_14_MASK 0xFFFFC000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6; ///< + UINT32 Reserved_6_6:1; ///< + UINT32 Pif1xIdleGateEnable:1; ///< + UINT32 Pif1xIdleResumeLatency:6; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8012_STRUCT; + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 +// Type +#define D0F0xE4_WRAP_8013_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_OFFSET 1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllB_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_OFFSET 5 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideB_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_OFFSET 10 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifBOverride_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_OFFSET 13 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_WIDTH 2 +#define D0F0xE4_WRAP_8013_PhyRxIsoDis_MASK 0x6000 +#define D0F0xE4_WRAP_8013_Reserved_31_15_OFFSET 15 +#define D0F0xE4_WRAP_8013_Reserved_31_15_WIDTH 17 +#define D0F0xE4_WRAP_8013_Reserved_31_15_MASK 0xFFFF8000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1; ///< + UINT32 MasterPciePllB:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 ClkDividerResetOverrideA:1; ///< + UINT32 ClkDividerResetOverrideB:1; ///< + UINT32 Reserved_6_6:1; ///< + UINT32 Reserved_7_7:1; ///< + UINT32 TxclkSelCoreOverride:1; ///< + UINT32 TxclkSelPifAOverride:1; ///< + UINT32 TxclkSelPifBOverride:1; ///< + UINT32 Reserved_11_11:1; ///< + UINT32 Reserved_12_12:1; ///< + UINT32 PhyRxIsoDis:2; ///< + UINT32 Reserved_31_15:17; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 +// Type +#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_11_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_WIDTH 6 +#define D0F0xE4_WRAP_8014_Reserved_11_6_MASK 0xFC0 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_Reserved_19_16_OFFSET 16 +#define D0F0xE4_WRAP_8014_Reserved_19_16_WIDTH 4 +#define D0F0xE4_WRAP_8014_Reserved_19_16_MASK 0xF0000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3 +#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xE00000 +#define D0F0xE4_WRAP_8014_Reserved_24_24_OFFSET 24 +#define D0F0xE4_WRAP_8014_Reserved_24_24_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_24_24_MASK 0x1000000 +#define D0F0xE4_WRAP_8014_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8014_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8014_Reserved_26_26_OFFSET 26 +#define D0F0xE4_WRAP_8014_Reserved_26_26_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_26_26_MASK 0x4000000 +#define D0F0xE4_WRAP_8014_Reserved_27_27_OFFSET 27 +#define D0F0xE4_WRAP_8014_Reserved_27_27_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28 +#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4 +#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xF0000000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1; ///< + UINT32 TxclkPrbsGateEnable:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 Reserved_4_4:1; ///< + UINT32 Reserved_5_5:1; ///< + UINT32 Reserved_11_6:6; ///< + UINT32 PcieGatePifA1xEnable:1; ///< + UINT32 PcieGatePifB1xEnable:1; ///< + UINT32 Reserved_14_14:1; ///< + UINT32 Reserved_15_15:1; ///< + UINT32 Reserved_19_16:4; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1; ///< + UINT32 Reserved_23_21:3; ///< + UINT32 Reserved_24_24:1; ///< + UINT32 Reserved_25_25:1; ///< + UINT32 Reserved_26_26:1; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 SpareRegRw:4; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8015 Register Definition **** +// Address +#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 +// Type +#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8015_Bitfield_0_0_OFFSET 0 +#define D0F0xE4_WRAP_8015_Bitfield_0_0_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_0_0_MASK 0x1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8015_Reserved_7_2_OFFSET 2 +#define D0F0xE4_WRAP_8015_Reserved_7_2_WIDTH 6 +#define D0F0xE4_WRAP_8015_Reserved_7_2_MASK 0xFC +#define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8015_Bitfield_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8015_Reserved_13_12_OFFSET 12 +#define D0F0xE4_WRAP_8015_Reserved_13_12_WIDTH 2 +#define D0F0xE4_WRAP_8015_Reserved_13_12_MASK 0x3000 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8015_Bitfield_15_14_MASK 0xC000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3F0000 +#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8015_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8015_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8015_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xE4_WRAP_8015 +typedef union { + struct { ///< + UINT32 Bitfield_0_0:1; ///< + UINT32 Reserved_1_1:1; ///< + UINT32 Reserved_7_2:6; ///< + UINT32 Reserved_8_8:1; ///< + UINT32 Bitfield_9_9:1; ///< + UINT32 Bitfield_10_10:1; ///< + UINT32 Bitfield_11_11:1; ///< + UINT32 Reserved_13_12:2; ///< + UINT32 Bitfield_15_14:2; ///< + UINT32 RefclkRegsGateLatency:6; ///< + UINT32 Reserved_22_22:1; ///< + UINT32 RefclkRegsGateEnable:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8015_STRUCT; + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3F +#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH 10 +#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK 0xFFC0 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3F0000 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xFF000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 LclkDynGateLatency:6; ///< + UINT32 LclkGateFree:1; ///< + UINT32 LclkDynGateEnable:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8016_STRUCT; + +// **** D0F0xE4_WRAP_8029 Register Definition **** +// Address +#define D0F0xE4_WRAP_8029_ADDRESS 0x8029 +// Type +#define D0F0xE4_WRAP_8029_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_WRAP_8029_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8029_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8029_LaneEnable_MASK 0xFFFF +#define D0F0xE4_WRAP_8029_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8029_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_WRAP_8029 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_WRAP_8029_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_X2Lane98_OFFSET 4 +#define D0F0xE4_PIF_0011_X2Lane98_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane98_MASK 0x10 +#define D0F0xE4_PIF_0011_X2Lane1110_OFFSET 5 +#define D0F0xE4_PIF_0011_X2Lane1110_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1110_MASK 0x20 +#define D0F0xE4_PIF_0011_X2Lane1312_OFFSET 6 +#define D0F0xE4_PIF_0011_X2Lane1312_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1312_MASK 0x40 +#define D0F0xE4_PIF_0011_X2Lane1514_OFFSET 7 +#define D0F0xE4_PIF_0011_X2Lane1514_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane1514_MASK 0x80 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_X4Lane118_OFFSET 10 +#define D0F0xE4_PIF_0011_X4Lane118_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane118_MASK 0x400 +#define D0F0xE4_PIF_0011_X4Lane1512_OFFSET 11 +#define D0F0xE4_PIF_0011_X4Lane1512_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane1512_MASK 0x800 +#define D0F0xE4_PIF_0011_Reserved_15_12_OFFSET 12 +#define D0F0xE4_PIF_0011_Reserved_15_12_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_15_12_MASK 0xF000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_X8Lane158_OFFSET 17 +#define D0F0xE4_PIF_0011_X8Lane158_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane158_MASK 0x20000 +#define D0F0xE4_PIF_0011_Reserved_19_18_OFFSET 18 +#define D0F0xE4_PIF_0011_Reserved_19_18_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_19_18_MASK 0xC0000 +#define D0F0xE4_PIF_0011_X16Lane150_OFFSET 20 +#define D0F0xE4_PIF_0011_X16Lane150_WIDTH 1 +#define D0F0xE4_PIF_0011_X16Lane150_MASK 0x100000 +#define D0F0xE4_PIF_0011_Reserved_24_21_OFFSET 21 +#define D0F0xE4_PIF_0011_Reserved_24_21_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_24_21_MASK 0x1E00000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xFC000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1; ///< + UINT32 X2Lane32:1; ///< + UINT32 X2Lane54:1; ///< + UINT32 X2Lane76:1; ///< + UINT32 X2Lane98:1; ///< + UINT32 X2Lane1110:1; ///< + UINT32 X2Lane1312:1; ///< + UINT32 X2Lane1514:1; ///< + UINT32 X4Lane30:1; ///< + UINT32 X4Lane74:1; ///< + UINT32 X4Lane118:1; ///< + UINT32 X4Lane1512:1; ///< + UINT32 Reserved_15_12:4; ///< + UINT32 X8Lane70:1; ///< + UINT32 X8Lane158:1; ///< + UINT32 Reserved_19_18:2; ///< + UINT32 X16Lane150:1; ///< + UINT32 Reserved_24_21:4; ///< + UINT32 MultiPif:1; ///< + UINT32 Reserved_31_26:6; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1C00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xE000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xFE0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xE0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3; ///< + UINT32 ForceRxEnInL0s:1; ///< + UINT32 RxPowerStateInRxs2:3; ///< + UINT32 PllPowerStateInTxs2:3; ///< + UINT32 PllPowerStateInOff:3; ///< + UINT32 Reserved_15_13:3; ///< + UINT32 Tx2p5clkClockGatingEn:1; ///< + UINT32 Reserved_23_17:7; ///< + UINT32 PllRampUpTime:3; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 PllPwrOverrideEn:1; ///< + UINT32 PllPwrOverrideVal:3; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_CORE_0002 Register Definition **** +// Address +#define D0F0xE4_CORE_0002_ADDRESS 0x0002 +// Type +#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0002_HwDebug_0_OFFSET 0 +#define D0F0xE4_CORE_0002_HwDebug_0_WIDTH 1 +#define D0F0xE4_CORE_0002_HwDebug_0_MASK 0x1 +#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 +#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 +#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xFFFFFFFE + +/// D0F0xE4_CORE_0002 +typedef union { + struct { ///< + UINT32 HwDebug_0:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0002_STRUCT; + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1FE +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK 0x1C00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xFFFFE000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1; ///< + UINT32 Reserved_8_1:8; ///< + UINT32 UmiNpMemWrite:1; ///< + UINT32 RxUmiAdjPayloadSize:3; ///< + UINT32 Reserved_31_13:19; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0010_STRUCT; + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 +// Type +#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xF +#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4 +#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28 +#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xFFFFFFF0 + +/// D0F0xE4_CORE_0011 +typedef union { + struct { ///< + UINT32 DynClkLatency:4; ///< + UINT32 Reserved_31_4:28; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0011_STRUCT; + +// **** D0F0xE4_CORE_001C Register Definition **** +// Address +#define D0F0xE4_CORE_001C_ADDRESS 0x1C +// Type +#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3E +#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 +#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7C0 +#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 +#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 +#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xFFFFF800 + +/// D0F0xE4_CORE_001C +typedef union { + struct { ///< + UINT32 TxArbRoundRobinEn:1; ///< + UINT32 TxArbSlvLimit:5; ///< + UINT32 TxArbMstLimit:5; ///< + UINT32 Reserved_31_11:21; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_001C_STRUCT; + +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x0020 +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH 8 +#define D0F0xE4_CORE_0020_Reserved_7_0_MASK 0xFF +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 +#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 +#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 +#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xFFFFFC00 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8; ///< + UINT32 CiSlvOrderingDis:1; ///< + UINT32 CiRcOrderingDis:1; ///< + UINT32 Reserved_31_10:22; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0020_STRUCT; + +// **** D0F0xE4_CORE_0040 Register Definition **** +// Address +#define D0F0xE4_CORE_0040_ADDRESS 0x40 +// Type +#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 +#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 +#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3FFF +#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 +#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 +#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xC000 +#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xFFFF0000 + +/// D0F0xE4_CORE_0040 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 PElecIdleMode:2; ///< + UINT32 Reserved_31_16:16; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_0040_STRUCT; + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xB0 +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 +#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 +#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xFFFFFFC0 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 StrapF0MsiEn:1; ///< + UINT32 Reserved_4_3:2; ///< + UINT32 StrapF0AerEn:1; ///< + UINT32 Reserved_31_6:26; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_00B0_STRUCT; + +// **** D0F0xE4_CORE_00C1 Register Definition **** +// Address +#define D0F0xE4_CORE_00C1_ADDRESS 0xC1 +// Type +#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 + +// Field Data +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 +#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xFFFFFFFC + +/// D0F0xE4_CORE_00C1 +typedef union { + struct { ///< + UINT32 StrapLinkBwNotificationCapEn:1; ///< + UINT32 StrapGen2Compliance:1; ///< + UINT32 Reserved_31_2:30; ///< + + } Field; + + UINT32 Value; +} D0F0xE4_CORE_00C1_STRUCT; + +// **** DxFxxE4_x70 Register Definition **** +// Address +#define DxFxxE4_x70_ADDRESS 0x70 +// Type +#define DxFxxE4_x70_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_x70_Reserved_15_0_OFFSET 0 +#define DxFxxE4_x70_Reserved_15_0_WIDTH 16 +#define DxFxxE4_x70_Reserved_15_0_MASK 0xFFFF +#define DxFxxE4_x70_RxRcbCplTimeout_OFFSET 16 +#define DxFxxE4_x70_RxRcbCplTimeout_WIDTH 3 +#define DxFxxE4_x70_RxRcbCplTimeout_MASK 0x70000 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET 19 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH 1 +#define DxFxxE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 +#define DxFxxE4_x70_Reserved_31_20_OFFSET 20 +#define DxFxxE4_x70_Reserved_31_20_WIDTH 12 +#define DxFxxE4_x70_Reserved_31_20_MASK 0xFFF00000 + +/// DxFxxE4_x70 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 RxRcbCplTimeout:3; ///< + UINT32 RxRcbCplTimeoutMode:1; ///< + UINT32 Reserved_31_20:12; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_x70_STRUCT; + +// **** DxFxxE4_xA0 Register Definition **** +// Address +#define DxFxxE4_xA0_ADDRESS 0xA0 +// Type +#define DxFxxE4_xA0_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA0_Reserved_3_0_OFFSET 0 +#define DxFxxE4_xA0_Reserved_3_0_WIDTH 4 +#define DxFxxE4_xA0_Reserved_3_0_MASK 0xF +#define DxFxxE4_xA0_Lc16xClearTxPipe_OFFSET 4 +#define DxFxxE4_xA0_Lc16xClearTxPipe_WIDTH 4 +#define DxFxxE4_xA0_Lc16xClearTxPipe_MASK 0xF0 +#define DxFxxE4_xA0_LcL0sInactivity_OFFSET 8 +#define DxFxxE4_xA0_LcL0sInactivity_WIDTH 4 +#define DxFxxE4_xA0_LcL0sInactivity_MASK 0xF00 +#define DxFxxE4_xA0_LcL1Inactivity_OFFSET 12 +#define DxFxxE4_xA0_LcL1Inactivity_WIDTH 4 +#define DxFxxE4_xA0_LcL1Inactivity_MASK 0xF000 +#define DxFxxE4_xA0_Reserved_22_16_OFFSET 16 +#define DxFxxE4_xA0_Reserved_22_16_WIDTH 7 +#define DxFxxE4_xA0_Reserved_22_16_MASK 0x7F0000 +#define DxFxxE4_xA0_LcL1ImmediateAck_OFFSET 23 +#define DxFxxE4_xA0_LcL1ImmediateAck_WIDTH 1 +#define DxFxxE4_xA0_LcL1ImmediateAck_MASK 0x800000 +#define DxFxxE4_xA0_Reserved_31_24_OFFSET 24 +#define DxFxxE4_xA0_Reserved_31_24_WIDTH 8 +#define DxFxxE4_xA0_Reserved_31_24_MASK 0xFF000000 + +/// DxFxxE4_xA0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4; ///< + UINT32 Lc16xClearTxPipe:4; ///< + UINT32 LcL0sInactivity:4; ///< + UINT32 LcL1Inactivity:4; ///< + UINT32 Reserved_22_16:7; ///< + UINT32 LcL1ImmediateAck:1; ///< + UINT32 Reserved_31_24:8; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA0_STRUCT; + +// **** DxFxxE4_xA1 Register Definition **** +// Address +#define DxFxxE4_xA1_ADDRESS 0xA1 +// Type +#define DxFxxE4_xA1_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA1_Reserved_10_0_OFFSET 0 +#define DxFxxE4_xA1_Reserved_10_0_WIDTH 11 +#define DxFxxE4_xA1_Reserved_10_0_MASK 0x7FF +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 +#define DxFxxE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 +#define DxFxxE4_xA1_Reserved_31_12_OFFSET 12 +#define DxFxxE4_xA1_Reserved_31_12_WIDTH 20 +#define DxFxxE4_xA1_Reserved_31_12_MASK 0xFFFFF000 + +/// DxFxxE4_xA1 +typedef union { + struct { ///< + UINT32 Reserved_10_0:11; ///< + UINT32 LcDontGotoL0sifL1Armed:1; ///< + UINT32 Reserved_31_12:20; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA1_STRUCT; + +// **** DxFxxE4_xA3 Register Definition **** +// Address +#define DxFxxE4_xA3_ADDRESS 0xA3 +// Type +#define DxFxxE4_xA3_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xA3_Reserved_8_0_OFFSET 0 +#define DxFxxE4_xA3_Reserved_8_0_WIDTH 9 +#define DxFxxE4_xA3_Reserved_8_0_MASK 0x1FF +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 +#define DxFxxE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 +#define DxFxxE4_xA3_Reserved_31_10_OFFSET 10 +#define DxFxxE4_xA3_Reserved_31_10_WIDTH 22 +#define DxFxxE4_xA3_Reserved_31_10_MASK 0xFFFFFC00 + +/// DxFxxE4_xA3 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9; ///< + UINT32 LcXmitFtsBeforeRecovery:1; ///< + UINT32 Reserved_31_10:22; ///< + + } Field; + + UINT32 Value; +} DxFxxE4_xA3_STRUCT; + +// **** DxFxxE4_xB1 Register Definition **** +// Address +#define DxFxxE4_xB1_ADDRESS 0xB1 +// Type +#define DxFxxE4_xB1_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xB1_Reserved_13_0_OFFSET 0 +#define DxFxxE4_xB1_Reserved_13_0_WIDTH 14 +#define DxFxxE4_xB1_Reserved_13_0_MASK 0x3FFF +#define DxFxxE4_xB1_LcElecIdleMode_OFFSET 14 +#define DxFxxE4_xB1_LcElecIdleMode_WIDTH 2 +#define DxFxxE4_xB1_LcElecIdleMode_MASK 0xc000 +#define DxFxxE4_xB1_Reserved_18_16_OFFSET 16 +#define DxFxxE4_xB1_Reserved_18_16_WIDTH 3 +#define DxFxxE4_xB1_Reserved_18_16_MASK 0x70000 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 +#define DxFxxE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 +#define DxFxxE4_xB1_LcBlockElIdleinL0_OFFSET 20 +#define DxFxxE4_xB1_LcBlockElIdleinL0_WIDTH 1 +#define DxFxxE4_xB1_LcBlockElIdleinL0_MASK 0x100000 +#define DxFxxE4_xB1_Reserved_31_21_OFFSET 21 +#define DxFxxE4_xB1_Reserved_31_21_WIDTH 11 +#define DxFxxE4_xB1_Reserved_31_21_MASK 0xFFE00000 + +/// DxFxxE4_xB1 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 LcElecIdleMode:2 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 LcDeassertRxEnInL0s:1; ///< + UINT32 LcBlockElIdleinL0:1; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + UINT32 Value; +} DxFxxE4_xB1_STRUCT; + +// **** DxFxxE4_xC0 Register Definition **** +// Address +// Type +#define DxFxxE4_xC0_TYPE TYPE_D2F1xE4 + +// Field Data +#define DxFxxE4_xC0_Reserved_3_0_OFFSET 0 +#define DxFxxE4_xC0_Reserved_3_0_WIDTH 4 +#define DxFxxE4_xC0_Reserved_3_0_MASK 0xF +#define DxFxxE4_xC0_Reserved_12_6_OFFSET 6 +#define DxFxxE4_xC0_Reserved_12_6_WIDTH 7 +#define DxFxxE4_xC0_Reserved_12_6_MASK 0x1FC0 +#define DxFxxE4_xC0_StrapForceCompliance_OFFSET 13 +#define DxFxxE4_xC0_StrapForceCompliance_WIDTH 1 +#define DxFxxE4_xC0_StrapForceCompliance_MASK 0x2000 +#define DxFxxE4_xC0_Reserved_14_14_OFFSET 14 +#define DxFxxE4_xC0_Reserved_14_14_WIDTH 1 +#define DxFxxE4_xC0_Reserved_14_14_MASK 0x4000 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define DxFxxE4_xC0_Reserved_31_19_OFFSET 19 +#define DxFxxE4_xC0_Reserved_31_19_WIDTH 13 +#define DxFxxE4_xC0_Reserved_31_19_MASK 0xfff80000 + +/// DxFxxE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 StrapMedyTSxCount:2 ; ///< + UINT32 Reserved_12_6:7 ; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 StrapLaneNegotiation:3 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; + UINT32 Value; +} DxFxxE4_xC0_STRUCT; + + + + +typedef union { + struct { ///< + UINT32 Reserved_1_0:2; ///< + UINT32 bit2:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 Reserved_7_4:4; ///< + UINT32 Reserved_8_8:1; ///< + UINT32 Reserved_31_9:23; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7208_STRUCT; + + +typedef union { + struct { ///< + UINT32 Reserved_16_0:17; ///< + UINT32 bit17:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} GnbRegistersKB7236_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 bit16:1; ///< + UINT32 Reserved_17_17:1; ///< + UINT32 Reserved_31_18:14; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7269_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_7_0:8; ///< + UINT32 StrapBifF0LegacyDeviceTypeDis:1; ///< + UINT32 Reserved_9_9:1; ///< + UINT32 bita:1; ///< + UINT32 Reserved_12_11:2; ///< + UINT32 bit13:1; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7314_STRUCT; + +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 bit_20:1; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} GnbRegistersKB7341_STRUCT; + + +// **** D0F0xD4_x010914E1 Register Definition **** +// Address +#define D0F0xD4_x010914E1_ADDRESS 0x10914E1 +// Type +#define D0F0xD4_x010914E1_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x010914E1_Reserved_0_0_OFFSET 0 +#define D0F0xD4_x010914E1_Reserved_0_0_WIDTH 1 +#define D0F0xD4_x010914E1_Reserved_0_0_MASK 0x1 +#define D0F0xD4_x010914E1_StrapBifRegApSize_OFFSET 1 +#define D0F0xD4_x010914E1_StrapBifRegApSize_WIDTH 2 +#define D0F0xD4_x010914E1_StrapBifRegApSize_MASK 0x6 +#define D0F0xD4_x010914E1_StrapBifMemApSize_OFFSET 3 +#define D0F0xD4_x010914E1_StrapBifMemApSize_WIDTH 3 +#define D0F0xD4_x010914E1_StrapBifMemApSize_MASK 0x38 +#define D0F0xD4_x010914E1_Reserved_11_6_OFFSET 6 +#define D0F0xD4_x010914E1_Reserved_11_6_WIDTH 6 +#define D0F0xD4_x010914E1_Reserved_11_6_MASK 0xFC0 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_OFFSET 12 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_WIDTH 1 +#define D0F0xD4_x010914E1_StrapBifDoorbellBarDis_MASK 0x1000 +#define D0F0xD4_x010914E1_Bitfield_13_13_OFFSET 13 +#define D0F0xD4_x010914E1_Bitfield_13_13_WIDTH 1 +#define D0F0xD4_x010914E1_Bitfield_13_13_MASK 0x2000 +#define D0F0xD4_x010914E1_Bitfield_15_14_OFFSET 14 +#define D0F0xD4_x010914E1_Bitfield_15_14_WIDTH 2 +#define D0F0xD4_x010914E1_Bitfield_15_14_MASK 0xC000 +#define D0F0xD4_x010914E1_Reserved_31_13_OFFSET 16 +#define D0F0xD4_x010914E1_Reserved_31_13_WIDTH 16 +#define D0F0xD4_x010914E1_Reserved_31_13_MASK 0xFFFF0000 + +/// D0F0xD4_x010914E1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 StrapBifRegApSize:2; ///< + UINT32 StrapBifMemApSize:3; ///< + UINT32 Reserved_11_6:6; ///< + UINT32 StrapBifDoorbellBarDis:1; ///< + UINT32 Bitfield_13_13:1; ///< + UINT32 Bitfield_15_14:2; ///< + UINT32 Reserved_31_13:16; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x010914E1_STRUCT; + +// **** D0F0xD4_x010914E2 Register Definition **** +// Address +#define D0F0xD4_x010914E2_ADDRESS 0x10914E2 +// Type +#define D0F0xD4_x010914E2_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x010914E2_Reserved_0_0_OFFSET 0 +#define D0F0xD4_x010914E2_Reserved_0_0_WIDTH 1 +#define D0F0xD4_x010914E2_Reserved_0_0_MASK 0x1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_OFFSET 1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_WIDTH 1 +#define D0F0xD4_x010914E2_StrapBifIoBarDis_MASK 0x2 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_OFFSET 3 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_WIDTH 1 +#define D0F0xD4_x010914E2_StrapBifF064BarDisA_MASK 0x8 + +/// D0F0xD4_x010914E2 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1; ///< + UINT32 StrapBifIoBarDis:1; ///< + UINT32 Reserved_2_2:1; ///< + UINT32 StrapBifF064BarDisA:1; ///< + UINT32 Reserved_7_4:4; ///< + UINT32 bit8:1; ///< + UINT32 Reserved_9_9:1; ///< + UINT32 bita:1; ///< + UINT32 Reserved_12_11:2; ///< + UINT32 bit13:1; ///< + UINT32 Reserved_31_14:18; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x010914E2_STRUCT; + +// **** D0F0xD4_x01091507 Register Definition **** +// Address +#define D0F0xD4_x01091507_ADDRESS 0x1091507 +// Type +#define D0F0xD4_x01091507_TYPE TYPE_D0F0xD4 + +// Field Data +#define D0F0xD4_x01091507_StrapBifMemApSizePin_OFFSET 5 +#define D0F0xD4_x01091507_StrapBifMemApSizePin_WIDTH 3 +#define D0F0xD4_x01091507_StrapBifMemApSizePin_MASK 0xE0 + +/// D0F0xD4_x01091507 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5; ///< + UINT32 StrapBifMemApSizePin:3; ///< + UINT32 Reserved_15_8:8; ///< + UINT32 bit16:1; ///< + UINT32 Reserved_31_17:15; ///< + + } Field; + + UINT32 Value; +} D0F0xD4_x01091507_STRUCT; + +typedef union { + struct { ///< + UINT32 bit0:1; ///< + UINT32 Reserved_31_1:31; ///< + + } Field; + + UINT32 Value; +} GnbRegistersKB7514_STRUCT; + + +// **** D0F0xFC_x00 Register Definition **** +// Address +#define D0F0xFC_x00_ADDRESS 0x0 +// Type +#define D0F0xFC_x00_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x00_IoapicEnable_OFFSET 0 +#define D0F0xFC_x00_IoapicEnable_WIDTH 1 +#define D0F0xFC_x00_IoapicEnable_MASK 0x1 +#define D0F0xFC_x00_Reserved_1_1_OFFSET 1 +#define D0F0xFC_x00_Reserved_1_1_WIDTH 1 +#define D0F0xFC_x00_Reserved_1_1_MASK 0x2 +#define D0F0xFC_x00_IoapicIdExtEn_OFFSET 2 +#define D0F0xFC_x00_IoapicIdExtEn_WIDTH 1 +#define D0F0xFC_x00_IoapicIdExtEn_MASK 0x4 +#define D0F0xFC_x00_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x00_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x00_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x00_IoapicSbFeatureEn_OFFSET 4 +#define D0F0xFC_x00_IoapicSbFeatureEn_WIDTH 1 +#define D0F0xFC_x00_IoapicSbFeatureEn_MASK 0x10 +#define D0F0xFC_x00_Reserved_31_5_OFFSET 5 +#define D0F0xFC_x00_Reserved_31_5_WIDTH 27 +#define D0F0xFC_x00_Reserved_31_5_MASK 0xFFFFFFE0 + +/// D0F0xFC_x00 +typedef union { + struct { ///< + UINT32 IoapicEnable:1; ///< + UINT32 Reserved_1_1:1; ///< + UINT32 IoapicIdExtEn:1; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 IoapicSbFeatureEn:1; ///< + UINT32 Reserved_31_5:27; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x00_STRUCT; + +// **** D0F0xFC_x0F Register Definition **** +// Address +#define D0F0xFC_x0F_ADDRESS 0x0F +// Type +#define D0F0xFC_x0F_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x0F_GBIFExtIntrGrp_OFFSET 0 +#define D0F0xFC_x0F_GBIFExtIntrGrp_WIDTH 3 +#define D0F0xFC_x0F_GBIFExtIntrGrp_MASK 0x7 +#define D0F0xFC_x0F_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x0F_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x0F_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x0F_GBIFExtIntrSwz_OFFSET 4 +#define D0F0xFC_x0F_GBIFExtIntrSwz_WIDTH 2 +#define D0F0xFC_x0F_GBIFExtIntrSwz_MASK 0x30 +#define D0F0xFC_x0F_Reserved_31_6_OFFSET 6 +#define D0F0xFC_x0F_Reserved_31_6_WIDTH 26 +#define D0F0xFC_x0F_Reserved_31_6_MASK 0xFFFFFFC0 + +/// D0F0xFC_xOF +typedef union { + struct { ///< + UINT32 GBIFExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 GBIFExtIntrSwz:2; ///< + UINT32 Reserved_31_6:26; ///< + } Field; + + UINT32 Value; +} D0F0xFC_x0F_STRUCT; + +// **** D0F0xFC_x10 Register Definition **** +// Address +#define D0F0xFC_x10_ADDRESS 0x10 +// Type +#define D0F0xFC_x10_TYPE TYPE_D0F0xFC + +// Field Data +#define D0F0xFC_x10_BrExtIntrGrp_OFFSET 0 +#define D0F0xFC_x10_BrExtIntrGrp_WIDTH 3 +#define D0F0xFC_x10_BrExtIntrGrp_MASK 0x7 +#define D0F0xFC_x10_Reserved_3_3_OFFSET 3 +#define D0F0xFC_x10_Reserved_3_3_WIDTH 1 +#define D0F0xFC_x10_Reserved_3_3_MASK 0x8 +#define D0F0xFC_x10_BrExtIntrSwz_OFFSET 4 +#define D0F0xFC_x10_BrExtIntrSwz_WIDTH 2 +#define D0F0xFC_x10_BrExtIntrSwz_MASK 0x30 +#define D0F0xFC_x10_Reserved_15_6_OFFSET 6 +#define D0F0xFC_x10_Reserved_15_6_WIDTH 10 +#define D0F0xFC_x10_Reserved_15_6_MASK 0xFFC0 +#define D0F0xFC_x10_BrIntIntrMap_OFFSET 16 +#define D0F0xFC_x10_BrIntIntrMap_WIDTH 5 +#define D0F0xFC_x10_BrIntIntrMap_MASK 0x1F0000 +#define D0F0xFC_x10_Reserved_31_21_OFFSET 21 +#define D0F0xFC_x10_Reserved_31_21_WIDTH 11 +#define D0F0xFC_x10_Reserved_31_21_MASK 0xFFE00000 + +/// D0F0xFC_x10 +typedef union { + struct { ///< + UINT32 BrExtIntrGrp:3; ///< + UINT32 Reserved_3_3:1; ///< + UINT32 BrExtIntrSwz:2; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 BrIntIntrMap:5; ///< + UINT32 Reserved_31_21:11; ///< + + } Field; + + UINT32 Value; +} D0F0xFC_x10_STRUCT; + + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 +// Type +#define D0F0x90_TYPE TYPE_D0F0 + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 +// Type +#define D0F0x94_TYPE TYPE_D0F0 + + +// **** D18F1xF0 Register Definition **** +// Address +#define D18F1xF0_ADDRESS 0xF0 +// Type +#define D18F1xF0_TYPE TYPE_D18F1 + +// **** D18F1x200 Register Definition **** +// Address +#define D18F1x200_ADDRESS 0x200 +// Type +#define D18F1x200_TYPE TYPE_D18F1 + +// **** D18F1x204 Register Definition **** +// Address +#define D18F1x204_ADDRESS 0x204 +// Type +#define D18F1x204_TYPE TYPE_D18F1 + +// **** D18F1x240 Register Definition **** +// Address +#define D18F1x240_ADDRESS 0x240 +// Type +#define D18F1x240_TYPE TYPE_D18F1 + +// **** D18F2x40_dct0 Register Definition **** +// Address +#define D18F2x40_dct0_ADDRESS 0x40 +// Type +#define D18F2x40_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x44_dct0 Register Definition **** +// Address +#define D18F2x44_dct0_ADDRESS 0x44 +// Type +#define D18F2x44_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x48_dct0 Register Definition **** +// Address +#define D18F2x48_dct0_ADDRESS 0x48 +// Type +#define D18F2x48_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x4C_dct0 Register Definition **** +// Address +#define D18F2x4C_dct0_ADDRESS 0x4C +// Type +#define D18F2x4C_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x60_dct0 Register Definition **** +// Address +#define D18F2x60_dct0_ADDRESS 0x60 +// Type +#define D18F2x60_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x64_dct0 Register Definition **** +// Address +#define D18F2x64_dct0_ADDRESS 0x64 +// Type +#define D18F2x64_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x80_dct0 Register Definition **** +// Address +#define D18F2x80_dct0_ADDRESS 0x80 +// Type +#define D18F2x80_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2xA8_dct0 Register Definition **** +// Address +#define D18F2xA8_dct0_ADDRESS 0xA8 +// Type +#define D18F2xA8_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x78_dct0 Register Definition **** +// Address +#define D18F2x78_dct0_ADDRESS 0x78 +// Type +#define D18F2x78_dct0_TYPE TYPE_D18F2_dct0 + +// **** D18F2x110 Register Definition **** +// Address +#define D18F2x110_ADDRESS 0x110 +// Type +#define D18F2x110_TYPE TYPE_D18F2 + +// **** D18F2x114 Register Definition **** +// Address +#define D18F2x114_ADDRESS 0x114 +// Type +#define D18F2x114_TYPE TYPE_D18F2 + +// **** DxFxx18 Register Definition **** +// Address +#define DxFxx18_ADDRESS 0x18 +// Type +#define DxFxx18_TYPE TYPE_D2F1 + +// **** DxFxx20 Register Definition **** +// Address +#define DxFxx20_ADDRESS 0x20 +// Type +#define DxFxx20_TYPE TYPE_D2F1 + +// **** DxFxx24 Register Definition **** +// Address +#define DxFxx24_ADDRESS 0x24 +// Type +#define DxFxx24_TYPE TYPE_D2F1 + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 +// Type +#define D0F0x60_TYPE TYPE_D0F0 + +// **** D0F0xB8 Register Definition **** +// Address +#define D0F0xB8_ADDRESS 0xB8 +// Type +#define D0F0xB8_TYPE TYPE_D0F0 + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xE0 +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// **** D0F0x64_x1F Register Definition **** +// Address +#define D0F0x64_x1F_ADDRESS 0x1F +// Type +#define D0F0x64_x1F_TYPE TYPE_D0F0x64 + +// **** D0F0xE4_PIF_0017 Register Definition **** +// Address +#define D0F0xE4_PIF_0017_ADDRESS 0x17 +// Type +#define D0F0xE4_PIF_0017_TYPE TYPE_D0F0xE4 + +// **** D0F2xF4_x49 Register Definition **** +// Address +// Type + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 + +// **** D0F0xE4_WRAP_8026 Register Definition **** +// Address +#define D0F0xE4_WRAP_8026_ADDRESS 0x8026 +// Type +#define D0F0xE4_WRAP_8026_TYPE TYPE_D0F0xE4 + +// **** D0F0xF8 Register Definition **** +// Address +#define D0F0xF8_ADDRESS 0xF8 +// Type +#define D0F0xF8_TYPE TYPE_D0F0 + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1A +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 + +// **** D0F0xBC_x20000 Register Definition **** +// Address +#define D0F0xBC_x20000_ADDRESS 0x20000 +// Type +#define D0F0xBC_x20000_TYPE TYPE_D0F0xBC + +// **** D0F0xBC_x0 Register Definition **** +// Address +#define D0F0xBC_x0_ADDRESS 0x0 +// Type +#define D0F0xBC_x0_TYPE TYPE_D0F0xBC + + + +// **** D0F0xBC_xC210003C Register Definition **** +// Address +#define D0F0xBC_xC210003C_ADDRESS 0xC210003C +// Type +#define D0F0xBC_xC210003C_TYPE TYPE_D0F0xBC + +// **** D0F0xD4_x010914C3 Register Definition **** +// Address +#define D0F0xD4_x010914C3_ADDRESS 0x010914C3 +// Type +#define D0F0xD4_x010914C3_TYPE TYPE_D0F0xD4 + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h new file mode 100644 index 0000000000..2bf8952d29 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBURA_H_ +#define _GNBURA_H_ + +#include "GnbPcie.h" + +/// Generic device object +typedef struct { + PCI_ADDR DevPciAddress; ///< DevPciAddress + GNB_HANDLE *GnbHandle; ///< GnbHandle + AMD_CONFIG_PARAMS *StdHeader; ///< +} DEV_OBJECT; + +/// Register address 32 bit encoding +typedef struct { + UINT32 Address: 31; ///< Register address + UINT32 MultInst: 1; ///< Must equals to 0 +} URA_REGISTER_32B_ENTRY; + +/// Register address encoding that represents a group of registers that have same fields' definitions +typedef struct { + UINT32 Addr: 24; ///< Register address + UINT32 InstOffset: 7; ///< The address offset between register instances + UINT32 MultInst: 1; ///< Must equals to 1 +} URA_MULT_REG_ENTRY; + +/// 16 bit field encoding +typedef struct { + UINT16 BfOffset: 6; ///< Offset of the bit field + UINT16 BfWidth: 6; ///< Width of the bit field + UINT16 Offset: 4; ///< Number of field entries from its register address entry + ///< The first field entry of a register must be place right after its register entry and has offset 1. + ///< The second field is placed right after the first field and has offset 2 and so on. + ///< The offset field is maxed out at 15. So any entries after the 15th entries will take offset 0. +} URA_FIELD_16B_ENTRY; + +/// 32 bit field encoding +typedef struct { + UINT32 BfOffset: 6; ///< Offset of the bit field + UINT32 BfWidth: 6; ///< Width of the bit field + UINT32 RegIndex: 13; ///< Direct index to its register address entry + UINT32 Rev: 6; ///< Contains ID of the family/rev that this bit field is valid + UINT32 Reserved: 1; ///< Reserved +} URA_FIELD_32B_ENTRY; + +/// Register address 64 bit encoding +typedef struct { + UINT64 DomainAddress:32; ///< Register domain address + UINT64 DomainType: 8; ///< Register domain type + UINT64 Reserved: 24; ///< Reserved +} URA_REGISTER_64B_ENTRY; + +/// Register / Field table entry +#define URA_ENTRY UINT16 + +/// Token +typedef union { + UINT32 Encode; ///< Token value + + struct { ///< Sub structure used to parse Token + UINT32 Index: 13; ///< Index into a specific register or field entry in register/field table + UINT32 Type: 3; ///< Entry type: + ///< 000b: 16-bit field location encoding + ///< 001b: Register address encoding + ///< 010b: 32-bit field location encoding + ///< 011b: 64-bit field location encoding + ///< Others would reserved + UINT32 Selector: 6; ///< Used by unified register access to select the access method + UINT32 InstSel: 6; ///< When register/field has multiple instances, this field is used to obtain the register address of a register group. + UINT32 S3Save:1; ///< Indicate whether S3Save is needed. + UINT32 StreamSet:1; ///< Stream Set + UINT32 ParentType:1; ///< Parent token type + UINT32 Reserved: 1; ///< Reserved for device specific usage + } Parser; +} URA_TOKEN_STRUCT; + +#define URA_TOKEN UINT32 + +#define URA_TYPE_FIELD_16 0 +#define URA_TYPE_FIELD_32 1 +#define URA_TYPE_REGISTER_32 2 +#define URA_TYPE_REGISTER_64 3 + +#define URA_TOKEN_PARENT_TYPE_32 0x20000000ul +#define URA_TOKEN_PARENT_TYPE_64 0x00000000ul + +/** + TOKEN_DEF(Index, Type, Selector) + Defines a register of field token + + @param[in] Index + @param[in] Type + @param[in] Selector + @param[in] ParentType + + @return URA_TOKEN Encrypted URA_TOKEN format +--*/ +#define TOKEN_DEF(Index, Type, Selector, ParentType) ( \ + (((UINT32) (Index)) | (((UINT32) (Type)) << 13) | (((UINT32) (Selector)) << 16) | ((UINT32) (ParentType))) \ + ) + +#define _RESERVED 0xFFFFFFFFul +#define _UNUSED 0xFEFEFEFEul +#define GNB_URA_FLAG_S3SAVE 0x00000001ul +#define GNB_URA_STREAM_SET 0x20000000ul + +/// Structure used to pass token info to access methods +typedef struct { + UINT32 RegAddress; ///< Register address + UINT8 BfOffset; ///< Offset of the bit field + UINT8 BfWidth; ///< Width of the bit field + BOOLEAN WholeRegAccess; ///< Whole register access + UINT32 MethodType; ///< Index into the access method table to select access method + UINT32 Flags; ///< S3 + UINT32 StreamSet; ///< StreamSet + UINT8 RegDomainType; ///< Register Domain type +} URA_TOKEN_INFO; + +#define TYPE_GNB_INDIRECT_ACCESS 0 +#define TYPE_GNB_PROTOCOL_ACCESS 1 + +/// URA_TUPLE +typedef struct { + URA_TOKEN Token; ///< Token + UINT32 Value; ///< Token value + UINT32 StepLength; ///< Byte length to next address for stream set usage. +} URA_TUPLE; + +typedef VOID F_GNBURASERVICELOCATEREGTBL ( + IN DEV_OBJECT *Device, + IN UINT32 *UraTableAddress + ); + +typedef VOID F_GNBURASERVICEGET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +typedef VOID F_GNBURASERVICESET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +typedef VOID F_GNBURASERVICESTREAMSET ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +/// Register Read/Write protocol +typedef struct { + F_GNBURASERVICELOCATEREGTBL *GnbUraLocateRegTbl; ///< + F_GNBURASERVICEGET *GnbUraGet; ///< + F_GNBURASERVICESET *GnbUraSet; ///< + F_GNBURASERVICESTREAMSET *GnbUraStreamSet; ///< +} GNB_URA_SERVICE; + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h new file mode 100644 index 0000000000..c4e51b0588 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBURASERVICES_H_ +#define _GNBURASERVICES_H_ + +#include "GnbUra.h" +#include "GnbUraToken.h" + +/*---------------------------------------------------------------------------- + * FUNCTION PROTOTYPES + * + *---------------------------------------------------------------------------- + */ + +VOID +GnbUraGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN OUT VOID *Value + ); + +VOID +GnbUraSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraToken, + IN VOID *Value + ); + +VOID +GnbUraCombinedGet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +VOID +GnbUraCombinedSet ( + IN DEV_OBJECT *Device, + IN URA_TOKEN UraTokenRegister, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h new file mode 100644 index 0000000000..29683607ca --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +#ifndef _GNBURATOKEN_H_ +#define _GNBURATOKEN_H_ + +/// Template structure for register/field table +typedef struct { + URA_REGISTER_64B_ENTRY RxSmuIntReq;///< + URA_FIELD_16B_ENTRY BfxSmuIntToggle;///< + URA_FIELD_16B_ENTRY BfxSmuServiceIndex;///< + URA_REGISTER_64B_ENTRY RxSmuIntSts;///< + URA_FIELD_16B_ENTRY BfxSmuIntAck;///< + URA_FIELD_16B_ENTRY BfxSmuIntDone;///< + URA_REGISTER_64B_ENTRY RxSmuAuthSts;///< + URA_FIELD_16B_ENTRY BfxSmuAuthDone;///< + URA_FIELD_16B_ENTRY BfxSmuAuthPass;///< + URA_REGISTER_64B_ENTRY RxSmuFwAuth;///< + URA_FIELD_16B_ENTRY BfxSmuProtectedMode;///< + URA_REGISTER_64B_ENTRY REG_FIELD_TABLE_STRUCT_fld11;///< + URA_FIELD_16B_ENTRY BfxSmuBootSeqDone;///< + URA_REGISTER_64B_ENTRY RxSmuFwFlags;///< + URA_FIELD_16B_ENTRY BfxSmuInterruptsEnabled;///< + URA_REGISTER_64B_ENTRY RxSmuResetCntl;///< + URA_FIELD_16B_ENTRY BfxSmuRstReg;///< + URA_REGISTER_64B_ENTRY RxSmuClkCntl;///< + URA_FIELD_16B_ENTRY BfxSmuCkDisable;///< + URA_REGISTER_64B_ENTRY RxSmuAuthVector;///< + URA_REGISTER_64B_ENTRY RxSmuRamStartAddr;///< + URA_REGISTER_64B_ENTRY RxSmuRomStartAddr;///< + URA_REGISTER_64B_ENTRY RxSmuIntArgument;///< + +} REG_FIELD_TABLE_STRUCT; + +#define IDX_CALC(VarName) (offsetof (REG_FIELD_TABLE_STRUCT, VarName) / 2) /* TODO: why ## */ +#define SEL_CALC(VarName) VarName +#define FIELD_OFFSET(RegName, FieldName) ((((IDX_CALC(FieldName) - IDX_CALC(RegName) - 1) / 2) <= 15) ? ((IDX_CALC(FieldName) - IDX_CALC(RegName) - 1) / 2) : 0) + +#define TRxSmuIntReq TOKEN_DEF (IDX_CALC (RxSmuIntReq), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntToggle TOKEN_DEF (IDX_CALC (BfxSmuIntToggle), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuServiceIndex TOKEN_DEF (IDX_CALC (BfxSmuServiceIndex), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuIntSts TOKEN_DEF (IDX_CALC (RxSmuIntSts), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntAck TOKEN_DEF (IDX_CALC (BfxSmuIntAck), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuIntDone TOKEN_DEF (IDX_CALC (BfxSmuIntDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuAuthSts TOKEN_DEF (IDX_CALC (RxSmuAuthSts), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuAuthDone TOKEN_DEF (IDX_CALC (BfxSmuAuthDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuAuthPass TOKEN_DEF (IDX_CALC (BfxSmuAuthPass), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuFwAuth TOKEN_DEF (IDX_CALC (RxSmuFwAuth), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuProtectedMode TOKEN_DEF (IDX_CALC (BfxSmuProtectedMode), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRcuUcEvents TOKEN_DEF (IDX_CALC (REG_FIELD_TABLE_STRUCT_fld11), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuBootSeqDone TOKEN_DEF (IDX_CALC (BfxSmuBootSeqDone), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuFwFlags TOKEN_DEF (IDX_CALC (RxSmuFwFlags), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_PROTOCOL_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuInterruptsEnabled TOKEN_DEF (IDX_CALC (BfxSmuInterruptsEnabled), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_PROTOCOL_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuResetCntl TOKEN_DEF (IDX_CALC (RxSmuResetCntl), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuRstReg TOKEN_DEF (IDX_CALC (BfxSmuRstReg), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuClkCntl TOKEN_DEF (IDX_CALC (RxSmuClkCntl), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TBfxSmuCkDisable TOKEN_DEF (IDX_CALC (BfxSmuCkDisable), URA_TYPE_FIELD_16, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuAuthVector TOKEN_DEF (IDX_CALC (RxSmuAuthVector), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRamStartAddr TOKEN_DEF (IDX_CALC (RxSmuRamStartAddr), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuRomStartAddr TOKEN_DEF (IDX_CALC (RxSmuRomStartAddr), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) +#define TRxSmuIntArgument TOKEN_DEF (IDX_CALC (RxSmuIntArgument), URA_TYPE_REGISTER_64, SEL_CALC (TYPE_GNB_INDIRECT_ACCESS), URA_TOKEN_PARENT_TYPE_64) + + +#endif + |