diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc')
3 files changed, 5 insertions, 5 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c index fcd7bf466c..e9c89227dc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S index 4ab535a3fe..c1e7ab7b6c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S @@ -187,7 +187,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c index f28159363b..4b6b6ec675 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c @@ -188,7 +188,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); |