diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h | 72 |
1 files changed, 0 insertions, 72 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h index 963d96da66..6b15aaf38b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h @@ -892,78 +892,6 @@ // Device 20 (0x14) Func 2 // -#define FCH_AZ_REG00 0x00 // Vendor ID - R -#define FCH_AZ_REG02 0x02 // Device ID - R/W -#define FCH_AZ_REG04 0x04 // PCI Command -#define FCH_AZ_REG06 0x06 // PCI Status - R/W -#define FCH_AZ_REG08 0x08 // Revision ID -#define FCH_AZ_REG09 0x09 // Programming Interface -#define FCH_AZ_REG0A 0x0A // Sub Class Code -#define FCH_AZ_REG0B 0x0B // Base Class Code -#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W -#define FCH_AZ_REG0D 0x0D // Latency Timer -#define FCH_AZ_REG0E 0x0E // Header Type -#define FCH_AZ_REG0F 0x0F // BIST -#define FCH_AZ_REG10 0x10 // Lower Base Address Register -#define FCH_AZ_REG14 0x14 // Upper Base Address Register -#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID -#define FCH_AZ_REG2D 0x2D // Subsystem ID -#define FCH_AZ_REG34 0x34 // Capabilities Pointer -#define FCH_AZ_REG3C 0x3C // Interrupt Line -#define FCH_AZ_REG3D 0x3D // Interrupt Pin -#define FCH_AZ_REG3E 0x3E // Minimum Grant -#define FCH_AZ_REG3F 0x3F // Maximum Latency -#define FCH_AZ_REG40 0x40 // Misc Control 1 -#define FCH_AZ_REG42 0x42 // Misc Control 2 Register -#define FCH_AZ_REG43 0x43 // Misc Control 3 Register -#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register -#define FCH_AZ_REG46 0x46 // Debug Control Register -#define FCH_AZ_REG4C 0x4C -#define FCH_AZ_REG50 0x50 // Power Management Capability ID -#define FCH_AZ_REG52 0x52 // Power Management Capabilities -#define FCH_AZ_REG54 0x54 // Power Management Control/Status -#define FCH_AZ_REG60 0x60 // MSI Capability ID -#define FCH_AZ_REG62 0x62 // MSI Message Control -#define FCH_AZ_REG64 0x64 // MSI Message Lower Address -#define FCH_AZ_REG68 0x68 // MSI Message Upper Address -#define FCH_AZ_REG6C 0x6C // MSI Message Data - -#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R -#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R -#define FCH_AZ_BAR_REG03 0x03 // Major Version - R -#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R -#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R -#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W -#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W -#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W -#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W -#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R -#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R -#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W -#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W -#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R -#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W -#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W -#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW -#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W -#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W -#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W -#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W -#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W -#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW -#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW -#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW -#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W -#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W -#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W -#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W -#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W -#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W -#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W -#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W -#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W -#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R - // // FCH LPC Device 0x780E // Device 20 (0x14) Func 3 |