diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc/Mem/Ps')
31 files changed, 0 insertions, 7993 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc deleted file mode 100644 index 209b77f445..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -libagesa-y += mprc32_3.c -libagesa-y += mpuc32_3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c deleted file mode 100644 index 802a48e4fa..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c +++ /dev/null @@ -1,325 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc32_3.c - * - * Platform specific settings for C32 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* - * ODT Settings for 1 or 2 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} -}; -/* - * ODT Settings for 3 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = { - {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = { - {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, - {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = { - {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0} - -}; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsRC32_3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsRC32_3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for R-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { - DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D); - DramTermPtr = C32RDdr3DramTerm2D; - } else if (MaxDimmsPerChannel == 3) { - DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D); - DramTermPtr = C32RDdr3DramTerm3D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - // - // Special Cases for certain configs not covered by the table - // - // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066) - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) && - (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) { - NBPtr->PsPtr->DramTerm = 5; //30 Ohms - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for R-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitRC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - UINT8 FreqLimitSize; - UINT16 SpeedLimit; - CONST POR_SPEED_LIMIT *FreqLimitPtr; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - if (MaxDimmPerCH == 4) { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - return; - } else if (MaxDimmPerCH == 3) { - FreqLimitPtr = C32RDdr3PSPorFreqLimit3D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D); - } else if (MaxDimmPerCH == 2) { - FreqLimitPtr = C32RDdr3PSPorFreqLimit2D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D); - } else { - FreqLimitPtr = C32RDdr3PSPorFreqLimit1D; - FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D); - } - - SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); - - if (SpeedLimit != 0) { - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - } else { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c deleted file mode 100644 index 2dbc362bfc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c +++ /dev/null @@ -1,204 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpuc32_3.c - * - * Platform specific settings for C32 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "PlatformMemoryConfiguration.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsUC32_3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsUC32_3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for U-DDR3 C32 DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for SO-DDR3 C32 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitUC32_3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066 - // - if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) { - MaxSpeed = DDR1066_FREQUENCY; - } else { - // - // Highest POR supported speed for Unbuffered dimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - } - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { - // Unbuffered DDR3 at 333MHz is not supported - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc deleted file mode 100644 index fa2029006c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mprhy3.c -libagesa-y += mpshy3.c -libagesa-y += mpuhy3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c deleted file mode 100644 index 24d4384e05..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c +++ /dev/null @@ -1,324 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprhy3.c - * - * Platform specific settings for HY DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ - -/* - * ODT Settings for 1 Dimm or 2 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1} -}; -/* - * ODT Settings for 3 Dimms Per Channel - * - * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm - */ -STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = { - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2}, - {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2}, - {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2}, - {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1}, - {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = { - {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = { - {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0} -}; -/* - * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel - * - * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25 - */ -STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = { - {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}, - {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}, - {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsRHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsRHy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3; - - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for R-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) { - DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D); - DramTermPtr = HyRDdr3DramTerm2D; - } else if (MaxDimmsPerChannel == 3) { - DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D); - DramTermPtr = HyRDdr3DramTerm3D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - // - // Special Cases for certain configs not covered by the table - // - // 3DPCH Fully populated. - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { - NBPtr->PsPtr->DramTerm = 5; //30 Ohms - NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for R-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitRHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 *DimmsPerChPtr; - UINT8 MaxDimmPerCH; - UINT8 FreqLimitSize; - UINT16 SpeedLimit; - CONST POR_SPEED_LIMIT *FreqLimitPtr; - DCT_STRUCT *DCTPtr; - - DCTPtr = NBPtr->DCTPtr; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmPerCH = *DimmsPerChPtr; - } else { - MaxDimmPerCH = 2; - } - - if (MaxDimmPerCH == 4) { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - return; - } else if (MaxDimmPerCH == 3) { - FreqLimitPtr = HyRDdr3PSPorFreqLimit3D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D); - } else if (MaxDimmPerCH == 2) { - FreqLimitPtr = HyRDdr3PSPorFreqLimit2D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D); - } else { - FreqLimitPtr = HyRDdr3PSPorFreqLimit1D; - FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D); - } - - SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr); - - if (SpeedLimit != 0) { - if (DCTPtr->Timings.TargetSpeed > SpeedLimit) { - DCTPtr->Timings.TargetSpeed = SpeedLimit; - } - } else { - DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c deleted file mode 100644 index 10595418eb..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c +++ /dev/null @@ -1,220 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpshy3.c - * - * Platform specific settings for HY DDR3 SO-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = { - {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0}, - {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0} -}; - -STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsSHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsSHy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for S-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST DRAM_TERM_ENTRY *DramTermPtr; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - UINT8 DramTermSize; - - DramTermSize = 0; - DramTermPtr = NULL; - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - if (MaxDimmsPerChannel == 1) { - DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D); - DramTermPtr = HySDdr3DramTerm1D; - } else if (MaxDimmsPerChannel == 2) { - DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D); - DramTermPtr = HySDdr3DramTerm2D; - } else { - IDS_ERROR_TRAP; - } - - if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for SO-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitSHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // Highest POR supported speed for SODimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c deleted file mode 100644 index 1aa93587d3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c +++ /dev/null @@ -1,198 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpuhy3.c - * - * Platform specific settings for HY DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/* This file contains routine that add platform specific support L1 */ - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPDoPsUhy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -STATIC -MemPGetPORFreqLimitUHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = { - {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}, - {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2}, - {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}, - {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1} -}; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the constructor for the platform specific settings for U-DDR3 HY DDR3 - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_SUCCESS - * - */ - -AGESA_STATUS -MemPConstructPsUHy3 ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - ASSERT (MemPtr != 0); - ASSERT (ChannelPtr != 0); - - if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) { - return AGESA_UNSUPPORTED; - } - if (ChannelPtr->TechType != DDR3_TECHNOLOGY) { - return AGESA_UNSUPPORTED; - } - if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) { - return AGESA_UNSUPPORTED; - } - PsPtr->MemPDoPs = MemPDoPsUhy3; - PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3; - return AGESA_SUCCESS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function sets the platform specific settings for U-DDR3 HY DDR3 - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Find settings for corresponding platform and dimm population. - * @return FALSE - Fail to find settings for corresponding platform and dimm population. - * - */ - -BOOLEAN -STATIC -MemPDoPsUhy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) { - return FALSE; - } - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is function gets the POR speed limit for U-DDR3 HY - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * - */ -VOID -STATIC -MemPGetPORFreqLimitUHy3 ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT16 MaxSpeed; - // - // Highest POR supported speed for Unbuffered dimm is 1333 - // - MaxSpeed = DDR1333_FREQUENCY; - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed; - } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) { - // Unbuffered DDR3 at 333MHz is not supported - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc deleted file mode 100644 index 5eb7129f90..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -libagesa-y += mp.c -libagesa-y += mplribt.c -libagesa-y += mplrnlr.c -libagesa-y += mplrnpr.c -libagesa-y += mpmaxfreq.c -libagesa-y += mpmr0.c -libagesa-y += mpodtpat.c -libagesa-y += mprc10opspd.c -libagesa-y += mprc2ibt.c -libagesa-y += mprtt.c -libagesa-y += mps2d.c -libagesa-y += mpsao.c -libagesa-y += mpseeds.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc deleted file mode 100644 index 45e839c04f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mpLorC3.c -libagesa-y += mpRorC3.c -libagesa-y += mpUorC3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c deleted file mode 100644 index 711acef9c6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c +++ /dev/null @@ -1,320 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpLorC3.c - * - * Platform specific settings for OR C32 DDR3 LRDIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 56315 $ @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - - -#define FILECODE PROC_MEM_PS_OR_C32_MPLORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32LRDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 0, 0x00383A38, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00383C38, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00353A35, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 0, 0x00363A36, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntLRC32 = { - {PSCFG_SAO, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32LRDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32LRDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32LRDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1066, VOLT_ALL, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntLRC32 = { - {PSCFG_S__, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32LRDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32LRDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1LRDdr3OdtPat[] = { - {DIMM_LR, 0x00000000, 0x00000000, 0x00000101, 0x00000101} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntLRC32 = { - {PSCFG_ODT_PAT_1D, LRDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1LRDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1LRDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2LRDdr3OdtPat[] = { - {NP, DIMM_LR, 0x00000000, 0x00000000, 0x02020000, 0x02020000}, - {DIMM_LR, DIMM_LR, 0x01010202, 0x01010202, 0x03030303, 0x03030303} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntLRC32 = { - {PSCFG_ODT_PAT___, LRDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2LRDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2LRDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3LRDdr3OdtPat[] = { - {NP, NP, DIMM_LR, 0x00000000, 0x00000000, 0x00000404, 0x00000000}, - {DIMM_LR, NP, DIMM_LR, 0x00000101, 0x00000404, 0x00000505, 0x00000505}, - {DIMM_LR, DIMM_LR, DIMM_LR, 0x00000303, 0x05050606, 0x00000707, 0x07070707} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntLRC32 = { - {PSCFG_ODT_PAT_3D, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3LRDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, RttNom, RttWr -// -STATIC CONST PSCFG_LR_RTT_ENTRY DramTermOrC32LRDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1, 0}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_LR, NP, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 3, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntLRC32 = { - {PSCFG_LR_RTT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32LRDIMM) / sizeof (PSCFG_LR_RTT_ENTRY), - (VOID *)&DramTermOrC32LRDIMM -}; -// Max Freq. -// Format : -// DimmPerCh, Dimms, LR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_LR_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32LRDIMM[] = { - {{1, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 3, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntLRC32 = { - {PSCFG_LR_MAXFREQ, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32LRDIMM) / sizeof (PSCFG_LR_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32LRDIMM -}; - -// IBT -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, F0RC8, F1RC0, F1RC1, F1RC2 -// -STATIC CONST PSCFG_L_IBT_ENTRY OrLRDdr3IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 1, 1, 1, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800 + DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800, V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, -}; -CONST PSC_TBL_ENTRY IBTTblEntLRC32 = { - {PSCFG_LR_IBT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3IBT) / sizeof (PSCFG_L_IBT_ENTRY), - (VOID *)&OrLRDdr3IBT -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3LRDdr3CLKDis[] = {0x03, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntLRC32 = { - {PSCFG_CLKDIS, LRDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3LRDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0xF7} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntLRC32 = { - {PSCFG_WL_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32LRDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_A, 0x132}, - {_1DIMM + _2DIMM + _3DIMM, CH_B, 0x122} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntLRC32 = { - {PSCFG_HWRXEN_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32LRDIMM -};
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c deleted file mode 100644 index de25ec8de9..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c +++ /dev/null @@ -1,653 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpRorC3.c - * - * Platform specific settings for OR C32 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" - -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_OR_C32_MPRORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32RDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x00222222}, - {1, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x10222222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x003C3C3C, 0x30222222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x00222222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00393C39, 0x20222222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00390039, 0x20222222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x20222222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntRC32 = { - {PSCFG_SAO, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32RDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32RDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32RDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 1}, - {1, DDR1333, V1_5, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 1}, - {1, DDR1333, V1_35 + V1_25, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1}, - {2, DDR1333, V1_35 + V1_25, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntRC32 = { - {PSCFG_S__, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32RDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32RDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1RDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}, - {DIMM_QR, 0x00000000, 0x00000000, 0x00000505, 0x00000505} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntRC32 = { - {PSCFG_ODT_PAT_1D, RDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1RDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1RDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2RDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {NP, DIMM_QR, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}, - {DIMM_SR + DIMM_DR, DIMM_QR, 0x01010000, 0x01010A0A, 0x01090000, 0x01030E0B}, - {DIMM_QR, DIMM_SR + DIMM_DR, 0x00000202, 0x05050202, 0x00000206, 0x0D070203}, - {DIMM_QR, DIMM_QR, 0x05050A0A, 0x05050A0A, 0x050D0A0E, 0x05070A0B} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntRC32 = { - {PSCFG_ODT_PAT___, RDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2RDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2RDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3RDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000303, 0x05050606, 0x00000307, 0x0D070607}, - {NP, DIMM_QR, NP, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {NP, DIMM_QR, DIMM_SR + DIMM_DR, 0x04040A0A, 0x04040000, 0x040C0A0E, 0x04060000}, - {DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0x05050B0B, 0x05050E0E, 0x050D0B0F, 0x05070E0F} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntRC32 = { - {PSCFG_ODT_PAT_3D, RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3RDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrC32RDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 2, 2}, - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 1, 2}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, VOLT_ALL, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntRC32 = { - {PSCFG_RTT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32RDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrC32RDIMM -}; - -// POR Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32RDIMM[] = { - {{1, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 0, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 0, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 3, 0, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 2, 1, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 2, 0, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 2, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 1, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 3, 0, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 2, 1, DDR667_FREQUENCY, DDR667_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntRC32 = { - {PSCFG_MAXFREQ, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32RDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32RDIMM -}; - -// RC2[IBT] -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, NumOfReg, IBT -// -STATIC CONST PSCFG_MR2IBT_ENTRY OrRDdr3RC2IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 0xF, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_5, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_35, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1066, VOLT_ALL, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, NP + DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, -}; -CONST PSC_TBL_ENTRY RC2IBTTblEntRC32 = { - {PSCFG_RC2IBT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3RC2IBT) / sizeof (PSCFG_MR2IBT_ENTRY), - (VOID *)&OrRDdr3RC2IBT -}; - -// RC10[OperatingSpeed] -// Format : -// DDRrate, Operating Speed -// -STATIC CONST PSCFG_OPSPD_ENTRY OrRDdr3OpSPD[] = { - {DDR667 + DDR800, 0}, - {DDR1066, 1}, - {DDR1333, 2}, - {DDR1600, 3} -}; -CONST PSC_TBL_ENTRY RC10OpSpdTblEntRC32 = { - {PSCFG_RC10OPSPD, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3OpSPD) / sizeof (PSCFG_OPSPD_ENTRY), - (VOID *)&OrRDdr3OpSPD -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3RDdr3CLKDis[] = {0x03, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntRC32 = { - {PSCFG_CLKDIS, RDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3RDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32RDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x3E} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntRC32 = { - {PSCFG_WL_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32RDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32RDIMM[] = { - {_1DIMM + _2DIMM, CH_A, 0x3F}, - {_1DIMM + _2DIMM, CH_B, 0x3E}, - {_3DIMM, CH_A, 0x47}, - {_3DIMM, CH_B, 0x38} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32 = { - {PSCFG_HWRXEN_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32RDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c deleted file mode 100644 index 89d6da71d5..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c +++ /dev/null @@ -1,343 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpUorC3.c - * - * Platform specific settings for OR C32 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/C32) - * @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_OR_C32_MPUORC3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrC32UDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00383837, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00363635, 0x30112222}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00333330, 0x30332222}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003330, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00383837, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3A3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363635, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00353533, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00003533, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10222222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x20222222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00383837, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A3A3A, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00363635, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, 0, 0x00353533, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, 1, 0x00003533, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntUC32 = { - {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrC32UDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrC32UDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1600, V1_35, DIMM_SR + DIMM_DR, NP, NP, 1}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, }; -CONST PSC_TBL_ENTRY S__TblEntUC32 = { - {PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrC32UDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrC32UDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntUC32 = { - {PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1UDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntUC32 = { - {PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2UDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntUC32 = { - {PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3UDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrC32UDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1600, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1600, V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntUC32 = { - {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (DramTermOrC32UDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrC32UDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrC32UDIMM[] = { - {{1, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntUC32 = { - {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrC32UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrC32UDIMM -}; - -// -// MemClkDis [1DPC & 2DPC] -// -STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x01, 0x04, 0x02, 0x08, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntUC32 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CLKDis) / sizeof (UINT8), - (VOID *)&OrUDdr3CLKDis -}; - -// -// MemClkDis [3DPC] -// -STATIC CONST UINT8 ROMDATA Or3UDdr3CLKDis[] = {0x01, 0x02, 0x10, 0x20, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMap3DEntUC32 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3UDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrC32UDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x12} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntUC32 = { - {PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrC32UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrC32UDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrC32UDIMM[] = { - {_1DIMM + _2DIMM, CH_A, 0x39}, - {_1DIMM + _2DIMM, CH_B, 0x32}, - {_3DIMM, CH_A, 0x45}, - {_3DIMM, CH_B, 0x37} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32 = { - {PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_C32, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrC32UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrC32UDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc deleted file mode 100644 index 173efca5b6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -libagesa-y += mpLorG3.c -libagesa-y += mpRorG3.c -libagesa-y += mpUorG3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c deleted file mode 100644 index 3b26f68407..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c +++ /dev/null @@ -1,336 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpLorG3.c - * - * Platform specific settings for OR G34 DDR3 LRDIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 58717 $ @e \$Date: 2011-09-05 23:20:11 -0600 (Mon, 05 Sep 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_PS_OR_G34_MPLORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34LRDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1600, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0x00393939, 0x30332222}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0x00393939, 0x30112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 0, 0x00353935, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 0, 0x00303A30, 0x30112222}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 0, 0x00343934, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntLRG34 = { - {PSCFG_SAO, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34LRDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34LRDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34LRDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_LR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_LR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 0}, - {2, DDR1333, V1_5 + V1_35, NP + DIMM_LR, DIMM_LR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_LR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR800, V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1066 + DDR1600, V1_5, NP, NP, DIMM_LR, 1}, - {3, DDR1066, V1_5, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_35 + V1_25, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_LR, NP, DIMM_LR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_LR, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntLRG34 = { - {PSCFG_S__, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34LRDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34LRDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1LRDdr3OdtPat[] = { - {DIMM_LR, 0x00000000, 0x00000000, 0x00000101, 0x00000101} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntLRG34 = { - {PSCFG_ODT_PAT_1D, LRDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1LRDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1LRDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2LRDdr3OdtPat[] = { - {NP, DIMM_LR, 0x00000000, 0x00000000, 0x02020000, 0x02020000}, - {DIMM_LR, DIMM_LR, 0x01010202, 0x01010202, 0x03030303, 0x03030303} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntLRG34 = { - {PSCFG_ODT_PAT___, LRDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2LRDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2LRDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3LRDdr3OdtPat[] = { - {NP, NP, DIMM_LR, 0x00000000, 0x00000000, 0x00000404, 0x00000000}, - {DIMM_LR, NP, DIMM_LR, 0x00000101, 0x00000404, 0x00000505, 0x00000505}, - {DIMM_LR, DIMM_LR, DIMM_LR, 0x00000303, 0x05050606, 0x00000707, 0x07070707} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntLRG34 = { - {PSCFG_ODT_PAT_3D, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3LRDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, RttNom, RttWr -// -STATIC CONST PSCFG_LR_RTT_ENTRY DramTermOrG34LRDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 1, 0}, - {1, DDR1600 + DDR1866, V1_5, DIMM_LR, NP, NP, 3, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_LR, NP, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 3, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 5, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_LR, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_LR, NP, DIMM_LR, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 1}, - {3, DDR1066, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 1}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 5, 2}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 5, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntLRG34 = { - {PSCFG_LR_RTT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34LRDIMM) / sizeof (PSCFG_LR_RTT_ENTRY), - (VOID *)&DramTermOrG34LRDIMM -}; -// Max Freq. -// Format : -// DimmPerCh, Dimms, LR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_LR_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34LRDIMM[] = { - {{1, 1, 1, DDR1866_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 3, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntLRG34 = { - {PSCFG_LR_MAXFREQ, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34LRDIMM) / sizeof (PSCFG_LR_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34LRDIMM -}; - -// IBT -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, F0RC8, F1RC0, F1RC1, F1RC2 -// -STATIC CONST PSCFG_L_IBT_ENTRY OrLRDdr3IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_LR, NP, NP, 1, 1, 1, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600 + DDR1866, V1_5, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {1, DDR1600, V1_35, DIMM_LR, NP, NP, 0, 0, 0, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1066, VOLT_ALL, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_LR, NP, 0, 0, 0, 0}, - {2, DDR1600, V1_5, DIMM_LR, DIMM_LR, NP, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800 + DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_5 + V1_35, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR800, V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_5, DIMM_LR, NP + DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_LR, 0, 0, 0, 0}, - {3, DDR800, V1_25, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1066, V1_35, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1333, V1_5, DIMM_LR, DIMM_LR, DIMM_LR, 1, 1, 1, 1}, - {3, DDR1600, V1_5, DIMM_LR, NP, DIMM_LR, 1, 1, 1, 1}, -}; -CONST PSC_TBL_ENTRY IBTTblEntLRG34 = { - {PSCFG_LR_IBT, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3IBT) / sizeof (PSCFG_L_IBT_ENTRY), - (VOID *)&OrLRDdr3IBT -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3LRDdr3CLKDis[] = {0x03, 0x0C, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntLRG34 = { - {PSCFG_CLKDIS, LRDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3LRDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3LRDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0xF7} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntLRG34 = { - {PSCFG_WL_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34LRDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34LRDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_A, 0x132}, - {_1DIMM + _2DIMM + _3DIMM, CH_B, 0x122}, - {_1DIMM + _2DIMM + _3DIMM, CH_C, 0x112}, - {_1DIMM + _2DIMM + _3DIMM, CH_D, 0x102} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34 = { - {PSCFG_HWRXEN_PASS1_SEED, LRDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34LRDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34LRDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c deleted file mode 100644 index fb34f6f17f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c +++ /dev/null @@ -1,743 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpRorG3.c - * - * Platform specific settings for OR G34 DDR3 R-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 58716 $ @e \$Date: 2011-09-05 23:18:21 -0600 (Mon, 05 Sep 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "mu.h" -#include "GeneralServices.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - - -#define FILECODE PROC_MEM_PS_OR_G34_MPRORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34RDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x00222222}, - {1, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x00000000, 0x10222222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003C3C3C, 0x20112222}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, 0, 0x003C3C3C, 0x30222222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x003A3A3A, 0x30112222}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, 0, 0x003A3A3A, 0x30222222}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00393939, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x00222222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00000000, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00393C39, 0x20112222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00393C39, 0x20222222}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_35 + V1_25, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00373A37, 0x30112222}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363936, 0x30112222}, - {2, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00353935, 0x30222222}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, 0, 0x003A3C3A, 0x30222222}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0, 0x00383A38, 0x30222222}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0, 0x00373A37, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x20222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00000000, 0x10222222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00380038, 0x30112222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP, 0, 0x00390039, 0x20222222}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x30222222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A003A, 0x20222222}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00373C37, 0x20332222}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, 0, 0x00373C37, 0x30222222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00353A35, 0x30332222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00363A36, 0x30222222}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 0, 0x00363A36, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00333933, 0x30332222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00360036, 0x30112222}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, 0, 0x00383C38, 0x30222222}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00333C33, 0x30112222}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, 0, 0x00353A35, 0x30222222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0, 0x00303A30, 0x30112222}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00343934, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntRG34 = { - {PSCFG_SAO, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34RDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34RDdr3SAO -}; - -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34RDdr3S__[] = { -// DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 0}, - {1, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR + DIMM_QR, NP, NP, 0}, - {1, DDR1333, V1_25, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_5, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_35 + V1_25, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_35 + V1_25, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_5, NP, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_35, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, 0}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_5, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_35, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1066 + DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, 1}, - {3, DDR1066, V1_5, DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35 + V1_25, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_SR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR800, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntRG34 = { - {PSCFG_S__, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34RDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34RDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1RDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}, - {DIMM_QR, 0x00000000, 0x00000000, 0x00000505, 0x00000505} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntRG34 = { - {PSCFG_ODT_PAT_1D, RDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1RDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1RDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2RDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {NP, DIMM_QR, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}, - {DIMM_SR + DIMM_DR, DIMM_QR, 0x01010000, 0x01010A0A, 0x01090000, 0x01030E0B}, - {DIMM_QR, DIMM_SR + DIMM_DR, 0x00000202, 0x05050202, 0x00000206, 0x0D070203}, - {DIMM_QR, DIMM_QR, 0x05050A0A, 0x05050A0A, 0x050D0A0E, 0x05070A0B} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntRG34 = { - {PSCFG_ODT_PAT___, RDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2RDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2RDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3RDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x0000405}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000303, 0x05050606, 0x00000307, 0x0D070607}, - {NP, DIMM_QR, NP, 0x00000000, 0x00000000, 0x020A0000, 0x080A0000}, - {NP, DIMM_QR, DIMM_SR + DIMM_DR, 0x04040A0A, 0x04040000, 0x040C0A0E, 0x04060000}, - {DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, 0x05050B0B, 0x05050E0E, 0x050D0B0F, 0x05070E0F} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntRG34 = { - {PSCFG_ODT_PAT_3D, RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3RDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrG34RDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 2, 2}, - {1, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 1, 2}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, R0 + R2, 3, 2}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, R1 + R3, 0, 2}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1066, V1_35, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_35, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR, R0, 5, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 2, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, NP + DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, VOLT_ALL, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR + DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_SR + DIMM_DR + DIMM_QR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR + DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_DR + DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5 + V1_35, DIMM_SR, DIMM_SR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R0 + R2, 1, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, R1 + R3, 0, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, R0 + R2, 1, 2}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R0 + R2, 3, 2}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, R1 + R3, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 4, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntRG34 = { - {PSCFG_RTT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34RDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrG34RDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34RDIMM[] = { - {{1, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 0, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 1, 0, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 1, 1, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{2, 2, 0, 0, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 0, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 1, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 3, 0, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR800_FREQUENCY}}, - {{3, 3, 2, 1, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 2, 0, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 2, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 1, 1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 3, 0, DDR1066_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, - {{3, 3, 0, 2, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, DDR667_FREQUENCY}}, -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntRG34 = { - {PSCFG_MAXFREQ, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34RDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34RDIMM -}; - -// RC2[IBT] -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, NumOfReg, IBT -// -STATIC CONST PSCFG_MR2IBT_ENTRY OrRDdr3RC2IBT[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 1}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 0xF, 1}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1066, VOLT_ALL, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, 1, 0}, - {1, DDR1333, V1_5 + V1_35, DIMM_QR, NP, NP, DIMM_QR, 2, 1}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, 1, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, 1, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP + DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR667 + DDR800, VOLT_ALL, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1066, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, VOLT_ALL, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1066, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, 1, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, 1, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, 1, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR + DIMM_DR, 1, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_DR, NP, DIMM_DR, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_35, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1066, V1_35, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1066, V1_35 + V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1066, V1_25, DIMM_QR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_SR, DIMM_QR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_DR, DIMM_QR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR, NP, DIMM_SR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_SR + DIMM_DR + DIMM_QR, NP, DIMM_QR, 2, 8}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_DR, NP, DIMM_DR + DIMM_QR, 1, 1}, - {2, DDR1333, V1_5, DIMM_QR, DIMM_QR, NP, DIMM_QR, 1, 1}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {2, DDR1333, V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, DIMM_QR, NP, DIMM_QR, 0xF, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR667, VOLT_ALL, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR667, VOLT_ALL, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_5 + V1_35, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_SR, DIMM_QR, DIMM_DR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_5 + V1_35, DIMM_DR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, NP + DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR800, V1_25, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1066, V1_5 + V1_35, DIMM_SR, NP + DIMM_SR, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, NP + DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, NP + DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35 + V1_25, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_25, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, 1, 0}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, 1, 0}, - {3, DDR800, V1_25, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR800, V1_25, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1066, V1_5, NP + DIMM_SR, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5 + V1_35, NP, DIMM_QR, DIMM_SR + DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, NP + DIMM_DR, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_5, DIMM_SR, DIMM_QR, DIMM_SR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_5, DIMM_DR, DIMM_QR, DIMM_DR, DIMM_QR, 2, 8}, - {3, DDR1066, V1_35, NP, DIMM_QR, DIMM_SR, DIMM_SR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_35, NP, DIMM_QR, DIMM_DR, DIMM_DR + DIMM_QR, 1, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1066, V1_35, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 1, 0}, - {3, DDR1333, V1_5, NP, DIMM_QR, NP, DIMM_QR, 2, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_SR, DIMM_DR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1333, V1_5, DIMM_DR, DIMM_DR, DIMM_DR, DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, 1, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, 1, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, 1, 1}, -}; -CONST PSC_TBL_ENTRY RC2IBTTblEntRG34 = { - {PSCFG_RC2IBT, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3RC2IBT) / sizeof (PSCFG_MR2IBT_ENTRY), - (VOID *)&OrRDdr3RC2IBT -}; - -// RC10[OperatingSpeed] -// Format : -// DDRrate, Operating Speed -// -STATIC CONST PSCFG_OPSPD_ENTRY OrRDdr3OpSPD[] = { - {DDR667 + DDR800, 0}, - {DDR1066, 1}, - {DDR1333, 2}, - {DDR1600, 3}, - {DDR1866, 4} -}; -CONST PSC_TBL_ENTRY RC10OpSpdTblEntRG34 = { - {PSCFG_RC10OPSPD, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrRDdr3OpSPD) / sizeof (PSCFG_OPSPD_ENTRY), - (VOID *)&OrRDdr3OpSPD -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA Or3RDdr3CLKDis[] = {0x03, 0x0C, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntRG34 = { - {PSCFG_CLKDIS, RDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3RDdr3CLKDis) / sizeof (UINT8), - (VOID *)&Or3RDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34RDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x41} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntRG34 = { - {PSCFG_WL_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34RDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34RDIMM[] = { - {_1DIMM, CH_A, 0x43}, - {_1DIMM, CH_B, 0x3F}, - {_1DIMM, CH_C, 0x3A}, - {_1DIMM, CH_D, 0x35}, - {_2DIMM, CH_A, 0x54}, - {_2DIMM, CH_B, 0x4D}, - {_2DIMM, CH_C, 0x45}, - {_2DIMM, CH_D, 0x40}, - {_3DIMM, CH_A, 0x6B}, - {_3DIMM, CH_B, 0x5E}, - {_3DIMM, CH_C, 0x4B}, - {_3DIMM, CH_D, 0x3D} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34 = { - {PSCFG_HWRXEN_PASS1_SEED, RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34RDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34RDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c deleted file mode 100644 index fee4e786f8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c +++ /dev/null @@ -1,351 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpUorG3.c - * - * Platform specific settings for OR G34 DDR3 U-DIMM system - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps/OR/G34) - * @e \$Revision: 56269 $ @e \$Date: 2011-07-11 12:37:42 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "PlatformMemoryConfiguration.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_MEM_PS_OR_G34_MPUORG3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// Slow mode, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC -// -STATIC CONST PSCFG_SAO_ENTRY OrG34UDdr3SAO[] = { - {1, DDR667, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222}, - {1, DDR667, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222}, - {1, DDR800, VOLT_ALL, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222}, - {1, DDR800, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x003B0000, 0x10112222}, - {1, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00383837, 0x20112222}, - {1, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00363635, 0x30112222}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x00353533, 0x30112222}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003533, 0x30112222}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00333330, 0x30332222}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003330, 0x30332222}, - {2, DDR667, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222}, - {2, DDR667, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222}, - {2, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222222}, - {2, DDR800, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222}, - {2, DDR800, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x003B0000, 0x10112222}, - {2, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222222}, - {2, DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00383837, 0x20112222}, - {2, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x003A3A3A, 0x30222222}, - {2, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00363635, 0x30112222}, - {2, DDR1333, VOLT_ALL, DIMM_SR, DIMM_SR, NP, 1, 0x00003939, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003938, 0x30222222}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00353533, 0x30112222}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00003533, 0x30112222}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 1, 0x00003738, 0x30222222}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 1, 0x00003737, 0x30222222}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00003737, 0x30222222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x00332222}, - {3, DDR667, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x00332222}, - {3, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x10222222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_SR, 0, 0x00000000, 0x10332222}, - {3, DDR800, VOLT_ALL, NP, NP, DIMM_DR, 0, 0x003B0000, 0x10332222}, - {3, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x00390039, 0x20222222}, - {3, DDR1066, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00383837, 0x20332222}, - {3, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0, 0x003A3A3A, 0x30222222}, - {3, DDR1333, VOLT_ALL, NP, NP, DIMM_SR + DIMM_DR, 0, 0x00363635, 0x30332222}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, 1, 0x00003939, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003938, 0x30222222}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, 0, 0x00353533, 0x30332222}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, 1, 0x00003533, 0x30332222}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, 1, 0x00003738, 0x30222222}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, 1, 0x00003737, 0x30222222}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, 1, 0x00003737, 0x30222222}, -}; -CONST PSC_TBL_ENTRY SAOTblEntUG34 = { - {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&OrG34UDdr3SAO -}; -// training configuratrions -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D -// -STATIC CONST PSCFG_S___ENTRY OrG34UDdr3S__[] = { - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {1, DDR667 + DDR800 + DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0}, - {1, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0}, - // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_5 + V1_35, NP + DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1333, V1_25, DIMM_SR, NP, DIMM_SR, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR + DIMM_DR, 1}, - {3, DDR1600, V1_5, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 1}, - }; -CONST PSC_TBL_ENTRY S__TblEntUG34 = { - {PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrG34UDdr3S__) / sizeof (PSCFG_S___ENTRY), - (VOID *)&OrG34UDdr3S__ -}; -// ODT pattern for 1 DPC -// Format: -// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = { - {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001}, - {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401} -}; -CONST PSC_TBL_ENTRY OdtPat1DTblEntUG34 = { - {PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY), - (VOID *)&Or1UDdr3OdtPat -}; - -// ODT pattern for 2 DPC -// Format: -// Dimm0, Dimm1, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = { - {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000}, - {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000}, - {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603} -}; -CONST PSC_TBL_ENTRY OdtPat2DTblEntUG34 = { - {PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY), - (VOID *)&Or2UDdr3OdtPat -}; - -// ODT pattern for 3 DPC -// Format: -// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow -// -STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = { - {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000}, - {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405} -}; -CONST PSC_TBL_ENTRY OdtPat3DTblEntUG34 = { - {PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY), - (VOID *)&Or3UDdr3OdtPat -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -STATIC CONST PSCFG_RTT_ENTRY DramTermOrG34UDIMM[] = { - {1, DDR667 + DDR800, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0}, - {1, DDR667 + DDR800, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0}, - {1, DDR1066 + DDR1333, VOLT_ALL, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {1, DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0}, - {1, DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0}, - {2, DDR667 + DDR800, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2}, - {2, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0}, - {2, DDR1066 + DDR1333, VOLT_ALL, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1333, V1_5 + V1_35, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2}, - {2, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 5, 2}, - {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0}, - {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}, - {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 2}, - {3, DDR667 + DDR800, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 3, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR667 + DDR800 + DDR1066, VOLT_ALL, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 3, 2}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1066 + DDR1333, VOLT_ALL, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1333, VOLT_ALL, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 5, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 2}, - {3, DDR1333, V1_5 + V1_35, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 5, 2}, - {3, DDR1600, V1_5, NP, NP, DIMM_SR, DIMM_SR, R0, 0, 1}, - {3, DDR1600, V1_5, NP, NP, DIMM_DR, DIMM_DR, R0 + R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_SR, DIMM_SR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_SR, NP, DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR, DIMM_SR + DIMM_DR, R0, 4, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_SR + DIMM_DR, DIMM_DR, R1, 0, 1}, - {3, DDR1600, V1_5, DIMM_DR, NP, DIMM_DR, DIMM_DR, R0, 4, 1}, -}; -CONST PSC_TBL_ENTRY DramTermTblEntUG34 = { - {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (DramTermOrG34UDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermOrG34UDIMM -}; - -// Max Freq. -// Format : -// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V -// -STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrG34UDIMM[] = { - {{1, 1, 1, 0, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{1, 1, 0, 1, 0, DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{2, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{2, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{3, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{3, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}} -}; -CONST PSC_TBL_ENTRY MaxFreqTblEntUG34 = { - {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (MaxFreqOrG34UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY), - (VOID *)&MaxFreqOrG34UDIMM -}; - -// -// MemClkDis -// -STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x01, 0x04, 0x02, 0x18, 0x20, 0x00, 0x00, 0x00}; -CONST PSC_TBL_ENTRY ClkDisMapEntUG34 = { - {PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM + _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CLKDis) / sizeof (UINT8), - (VOID *)&OrUDdr3CLKDis -}; - -// -// WL pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrG34UDIMM[] = { - {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x0F} -}; -CONST PSC_TBL_ENTRY WLPass1SeedEntUG34 = { - {PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (WLPas1SeedOrG34UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&WLPas1SeedOrG34UDIMM -}; - -// -// HW RxEn pass1 seed -// -// Format : -// DimmPerCh in bit map, Channel #, Seed value -STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrG34UDIMM[] = { - {_1DIMM, CH_A, 0x3E}, - {_1DIMM, CH_B, 0x38}, - {_1DIMM, CH_C, 0x37}, - {_1DIMM, CH_D, 0x31}, - {_2DIMM, CH_A, 0x51}, - {_2DIMM, CH_B, 0x4A}, - {_2DIMM, CH_C, 0x46}, - {_2DIMM, CH_D, 0x3F}, - {_3DIMM, CH_A, 0x5E}, - {_3DIMM, CH_B, 0x52}, - {_3DIMM, CH_C, 0x48}, - {_3DIMM, CH_D, 0x3C} -}; -CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34 = { - {PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_G34, DDR3_TECHNOLOGY}, - sizeof (HWRxEnPas1SeedOrG34UDIMM) / sizeof (PSCFG_SEED_ENTRY), - (VOID *)&HWRxEnPas1SeedOrG34UDIMM -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc deleted file mode 100644 index 412f9dd1bd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -libagesa-y += mpor3.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c deleted file mode 100644 index f4464e938b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c +++ /dev/null @@ -1,228 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpor3.c - * - * Platform specific settings for OR - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "mport.h" -#include "ma.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "mm.h" -#include "mn.h" -#include "mp.h" -#include "Filecode.h" - -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - - -#define FILECODE PROC_MEM_PS_OR_MPOR3_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ -// -// Common tables of Orochi platform specific configuration -// - -// MR0[WR] -// Format : -// D18F2x22C_dct[1:0][Twr], MR0[WR] -// -CONST PSCFG_MR0WR_ENTRY MR0WR[] = { - {0x10, 0}, - {0x05, 1}, - {0x06, 2}, - {0x07, 3}, - {0x08, 4}, - {0x0A, 5}, - {0x0C, 6}, - {0x0E, 7} -}; -CONST PSC_TBL_ENTRY MR0WrTblEntry = { - {PSCFG_MR0WR, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (MR0WR) / sizeof (PSCFG_MR0WR_ENTRY), - (VOID *)&MR0WR -}; - -// MR0[CL] -// Format : -// D18F2x200_dct[1:0][Tcl], MR0[CL][3:1], MR0[CL][0] -// -CONST PSCFG_MR0CL_ENTRY MR0CL[] = { - {0x05, 1, 0}, - {0x06, 2, 0}, - {0x07, 3, 0}, - {0x08, 4, 0}, - {0x09, 5, 0}, - {0x0A, 6, 0}, - {0x0B, 7, 0}, - {0x0C, 0, 1}, - {0x0D, 1, 1}, - {0x0E, 2, 1}, - {0x0F, 3, 1}, - {0x10, 4, 1} -}; -CONST PSC_TBL_ENTRY MR0CLTblEntry = { - {PSCFG_MR0CL, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (MR0CL) / sizeof (PSCFG_MR0CL_ENTRY), - (VOID *)&MR0CL -}; - - -// -// CKE tri-state -// -STATIC CONST UINT8 ROMDATA OrDdr3CKETri[] = {0x55, 0xAA}; -CONST PSC_TBL_ENTRY OrDdr3CKETriEnt = { - {PSCFG_CKETRI, DT_DONT_CARE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3CKETri) / sizeof (UINT8), - (VOID *)&OrDdr3CKETri -}; - - -// -// ODT tri-state [UDIMM & RDIMM][1DPC & 2DPC] -// -// Bit 0: MEMODT[1,0][0] -// Bit 1: MEMODT[1,0][1] -// Bit 2: MEMODT[1,0][2] -// Bit 3: MEMODT[1,0][3] -// -// Dimm 0 : BP_MEMCSx[1:0], BP_MEMODTx[2, 0] -// Dimm 1 : BP_MEMCSx[3:2], BP_MEMODTx[3, 1] -STATIC CONST UINT8 ROMDATA OrDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08}; -CONST PSC_TBL_ENTRY OrDdr3ODTTriEnt = { - {PSCFG_ODTTRI, UDIMM_TYPE + RDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3ODTTri) / sizeof (UINT8), - (VOID *)&OrDdr3ODTTri -}; -// -// ODT tri-state [UDIMM & RDIMM][3DPC] -// -// Dimm 0: BP_MEMCSx[1:0], BP_MEMODTx[0] -// Dimm 1: BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// Dimm 2: BP_MEMCSx[5:4], BP_MEMODTx[2] -STATIC CONST UINT8 ROMDATA OrDdr3ODTTri3D[] = {0x03, 0x44, 0x30, 0x88}; -CONST PSC_TBL_ENTRY OrDdr3ODTTri3DEnt = { - {PSCFG_ODTTRI, UDIMM_TYPE + RDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3ODTTri3D) / sizeof (UINT8), - (VOID *)&OrDdr3ODTTri3D -}; - - -// -// ODT tri-state [LRDIMM][1DPC & 2DPC] -// -// Bit 0: MEMODT[1,0][0] -// Bit 1: MEMODT[1,0][1] -// Bit 2: MEMODT[1,0][2] -// Bit 3: MEMODT[1,0][3] -// -// Dimm 0 : BP_MEMCSx[5:4, 1:0], BP_MEMODTx[2, 0] -// Dimm 1 : BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// LR : Assert DIMM ODT0 only -STATIC CONST UINT8 ROMDATA OrLRDdr3ODTTri[] = {0x03, 0x0C, 0x00, 0x00}; -CONST PSC_TBL_ENTRY OrLRDdr3ODTTriEnt = { - {PSCFG_ODTTRI, LRDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3ODTTri) / sizeof (UINT8), - (VOID *)&OrLRDdr3ODTTri -}; - -// -// ODT tri-state [LRDIMM][3DPC] -// -// Dimm 0: BP_MEMCSx[1:0], BP_MEMODTx[0] -// Dimm 1: BP_MEMCSx[7:6, 3:2], BP_MEMODTx[3, 1] -// Dimm 2: BP_MEMCSx[5:4], BP_MEMODTx[2] -// LR : Assert DIMM ODT0 only -STATIC CONST UINT8 ROMDATA OrLRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC0}; -CONST PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt = { - {PSCFG_ODTTRI, LRDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrLRDdr3ODTTri3D) / sizeof (UINT8), - (VOID *)&OrLRDdr3ODTTri3D -}; - -// -// ChipSel tri-state [UDIMM] -// -STATIC CONST UINT8 ROMDATA OrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80}; -CONST PSC_TBL_ENTRY OrUDdr3CSTriEnt = { - {PSCFG_CSTRI, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrUDdr3CSTri) / sizeof (UINT8), - (VOID *)&OrUDdr3CSTri -}; -// -// ChipSel tri-state [RDIMM & LRDIMM] -// BIOS must not tri-state chip select pin corresponding to the second chip -// select of a single rank registered dimm -STATIC CONST UINT8 ROMDATA OrDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0}; -CONST PSC_TBL_ENTRY OrDdr3CSTriEnt = { - {PSCFG_CSTRI, LRDIMM_TYPE + RDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (OrDdr3CSTri) / sizeof (UINT8), - (VOID *)&OrDdr3CSTri -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c deleted file mode 100644 index 92250693ef..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c +++ /dev/null @@ -1,1225 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mp.c - * - * Common platform specific configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 55046 $ @e \$Date: 2011-06-15 23:59:07 -0600 (Wed, 15 Jun 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MP_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define PSO_TYPE 0 -#define PSO_LENGTH 1 -#define PSO_DATA 2 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfig ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfigSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -VOID -STATIC -MemPTblDrvOverrideSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -UINT8 -STATIC -MemPTblDrvOverrideODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -VOID -STATIC -MemPTblDrvOverrideODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -UINT8 -STATIC -MemPTblDrvOverrideRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer, - IN UINT8 NumOfReg - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR0WR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR0CL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -BOOLEAN -STATIC -MemPTblDrvOverrideMR10OpSpeed ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * This is the default return function of the Platform Specific block. The function always - * returns AGESA_UNSUPPORTED - * - * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE - * @param[in] *ChannelPtr Pointer to CH_DEF_STRUCT - * @param[in] *PsPtr Pointer to MEM_PS_BLOCK - * - * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported - * - */ - -AGESA_STATUS -MemPConstructPsUDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT CH_DEF_STRUCT *ChannelPtr, - IN OUT MEM_PS_BLOCK *PsPtr - ) -{ - return AGESA_UNSUPPORTED; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function will set the DramTerm and DramTermDyn in the structure of a channel. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] ArraySize Size of the array of DramTerm - * @param[in] *DramTermPtr Address the array of DramTerm - * - * @return TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population. - * @return FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population. - * - */ -BOOLEAN -MemPGetDramTerm ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 ArraySize, - IN CONST DRAM_TERM_ENTRY *DramTermPtr - ) -{ - UINT8 Dimms; - UINT8 QR_Dimms; - UINT8 i; - Dimms = NBPtr->ChannelPtr->Dimms; - QR_Dimms = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) { - if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) { - QR_Dimms ++; - } - } - - for (i = 0; i < ArraySize; i ++) { - if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) { - if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) { - if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) || - ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) || - (DramTermPtr[i].QR_Dimms == ANY_NUM)) { - NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm; - NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm; - NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm; - break; - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the highest POR supported speed. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * @param[in] FreqLimitSize Size of the array of Frequency Limit - * @param[in] *FreqLimitPtr Address the array of Frequency Limit - * - * @return UINT8 - frequency limit - * - */ -UINT16 -MemPGetPorFreqLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 FreqLimitSize, - IN CONST POR_SPEED_LIMIT *FreqLimitPtr - ) -{ - UINT8 i; - UINT8 j; - UINT8 DimmTpMatch; - UINT16 SpeedLimit; - UINT16 DIMMRankType; - UINT16 _DIMMRankType; - - SpeedLimit = 0; - DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr); - for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) { - if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) { - continue; - } - DimmTpMatch = 0; - _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType; - for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) { - if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) { - DimmTpMatch++; - } - } - if (DimmTpMatch == FreqLimitPtr->Dimms) { - if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V; - break; - } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V; - break; - } else { - SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V; - break; - } - } - } - - return SpeedLimit; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function is the default function for getting POR speed limit. When a - * package does not need to cap the speed, it should use this function to initialize - * the corresponding function pointer. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - */ -VOID -MemPGetPORFreqLimitDef ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets the seed value of WL and HW RxEn pass 1 training. - * - * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK - * - * @return TRUE - Entries are found - * @return FALSE - Entries are not found - * - */ -BOOLEAN -MemPGetPSCPass1Seed ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - UINT8 Dct; - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if (!(memPlatSpecFlowArray[i])->TrainingSeedVal (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - return FALSE; - } - i++; - } - } - - return TRUE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term, - * and so on. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Successfully execute platform specific configuration flow. - * @return FALSE - Fail to execute platform specific configuration flow. - * - */ -BOOLEAN -MemPPSCFlow ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 i; - BOOLEAN Result; - - Result = TRUE; - i = 0; - while (memPlatSpecFlowArray[i] != NULL) { - if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) { - break; - } - } - } - } - } - } - } - } - } - } - i++; - } - - IDS_SKIP_HOOK (IDS_ENFORCE_PLAT_TABLES, NBPtr, &(NBPtr->MemPtr->StdHeader)) { - if (memPlatSpecFlowArray[i] == NULL) { - Result = FALSE; - } - } - return Result; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number - * of dimm in the table. - * - * @param[in] Dimm0 Rank type of Dimm0 - * @param[in] Dimm1 Rank type of Dimm1 - * @param[in] Dimm2 Rank type of Dimm2 - * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable - * - * - */ -VOID -MemPConstructRankTypeMap ( - IN UINT16 Dimm0, - IN UINT16 Dimm1, - IN UINT16 Dimm2, - IN OUT UINT16 *RankTypeInTable - ) -{ - UINT8 i; - UINT16 RT; - UINT8 BitShift; - - *RankTypeInTable = 0; - RT = 0; - BitShift = 0; - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - switch (i) { - case 0: - RT = (Dimm0 == 0) ? NP : Dimm0; - BitShift = 0; - break; - case 1: - RT = (Dimm1 == 0) ? NP : Dimm1; - BitShift = 4; - break; - case 2: - RT = (Dimm2 == 0) ? NP : Dimm2; - BitShift = 8; - break; - default: - // dimm3 is not used, fills nibble3 with "NP" - RT = NP; - BitShift = 12; - } - *RankTypeInTable |= RT << BitShift; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * MemPIsIdSupported - * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to - * determine if it is supported by this NB type. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] LogicalId - CPU_LOGICAL_ID - * @param[in] PackageType - Package Type - * - * @return TRUE - NB type is matched ! - * @return FALSE - NB type is not matched ! - * - */ -BOOLEAN -MemPIsIdSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID LogicalId, - IN UINT8 PackageType - ) -{ - CPUID_DATA CpuId; - UINT8 PkgType; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader)); - PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - - if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0) - && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) { - if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) { - return TRUE; - } - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function returns the rank type map of a channel. - * - * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT - * - * @return UINT16 - The map of rank type. - * - */ -UINT16 -MemPGetPsRankType ( - IN CH_DEF_STRUCT *CurrentChannel - ) -{ - UINT8 i; - UINT16 DIMMRankType; - - DIMMRankType = 0; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if (CurrentChannel->MCTPtr->Status[SbLrdimms]) { - // For LrDimm, we construct the map according to Dimm present bits rather than rank type bits - if ((CurrentChannel->LrDimmPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_LR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } else { - if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) { - if (i < 2) { - DIMMRankType |= (UINT16) DIMM_QR << (i << 2); - } - } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_DR << (i << 2); - } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) { - DIMMRankType |= (UINT16) DIMM_SR << (i << 2); - } else { - DIMMRankType |= (UINT16) NP << (i << 2); - } - } - } - - return DIMMRankType; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function performs the action for the rest of platform specific configuration such as - * tri-state stuff - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - No error occurred. - * @return FALSE - Error occurred. - * - */ -BOOLEAN -STATIC -MemPPSCGen ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - PSCFG_TYPE PSCType; - DIMM_TYPE DimmType; - UINT8 MaxDimmPerCh; - UINT8 NOD; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - CH_DEF_STRUCT *CurrentChannel; - UINT32 EventInfo; - - CurrentChannel = NBPtr->ChannelPtr; - - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) { - i = 0; - while (EntryOfTables->TblEntryOfGen[i] != NULL) { - if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - break; - } - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfGen[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s Table\n", (PSCType == PSCFG_CLKDIS) ? "ClkDis" : ((PSCType == PSCFG_CKETRI) ? "CkeTri" : ((PSCType == PSCFG_ODTTRI) ? "OdtTri" : "CsTri"))); - EventInfo = (PSCType == PSCFG_CLKDIS) ? MEM_ERROR_CLK_DIS_MAP_NOT_FOUND : ((PSCType == PSCFG_CKETRI) ? MEM_ERROR_CKE_TRI_MAP_NOT_FOUND : ((PSCType == PSCFG_ODTTRI) ? MEM_ERROR_ODT_TRI_MAP_NOT_FOUND : MEM_ERROR_CS_TRI_MAP_NOT_FOUND)); - PutEventLog (AGESA_ERROR, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - // Perform the action for specific PSCType. - if (PSCType == PSCFG_CLKDIS) { - CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CKETRI) { - CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_ODTTRI) { - CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } else if (PSCType == PSCFG_CSTRI) { - CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr; - } - } - - CurrentChannel->DctEccDqsLike = 0x0403; - CurrentChannel->DctEccDqsScale = 0x70; - - return TRUE; -} - - - /* -----------------------------------------------------------------------------*/ -/** - * - * This function proceeds Table Driven Overriding. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table - * @param[in] ProceededPSOType - Proceeded PSO type - * - * @return bit0 ~ bit7 - Overriding CS or DIMM map. - * @return bit15 - Invalid entry found if set. - * - */ -UINT16 -MemPProceedTblDrvOverride ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN PSO_TABLE *PlatformMemoryConfiguration, - IN UINT8 ProceededPSOType - ) -{ - UINT8 *Buffer; - UINT8 *PSOStartPtr; - UINT8 NumOfReg; - UINT8 RetVal; - UINT16 RetVal16; - BOOLEAN ConfigMatched; - BOOLEAN FirstGoThrough; - BOOLEAN FindNewConfig; - BOOLEAN InvertRetVal; - BOOLEAN InvalidConfigDetected; - - - ASSERT (PlatformMemoryConfiguration != NULL); - ASSERT ((ProceededPSOType >= PSO_TBLDRV_START) && (ProceededPSOType <= PSO_TBLDRV_END)); - - NumOfReg = 0; - RetVal = 0; - RetVal16 = 0; - FirstGoThrough = TRUE; - InvertRetVal = FALSE; - InvalidConfigDetected = FALSE; - // - // << P E R S P E C T I V E >> - // - // PlatformMemoryConfiguration [] = { - // . . . . . . . . . . . . . . . . . . . - // . . . . . . . . . . . . . . . . . . . - // TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1600, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1), - // TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 2), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS2_, 2), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS3_, 1), - // TBLDRV_CONFIG_ENTRY_ADDRTMG (0x003C3C3C), - // TBLDRV_CONFIG_ENTRY_ODCCTRL (0x20112222), - // - // TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE (2, 2, 0, 0) - // TBLDRV_CONFIG_ENTRY_SPEEDLIMIT (DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY), - // - // TBLDRV_CONFIG_TO_OVERRIDE (2, DDR1333, VOLT1_5_ + VOLT1_35_, SR_DIMM0 + DR_DIMM1), - // TBLDRV_CONFIG_ENTRY_RTTNOM (CS2_ + CS3_, 3), - // TBLDRV_CONFIG_ENTRY_RTTWR (CS2_ + CS3_, 0), - // - // TBLDRV_OVERRIDE_MR0_WR (3, 5) - // TBLDRV_OVERRIDE_MR0_WR (4, 6) - // - // TBLDRV_OVERRIDE_MR0_CL (3, 5) - // TBLDRV_OVERRIDE_MR0_CL (4, 6) - // . . . . . . . . . . . . . . . . . . . - // . . . . . . . . . . . . . . . . . . . - // - // PSO_END - // } - // - Buffer = PlatformMemoryConfiguration; - // Look for configuration descriptor and its sub-descriptor. - while (Buffer[PSO_TYPE] != PSO_END) { - FindNewConfig = FALSE; - ConfigMatched = FALSE; - if (Buffer[PSO_TYPE] == PSO_TBLDRV_CONFIG) { - // - // Config. descriptor is found, check its sub-descriptor to execute different checking routine. - // - if ((Buffer[PSO_DATA] == CONFIG_SPEEDLIMIT) && (ProceededPSOType == PSO_TBLDRV_SPEEDLIMIT)) { - if (MemPCheckTblDrvOverrideConfigSpeedLimit (NBPtr, &Buffer[PSO_DATA + 1])) { - ConfigMatched = TRUE; - } - } else if (Buffer[PSO_DATA] == CONFIG_DONT_CARE) { - ConfigMatched = TRUE; - } else { - if (MemPCheckTblDrvOverrideConfig (NBPtr, &Buffer[PSO_DATA + 1])) { - ConfigMatched = TRUE; - if ((Buffer[PSO_DATA] == CONFIG_RC2IBT) && (ProceededPSOType == PSO_TBLDRV_RC2_IBT)) { - NumOfReg = Buffer[PSO_DATA + 9]; - } - } - } - } - - if (ConfigMatched) { - // - // If config. is matched, parsing "Table Driven PSO" macros behinds this config. macro until PSO_END is reached. - // - PSOStartPtr = Buffer + (Buffer[PSO_LENGTH] + 2); - // Look for the current proceeded PSO type in PlatformMemoryConfiguration array. - while ((PSOStartPtr[PSO_TYPE] != PSO_END)) { - if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_CONFIG) { - // - // If there is an additional config. macro existed, break this while loop, - // then check its content with real platform config. again. - // If matched, parsing "Table Driven PSO" macros behind it. - // - Buffer = PSOStartPtr; - FindNewConfig = TRUE; - break; - } else if (PSOStartPtr[PSO_TYPE] == PSO_TBLDRV_INVALID_TYPE) { - InvalidConfigDetected = TRUE; - break; - } - - if (PSOStartPtr[PSO_TYPE] == ProceededPSOType) { - // - // Pre-set overriding Cs/Dimm map to "0xFF" for the types which are regardless of Cs/Dimm - // for the first time going through the overriding routines. - // - if (FirstGoThrough) { - RetVal = 0xFF; - } - switch (ProceededPSOType) { - case PSO_TBLDRV_SPEEDLIMIT : - MemPTblDrvOverrideSpeedLimit (NBPtr, &PSOStartPtr[PSO_DATA]); - break; - - case PSO_TBLDRV_ODT_RTTNOM : - case PSO_TBLDRV_ODT_RTTWR : - // Mask off Cs overridng map to record which Cs has been overridden. - RetVal &= ~ MemPTblDrvOverrideODT (NBPtr, &PSOStartPtr[PSO_TYPE]); - // Indicate RetVal is inverted. - InvertRetVal = TRUE; - break; - - case PSO_TBLDRV_ODTPATTERN : - MemPTblDrvOverrideODTPattern (NBPtr, &PSOStartPtr[PSO_DATA]); - break; - - case PSO_TBLDRV_ADDRTMG : - NBPtr->ChannelPtr->DctAddrTmg = *(UINT32 *)&PSOStartPtr[PSO_DATA]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: AddrTmg = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_ODCCTRL : - NBPtr->ChannelPtr->DctOdcCtl = *(UINT32 *)&PSOStartPtr[PSO_DATA]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: OdcCtl = 0x%x for Dct%d\n\n", *(UINT32 *)&PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_SLOWACCMODE : - NBPtr->ChannelPtr->SlowMode = (PSOStartPtr[PSO_DATA] == 1) ? TRUE : FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Slow Access Mode = %d for Dct%d\n\n", PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - case PSO_TBLDRV_RC2_IBT : - // Mask off Dimm overridng map to record which Dimm has been overridden. - RetVal &= ~ MemPTblDrvOverrideRC2IBT (NBPtr, &PSOStartPtr[PSO_DATA], NumOfReg); - // Indicate RetVal is inverted. - InvertRetVal = TRUE; - break; - - case PSO_TBLDRV_MR0_CL : - RetVal = 0; - if (MemPTblDrvOverrideMR0WR (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_MR0_WR : - RetVal = 0; - if (MemPTblDrvOverrideMR0CL (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_RC10_OPSPEED : - RetVal = 0; - if (MemPTblDrvOverrideMR10OpSpeed (NBPtr, &PSOStartPtr[PSO_DATA])) { - RetVal = 0xFF; - } - break; - - case PSO_TBLDRV_LRDIMM_IBT : - NBPtr->PsPtr->F0RC8 = PSOStartPtr[PSO_DATA]; - NBPtr->PsPtr->F1RC0 = PSOStartPtr[PSO_DATA + 1]; - NBPtr->PsPtr->F1RC1 = PSOStartPtr[PSO_DATA + 2]; - NBPtr->PsPtr->F1RC2 = PSOStartPtr[PSO_DATA + 3]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: LRDIMM IBT for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\nF0RC8 = %d, F1RC0 = %d, F1RC1 = %d, F1RC2 = %d", PSOStartPtr[PSO_DATA], PSOStartPtr[PSO_DATA + 1], \ - PSOStartPtr[PSO_DATA + 2], PSOStartPtr[PSO_DATA + 3]); - break; - - case PSO_TBLDRV____TRAINING : - RetVal = 0x1; - NBPtr->Override__Training = (PSOStartPtr[PSO_DATA] == 1) ? TRUE : FALSE; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Training = %d for Dct%d\n\n", PSOStartPtr[PSO_DATA], NBPtr->Dct); - break; - - default: - ASSERT (FALSE); - } - FirstGoThrough = FALSE; - } - PSOStartPtr += (PSOStartPtr[PSO_LENGTH] + 2); - } - - if (FindNewConfig) { - continue; - } - RetVal = (InvertRetVal) ? ~RetVal : RetVal; - RetVal16 = (UINT16) RetVal; - if (InvalidConfigDetected) { - RetVal16 |= INVALID_CONFIG_FLAG; - } - - return RetVal16; - } - Buffer += (Buffer[PSO_LENGTH] + 2); - } - - RetVal = (InvertRetVal) ? ~RetVal : RetVal; - RetVal16 = (UINT16) RetVal; - if (InvalidConfigDetected) { - RetVal16 |= INVALID_CONFIG_FLAG; - } - return RetVal16; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the speed limit. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - */ -VOID -STATIC -MemPTblDrvOverrideSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 CurrentVoltage; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: Max. Memory Speed for Dct%d\n", NBPtr->Dct); - - LibAmdMemCopy (NBPtr->PsPtr->SpeedLimit, Buffer, 6, &(NBPtr->MemPtr->StdHeader)); - - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz\t", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), NBPtr->PsPtr->SpeedLimit[CurrentVoltage]); - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the ODTs (RttNom and RttWr). - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return Target CS overriding bit map - * - */ -UINT8 -STATIC -MemPTblDrvOverrideODT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT16 i; - UINT8 TgtCS; - - IDS_HDT_CONSOLE_DEBUG_CODE ( - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT for Dct%d\n", NBPtr->Dct); - if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) { - IDS_HDT_CONSOLE (MEM_FLOW, "RttNom = %d for ", Buffer[3]); - } else { - IDS_HDT_CONSOLE (MEM_FLOW, "RttWr = %d for ", Buffer[3]); - } - ); - - TgtCS = Buffer[2]; - for (i = 0; i < MAX_CS_PER_CHANNEL; i++) { - if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << i)) != 0) { - if ((TgtCS & (UINT8) 1 << i) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "CS%d ", i); - if (Buffer[0] == PSO_TBLDRV_ODT_RTTNOM) { - NBPtr->PsPtr->RttNom[i] = Buffer[3]; - } else { - NBPtr->PsPtr->RttWr[i] = Buffer[3]; - } - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - return TgtCS; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the ODT patterns. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - */ -VOID -STATIC -MemPTblDrvOverrideODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: ODT pattern for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[0]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nRODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[4]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSHigh = 0x%x\n", *(UINT32 *)&Buffer[8]); - IDS_HDT_CONSOLE (MEM_FLOW, "\nWODTCSLow = 0x%x\n", *(UINT32 *)&Buffer[12]); - - CurrentChannel->PhyRODTCSHigh = *(UINT32 *)&Buffer[0]; - CurrentChannel->PhyRODTCSLow = *(UINT32 *)&Buffer[4]; - CurrentChannel->PhyWODTCSHigh = *(UINT32 *)&Buffer[8]; - CurrentChannel->PhyWODTCSLow = *(UINT32 *)&Buffer[12]; - - //WL ODTs need to be modified as well while overriding... - CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F); - CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow >> 16) & 0x0F); - CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F); - CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F); - - IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides the Ctrl Word 2 and 8. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * @param[in] NumOfReg - Number of registers - * - * @return Target DIMM overridng bit map - * - */ -UINT8 -STATIC -MemPTblDrvOverrideRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer, - IN UINT8 NumOfReg - ) -{ - UINT16 i; - UINT8 TgtDimm; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: RC2[IBT] for Dct%d\n", NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "RC2[IBT] = %d for ", Buffer[1]); - - TgtDimm = Buffer[0]; - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->ChDimmValid & (UINT16) (1 << i)) != 0) { - if (((TgtDimm & (UINT8) 1 << i) != 0) && (NBPtr->PsPtr->NumOfReg[i] == NumOfReg)) { - IDS_HDT_CONSOLE (MEM_FLOW, "DIMM%d ", i); - CurrentChannel->CtrlWrd02[i] = (Buffer[1] & 0x1) << 2; - CurrentChannel->CtrlWrd08[i] = (Buffer[1] & 0xE) >> 1; - } - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - - return TgtDimm; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR0[WR]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR0WR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTcl)) { - NBPtr->PsPtr->MR0CL31 = Buffer[1]; - NBPtr->PsPtr->MR0CL0 = Buffer[2]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[CL][3:1] = %d,\tMR0[CL][0] = %d for Dct%d\n", \ - Buffer[1], Buffer[2], NBPtr->Channel); - IDS_HDT_CONSOLE (MEM_FLOW, "Tcl = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTcl)); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR0[WR]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR0CL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - if (Buffer[0] == (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3)) { - NBPtr->PsPtr->MR0WR = Buffer[1]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR0[WR] = %d for Dct%d\n", Buffer[1], NBPtr->Dct); - IDS_HDT_CONSOLE (MEM_FLOW, "Twr = %d\n\n", (UINT8) NBPtr->GetBitField (NBPtr, BFTwrDDR3)); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function overrides MR10[OperatingSpeed]. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Overridden - * @return FALSE : Not overriden - * - */ -BOOLEAN -STATIC -MemPTblDrvOverrideMR10OpSpeed ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT32 CurDDRrate; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - - if ((Buffer[0] & CurDDRrate) != 0) { - NBPtr->PsPtr->RC10OpSpd = Buffer[1]; - IDS_HDT_CONSOLE (MEM_FLOW, "\nTable Driven Platform Override: MR10[OperatingSpeed] = %d for Dct%d\n", Buffer[1], NBPtr->Dct); - return TRUE; - } - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks if platform configuration is matched or not. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Configuration is matched - * @return FALSE : Configuration is not matched - * - */ -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfig ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 MaxDimmPerCh; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - // Get platform configuration. - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemAGetPsRankType (CurrentChannel); - - if ((MaxDimmPerCh == Buffer[0]) && ((DDR3Voltage & Buffer[1]) != 0) && - ((CurDDRrate & *(UINT32 *)&Buffer[2]) != 0) && ((RankTypeOfPopulatedDimm & *(UINT16 *)&Buffer[6]) != 0)) { - return TRUE; - } - - return FALSE; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function checks if platform configuration is matched or not. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *Buffer - Pointer to Platform config table - * - * @return TRUE : Configuration is matched - * @return FALSE : Configuration is not matched - * - */ -BOOLEAN -STATIC -MemPCheckTblDrvOverrideConfigSpeedLimit ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 *Buffer - ) -{ - UINT8 MaxDimmPerCh; - UINT8 NumOfSR; - UINT8 NumOfDR; - UINT8 NumOfQR; - UINT8 NumOfLRDimm; - UINT8 i; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - NumOfSR = 0; - NumOfDR = 0; - NumOfQR = 0; - NumOfLRDimm = 0; - - // Get platform configuration. - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { - NumOfSR += 1; - } else if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { - NumOfDR += 1; - } else if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { - if (i < 2) { - NumOfQR += 1; - } - } else if ((CurrentChannel->LrDimmPresent & (UINT16) (1 << i))) { - NumOfLRDimm += 1; - } - } - - if ((Buffer[0] == MaxDimmPerCh) && (Buffer[1] == CurrentChannel->Dimms)) { - if (NBPtr->MCTPtr->Status[SbLrdimms] == TRUE) { - if (Buffer[5] == NumOfLRDimm) { - return TRUE; - } - } else { - if ((Buffer[2] == NumOfSR) && (Buffer[3] == NumOfDR) && (Buffer[4] == NumOfQR)) { - return TRUE; - } - } - } - - return FALSE; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c deleted file mode 100644 index a8e43e3d26..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c +++ /dev/null @@ -1,206 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplribt.c - * - * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRIBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - UINT8 PsoMaskLRIBT; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_L_IBT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->LrDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8; - NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0; - NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1; - NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2; - break; - } - } - } - } - TblPtr++; - } - // - // If there is no entry, check if overriding value existed. If not, return FALSE - // - PsoMaskLRIBT = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_LRDIMM_IBT); - if ((PsoMaskLRIBT == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_LR_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c deleted file mode 100644 index ed14c165f1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnlr.c - * - * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNLR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c deleted file mode 100644 index bef6eba0f4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mplrnpr.c - * - * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input - * table and stores extracted value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetLRNPR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - return TRUE; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c deleted file mode 100644 index 4c93c10ebf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c +++ /dev/null @@ -1,303 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmaxfreq.c - * - * A sub-engine which extracts max. frequency limit value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52790 $ @e \$Date: 2011-05-11 15:31:24 -0600 (Wed, 11 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 SR:3; - UINT16 DR:3; - UINT16 QR:4; -} CDNMaxFreq; - -typedef struct { - UINT16 DimmPerCh:3; - UINT16 Dimms:3; - UINT16 LR:10; -} CDNLMaxFreq; -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts the value of max frequency supported from a input table and - * compares it with DCTPtr->Timings.TargetSpeed - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMaxFreqSupported ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - PSCFG_TYPE Type; - UINT16 CDN; - UINT16 MaxFreqSupported; - UINT16 *SpeedArray; - UINT8 DDR3Voltage; - UINT8 CurrentVoltage; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_MAXFREQ_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - BOOLEAN DisDct; - UINT8 PsoMaskMaxFreq; - UINT16 PsoMaskMaxFreq16; - PSC_TBL_ENTRY **TblEntryOfMaxFreq; - - CurrentChannel = NBPtr->ChannelPtr; - - DisDct = FALSE; - Type = PSCFG_MAXFREQ; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - SpeedArray = NULL; - - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - TblEntryOfMaxFreq = EntryOfTables->TblEntryOfMaxFreq; - IDS_OPTION_HOOK (IDS_GET_STRETCH_FREQUENCY_LIMIT, &TblEntryOfMaxFreq, &NBPtr->MemPtr->StdHeader); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (TblEntryOfMaxFreq[i] != NULL) { - if (((TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) { - if (((TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (TblEntryOfMaxFreq[i])->Header.LogicalCpuid; - PackageType = (TblEntryOfMaxFreq[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((TblEntryOfMaxFreq[i])->TBLPtr); - TableSize = (TblEntryOfMaxFreq[i])->TableSize; - Type = (TblEntryOfMaxFreq[i])->Header.PSCType; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (TblEntryOfMaxFreq[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No MaxFreq table. This channel will be disabled.\n", NBPtr->Dct); - return FALSE; - } - - MaxFreqSupported = UNSUPPORTED_DDR_FREQUENCY; - CDN = 0; - DDR3Voltage = (UINT8) CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage); - - // Construct the condition value - ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh; - ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms; - if (Type == PSCFG_MAXFREQ) { - for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) { - if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->SR += 1; - } - if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) { - ((CDNMaxFreq *)&CDN)->DR += 1; - } - if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) { - if (i < 2) { - ((CDNMaxFreq *)&CDN)->QR += 1; - } - } - } - } else { - ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms; - } - - for (i = 0; i < TableSize; i++) { - if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN : - ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) { - if (Type == PSCFG_MAXFREQ) { - SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed; - } else { - SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed; - } - break; - } - TblPtr++; - } - - PsoMaskMaxFreq16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SPEEDLIMIT); - if ((PsoMaskMaxFreq16 & INVALID_CONFIG_FLAG) == 0) { - PsoMaskMaxFreq = (UINT8) PsoMaskMaxFreq16; - if (PsoMaskMaxFreq != 0) { - SpeedArray = NBPtr->PsPtr->SpeedLimit; - } - } else { - SpeedArray = NULL; - } - - if (SpeedArray != NULL) { - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nCheck speed supported for each VDDIO for Node%d DCT%d: ", NBPtr->Node, NBPtr->Dct); - for (CurrentVoltage = VOLT1_5_ENCODED_VAL; CurrentVoltage <= VOLT1_25_ENCODED_VAL; CurrentVoltage ++) { - if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) { - IDS_HDT_CONSOLE (MEM_FLOW, "%s -> %dMHz ", (CurrentVoltage == VOLT1_5_ENCODED_VAL) ? "1.5V" : ((CurrentVoltage == VOLT1_35_ENCODED_VAL) ? "1.35V" : "1.25V"), SpeedArray[CurrentVoltage]); - if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) { - MaxFreqSupported = SpeedArray[CurrentVoltage]; - } else { - MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed; - } - if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported; - } - } else { - NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0; - } - } - IDS_HDT_CONSOLE (MEM_FLOW, "\n"); - } - ASSERT (DDR3Voltage <= VOLT1_25_ENCODED_VAL); - MaxFreqSupported = SpeedArray[DDR3Voltage]; - } - - if (MaxFreqSupported == UNSUPPORTED_DDR_FREQUENCY) { - // No entry in the table for current dimm population is found - IDS_HDT_CONSOLE (MEM_FLOW, "\nDCT %d: No entry is found in the Max Frequency table\n", NBPtr->Dct); - DisDct = TRUE; - } else if (MaxFreqSupported != 0) { - if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) { - NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported; - } - } else if (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED) { - // Dimm population is not supported at current voltage - // Also if there is no performance optimization, disable the DCT - DisDct = TRUE; - } - - if (DisDct) { - NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid; - PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - // Change target speed to highest value so it won't affect other channels when leveling frequency across the node. - NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY; - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c deleted file mode 100644 index 1e1d5dfd29..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c +++ /dev/null @@ -1,194 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpmr0.c - * - * A sub-engine which extracts MR0[WR] and MR0[CL] value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * - **/ -/***************************************************************************** -* - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPMR0_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetMR0WrCL ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 j; - UINT8 p; - UINT32 Value32; - UINT8 TableSize; - PSCFG_TYPE Type; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 PsoMaskMR0; - PSCFG_MR0CL_ENTRY *TblPtr; - PSC_TBL_ENTRY **ptr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - TblPtr = NULL; - TableSize = 0; - PsoMaskMR0 = 0; - - // Extract MR0[WR] value, then MR0[CL] value - for (i = 0; i < 2; i++) { - if (i == 0) { - ptr = EntryOfTables->TblEntryOfMR0WR; - Type = PSCFG_MR0WR; - } else { - ptr = EntryOfTables->TblEntryOfMR0CL; - Type = PSCFG_MR0CL; - } - - p = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (ptr[p] != NULL) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (ptr[p])->Header.LogicalCpuid; - PackageType = (ptr[p])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr); - TableSize = (ptr[p])->TableSize; - break; - } - p++; - } - - // Check whether no table entry is found. - if (ptr[p] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n"); - return FALSE; - } - - Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl); - for (j = 0; j < TableSize; j++, TblPtr++) { - if (Value32 == (UINT32) TblPtr->Timing) { - if (Type == PSCFG_MR0WR) { - NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value; - break; - } else { - NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value; - NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1; - break; - } - } - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE. - // - PsoMaskMR0 = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, ((i == 0) ? PSO_TBLDRV_MR0_WR : PSO_TBLDRV_MR0_CL)); - if ((PsoMaskMR0 == 0) && (j == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, (i == 0) ? "\nNo MR0[WR] entries\n" : "\nNo MR0[CL] entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_MR0_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c deleted file mode 100644 index ec0017749d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpodtpat.c - * - * A sub-engine which extracts ODT pattern value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts ODT Pattern value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetODTPattern ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT16 RankTypeInTable; - UINT16 RankTypeOfPopulatedDimm; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - DIMM_TYPE DimmType; - UINT8 PsoMaskOdtPat; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_3D_ODTPAT_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n"); - return FALSE; - } - - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh; - CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow; - CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh; - CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow; - - //WL ODT - CurrentChannel->PhyWLODT[0] = (UINT8) (CurrentChannel->PhyWODTCSLow & 0x0F); - CurrentChannel->PhyWLODT[1] = (UINT8) ((CurrentChannel->PhyWODTCSLow >> 16) & 0x0F); - CurrentChannel->PhyWLODT[2] = (UINT8) (CurrentChannel->PhyWODTCSHigh & 0x0F); - CurrentChannel->PhyWLODT[3] = (UINT8) ((CurrentChannel->PhyWODTCSHigh >> 16) & 0x0F); - - break; - } - TblPtr++; - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE - // - PsoMaskOdtPat = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODTPATTERN); - if ((PsoMaskOdtPat == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_ODT_PATTERN_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c deleted file mode 100644 index 662e99e7b3..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc10opspd.c - * - * A sub-engine which extracts RC10 operating speed value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC10 operating speed value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Succeed in extracting the table value - * @return FALSE - Fail to extract the table value - * - */ -BOOLEAN -MemPGetRC10OpSpd ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 TableSize; - UINT32 CurDDRrate; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 PsoMaskRC10OpSpeed; - PSCFG_OPSPD_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize; - break; - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - - for (i = 0; i < TableSize; i++) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD; - break; - } - TblPtr++; - } - - // - // If there is no entry, check if overriding value existed. If not, return FALSE. - // - PsoMaskRC10OpSpeed = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC10_OPSPEED); - if ((PsoMaskRC10OpSpeed == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RC10_OP_SPEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - - return TRUE; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c deleted file mode 100644 index ee6771057d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprc2ibt.c - * - * A sub-engine which extracts RC2[IBT] value for RDIMM configuration. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52114 $ @e \$Date: 2011-05-02 13:21:20 -0600 (Mon, 02 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RC2[IBT] value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRC2IBT ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 DimmIndex; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 NumOfReg; - UINT8 PsoDimmMaskRc2Ibt; - UINT8 NoEntryDimmMask; - PSCFG_MR2IBT_ENTRY *TblPtr; - PSCFG_MR2IBT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - if (CurrentChannel->RegDimmPresent == 0) { - return TRUE; - } - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - NoEntryDimmMask = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type. - while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) { - if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) { - LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType; - // - // Determine if this is the expected NB Type - // - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) { - TblPtr = OrgTblPtr; - NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex]; - if ((CurrentChannel->ChDimmValid & (UINT8) (1 << DimmIndex)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_QR; - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) { - TgtDimmType = DIMM_DR; - } else { - TgtDimmType = DIMM_SR; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if ((TblPtr->Dimm & TgtDimmType) != 0) { - // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM - if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) { - CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2); - CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1); - break; - } - } - } - } - } - } - TblPtr++; - } - - if (i == TableSize) { - NoEntryDimmMask |= (UINT8) 1 << DimmIndex; - } - } - } - - // - // If there are no entries for certain Dimm(s), check if overriding value existed for them. If not, return FALSE. - // - PsoDimmMaskRc2Ibt = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_RC2_IBT); - if (NoEntryDimmMask != 0) { - if ((NoEntryDimmMask & PsoDimmMaskRc2Ibt) != NoEntryDimmMask) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RC2_IBT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c deleted file mode 100644 index 73bb81796b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c +++ /dev/null @@ -1,270 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mprtt.c - * - * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPRTT_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define _DONT_CARE 0xFF - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted - * value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted for all present dimms/ranks - * @return FALSE - Table values cannot be extracted for all present dimms/ranks - * - */ -BOOLEAN -MemPGetRttNomWr ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 TgtDimmType; - UINT8 TgtRank; - UINT8 Chipsel; - UINT8 PsoCsMaskRtt; - UINT16 PsoCsMaskRtt16; - UINT8 NoEntryCsMask; - PSCFG_RTT_ENTRY *TblPtr; - PSCFG_RTT_ENTRY *OrgTblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - PsoCsMaskRtt = 0; - NoEntryCsMask = 0; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - OrgTblPtr = TblPtr; - for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) { - TblPtr = OrgTblPtr; - if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) (1 << Chipsel)) != 0) { - if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_QR; - TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1)); - } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) { - TgtDimmType = DIMM_DR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } else { - TgtDimmType = DIMM_SR; - TgtRank = (UINT8) 1 << (Chipsel & 1); - } - - if (DimmType == LRDIMM_TYPE) { - TgtDimmType = _DONT_CARE; - TgtRank = _DONT_CARE; - } - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) { - if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) { - NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom; - NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr; - break; - } - } - } - } - } - } - TblPtr++; - } - // Record which Cs(s) have no entries. Later on, we will check if there are overriding values for them. - if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) { - NoEntryCsMask |= (UINT8) 1 << Chipsel; - } - } - } - - PsoCsMaskRtt16 = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTNOM); - PsoCsMaskRtt16 &= MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODT_RTTWR); - // - // Check to see if invalid entry exist ? - // - if ((PsoCsMaskRtt16 & INVALID_CONFIG_FLAG) != 0) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nInvalid entry is found\n\n"); - return FALSE; - } - - // - // If there are no entries for certain Cs(s), we need to check if overriding values (both RttNom and RttWr) existed for them. - // Otherwise, return FALSE. - // - PsoCsMaskRtt = (UINT8) PsoCsMaskRtt16; - if (NoEntryCsMask != 0) { - if ((PsoCsMaskRtt & NoEntryCsMask) != NoEntryCsMask) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n"); - PutEventLog (AGESA_ERROR, MEM_ERROR_RTT_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c deleted file mode 100644 index 5d762a9ce6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c +++ /dev/null @@ -1,220 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mps2d.c - * - * A sub-engine determine which configs should use training. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-13 21:58:29 -0600 (Thu, 13 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPS___FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetS__ ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which determine if training should be run - * from a input table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetS__ ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - BOOLEAN FoundValue; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_S___ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - UINT16 P__TraingOveride; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfS__[i] != NULL) { - if (((EntryOfTables->TblEntryOfS__[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfS__[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfS__[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfS__[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_S___ENTRY *) ((EntryOfTables->TblEntryOfS__[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfS__[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfS__[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo training Config table\n"); - return FALSE; - } - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - FoundValue = FALSE; - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - if (TblPtr->Enable__ == 1) { - FoundValue = TRUE; - break; - } - } - } - } - } - TblPtr++; - } - P__TraingOveride = MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV____TRAINING); - if (P__TraingOveride != 0) { - if (NBPtr->Override__Training) { - FoundValue = TRUE; - } else { - FoundValue = FALSE; - } - } - // - // If there is no entry, check if overriding training existed. If not, show no entry found. - // - if (FoundValue == FALSE || ((P__TraingOveride & INVALID_CONFIG_FLAG) != 0)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo training config entries\n"); - return FALSE; - } else { - return TRUE; - } -}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c deleted file mode 100644 index b8cf2d9edc..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c +++ /dev/null @@ -1,227 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpsao.c - * - * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 52286 $ @e \$Date: 2011-05-04 03:48:21 -0600 (Wed, 04 May 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPSAO_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function which extracts Slow mode, Address timing and Output driver compensation value - * from a input table and store those value to a specific address. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return TRUE - Table values can be extracted per dimm population and ranks type. - * @return FALSE - Table values cannot be extracted per dimm population and ranks type. - * - */ -BOOLEAN -MemPGetSAO ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - UINT32 CurDDRrate; - UINT8 DDR3Voltage; - UINT16 RankTypeOfPopulatedDimm; - UINT16 RankTypeInTable; - UINT8 PsoMaskSAO; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - PSCFG_SAO_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (EntryOfTables->TblEntryOfSAO[i] != NULL) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) { - if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid; - PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr); - TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize; - break; - } - } - } - i++; - } - - // Check whether no table entry is found. - if (EntryOfTables->TblEntryOfSAO[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl table\n"); - return FALSE; - } - - CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66)); - DDR3Voltage = (UINT8) (1 << CONVERT_VDDIO_TO_ENCODED (NBPtr->RefPtr->DDR3Voltage)); - RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); - - for (i = 0; i < TableSize; i++) { - MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable); - if (TblPtr->DimmPerCh == MaxDimmPerCh) { - if ((TblPtr->DDRrate & CurDDRrate) != 0) { - if ((TblPtr->VDDIO & DDR3Voltage) != 0) { - if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) { - CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl; - CurrentChannel->DctOdcCtl = TblPtr->ODC; - CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE; - break; - } - } - } - } - TblPtr++; - } - - // - // If there is no entry, check if overriding values (SlowAccMode, AddrTmg and ODCCtrl) existed. If not, show no entry found. - // - PsoMaskSAO = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_SLOWACCMODE); - PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ODCCTRL); - PsoMaskSAO &= (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_TBLDRV_ADDRTMG); - if ((PsoMaskSAO == 0) && (i == TableSize)) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowAccMode, AddrTmg and ODCCtrl entries\n"); - } else { - return TRUE; - } - - if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) { - return TRUE; - } - - PutEventLog (AGESA_ERROR, MEM_ERROR_SAO_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c deleted file mode 100644 index c5450f1e0c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mpseeds.c - * - * A sub-engine extracts WL and HW RxEn seeds from PSCFG tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Ps) - * @e \$Revision: 45233 $ @e \$Date: 2011-01-13 21:58:29 -0600 (Thu, 13 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFamRegisters.h" -#include "cpuRegisters.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "mu.h" -#include "ma.h" -#include "mp.h" -#include "merrhdl.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_PS_MPSEEDS_FILECODE - - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemPGetTrainingSeeds ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * A sub-function extracts WL and HW RxEn seeds from PSCFG tables - * from a input table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK - * - * @return NBPtr->PsPtr->WLSeedVal - * @return NBPtr->PsPtr->HWRxENSeedVal - * - */ -BOOLEAN -MemPGetTrainingSeeds ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables - ) -{ - - UINT8 i; - UINT8 MaxDimmPerCh; - UINT8 NOD; - UINT8 TableSize; - DIMM_TYPE DimmType; - CPU_LOGICAL_ID LogicalCpuid; - UINT8 PackageType; - UINT8 Seedloop; - UINT8 CH; - PSC_TBL_ENTRY **TblEntryPtr; - PSCFG_SEED_ENTRY *TblPtr; - CH_DEF_STRUCT *CurrentChannel; - - CurrentChannel = NBPtr->ChannelPtr; - TblEntryPtr = NULL; - TblPtr = NULL; - TableSize = 0; - PackageType = 0; - LogicalCpuid.Family = AMD_FAMILY_UNKNOWN; - MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID); - NOD = (UINT8) 1 << (MaxDimmPerCh - 1); - CH = 1 << (CurrentChannel->ChannelID); - - if (CurrentChannel->RegDimmPresent != 0) { - DimmType = RDIMM_TYPE; - } else if (CurrentChannel->SODimmPresent != 0) { - DimmType = SODIMM_TYPE; - if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_SOLDERED_DOWN_SODIMM_TYPE, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL) != NULL) { - DimmType = SODWN_SODIMM_TYPE; - } - } else if (CurrentChannel->LrDimmPresent != 0) { - DimmType = LRDIMM_TYPE; - } else { - DimmType = UDIMM_TYPE; - } - - // Get seed value of WL, then HW RxEn - for (Seedloop = 0; Seedloop < 2; Seedloop++) { - TblEntryPtr = (Seedloop == 0) ? EntryOfTables->TblEntryOfWLSeed : EntryOfTables->TblEntryOfHWRxENSeed; - - i = 0; - // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. - while (TblEntryPtr[i] != NULL) { - if (((TblEntryPtr[i])->Header.DimmType & DimmType) != 0) { - // - // Determine if this is the expected NB Type - // - LogicalCpuid = (TblEntryPtr[i])->Header.LogicalCpuid; - PackageType = (TblEntryPtr[i])->Header.PackageType; - if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { - TblPtr = (PSCFG_SEED_ENTRY *) ((TblEntryPtr[i])->TBLPtr); - TableSize = (TblEntryPtr[i])->TableSize; - break; - } - } - i++; - } - - // Check whether no table entry is found. - if (TblEntryPtr[i] == NULL) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s training seeds Config table\n", (Seedloop == 0) ? "WL" : "HW RxEn"); - return FALSE; - } - - for (i = 0; i < TableSize; i++) { - if ((TblPtr->DimmPerCh & NOD) != 0) { - if ((TblPtr->Channel & CH) != 0) { - if (Seedloop == 0) { - NBPtr->PsPtr->WLSeedVal = (UINT8) TblPtr->SeedVal; - } else { - NBPtr->PsPtr->HWRxENSeedVal = TblPtr->SeedVal; - } - break; - } - } - TblPtr++; - } - - if (i == TableSize) { - IDS_HDT_CONSOLE (MEM_FLOW, "\nNo %s seed entries\n\n", (Seedloop == 0) ? "WL" : "HW RxEn"); - PutEventLog (AGESA_ERROR, MEM_ERROR_TRAINING_SEED_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); - SetMemError (AGESA_ERROR, NBPtr->MCTPtr); - if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { - ASSERT (FALSE); - } - return FALSE; - } - } - - return TRUE; -}
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