diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc | 11 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c | 228 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c | 746 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h | 84 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c | 456 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c | 134 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c | 496 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h | 212 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c | 140 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c | 213 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c | 247 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c | 238 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c | 66 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c | 639 |
14 files changed, 0 insertions, 3910 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc deleted file mode 100644 index 1114ad4eb8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/Makefile.inc +++ /dev/null @@ -1,11 +0,0 @@ -libagesa-y += mnParTrainHy.c -libagesa-y += mnS3hy.c -libagesa-y += mndcthy.c -libagesa-y += mnflowhy.c -libagesa-y += mnhy.c -libagesa-y += mnidendimmhy.c -libagesa-y += mnmcthy.c -libagesa-y += mnothy.c -libagesa-y += mnphyhy.c -libagesa-y += mnprotohy.c -libagesa-y += mnreghy.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c deleted file mode 100644 index fca7a61bcf..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c +++ /dev/null @@ -1,228 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnParTrainHy.c - * - * Feature which performs Memory DQS training on each node with each node training - * its own memory through code running on a core in the associated processor. - * This way memory can be trained in parallel by more than one processor. - * - * This file contains the Hydra specific parallel training function. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Feat/HCTRN) - * @e \$Revision: 54775 $ @e \$Date: 2011-06-12 21:05:26 -0600 (Sun, 12 Jun 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuApicUtilities.h" -#include "mfParallelTraining.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE -/*----------------------------------------------------------------------------- -* EXPORTED FUNCTIONS -* -*----------------------------------------------------------------------------- -*/ -BOOLEAN -MemFParallelTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -STATIC -MemConstructRemoteNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr -); -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is the training function which set up the environment for remote - * training on the ap and launches the remote routine. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - Launch training on AP successfully. - * @return FALSE - Fail to launch training on AP. - */ -BOOLEAN -MemFParallelTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - DIE_STRUCT *MCTPtr; - REMOTE_TRAINING_ENV *EnvPtr; - AP_TASK TrainingTask; - UINT8 Socket; - UINT8 Module; - UINT8 APCore; - UINT8 p; - UINT32 LowCore; - UINT32 HighCore; - UINT32 BspSocket; - UINT32 BspModule; - UINT32 BspCore; - AGESA_STATUS Status; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - UINT16 MctDataSize; - StdHeader = &(NBPtr->MemPtr->StdHeader); - MCTPtr = NBPtr->MCTPtr; - Socket = MCTPtr->SocketId; - Module = MCTPtr->DieId; - - // - // Allocate buffer for REMOTE_TRAINING_ENV - // - MctDataSize = MAX_DCTS_PER_NODE_HY * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { - EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); - - // - // Setup Remote training environment - // - LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); - LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); - for (p = 0; p < MAX_PLATFORM_TYPES; p++) { - EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; - } - EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; - EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY; - EnvPtr->FeatPtr = NBPtr->FeatPtr; - EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; - EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; - EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; - EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; - EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; - EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; - - LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); - - // - // Get Socket, Core of the BSP - // - IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); - EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); - EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); - - // - // Set up the remote task structure - // - TrainingTask.DataTransfer.DataPtr = EnvPtr; - TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4; - TrainingTask.DataTransfer.DataTransferFlags = 0; - TrainingTask.ExeFlags = 0; - TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; - - // - // Get Target AP Core - // - GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); - APCore = (UINT8) (LowCore & 0x000000FF); - - // - // Launch Remote Training - // - ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); - - HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); - - return TRUE; - } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" - return FALSE; - } -} - -BOOLEAN -STATIC -MemConstructRemoteNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN DIE_STRUCT *MCTPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr - ) -{ - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - NBPtr->MCTPtr = MCTPtr; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - - MemNInitNBDataHy (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - MemNSwitchDCTNb (NBPtr, 0); - - //---------------------------------------------------------------------------- - // Get TSC rate of the this AP - //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c deleted file mode 100644 index 3d6ec1d727..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c +++ /dev/null @@ -1,746 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mns3hy.c - * - * HY memory specific function to support S3 resume - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 50673 $ @e \$Date: 2011-04-12 21:18:06 -0600 (Tue, 12 Apr 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "S3.h" -#include "mfs3.h" -#include "mnhy.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "mnS3hy.h" -#include "heapManager.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemS3ResumeConstructNBBlockHy ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -UINT16 -STATIC -MemNS3GetRegLstPtrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ); - -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstHy ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ); - -VOID -STATIC -MemNS3ExitSelfRefRegHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -MemNS3SetSpecialPCIRegHy ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ); - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = { - {MemNS3GetCSRNb, MemNS3SetCSRNb}, - {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy}, - {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} -}; - -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = { - {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, - {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, - {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, - {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, - {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, - {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, - {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, - {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, - {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, - {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, - {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, - {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} -}; - -CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = { - 0, - (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)), - S3PciPreSelfRefDescriptorHy, - NULL -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = { - // DCT 0 - {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 322 - {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - //errata 263 - {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - - // DCT 1 - {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 322 - {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - // errata 263 - {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore F2x[1,0]94 right before exit self refresh - {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = { - 0, - (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPreSelfDescriptorHy, - PciSpecialCaseFuncHy -}; - -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = { - // DCT0 - {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, - - // DCT1 - {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, - - // DllShutDown - {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, - - // Restore scrubber related registers after restoring training related registers - {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} -}; - -CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = { - 0, - (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), - S3CPciPostSelfDescriptorHy, - PciSpecialCaseFuncHy -}; - -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = { - {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, - {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, - {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} -}; - -CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = { - 0, - (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)), - S3MSRPreSelfRefDescriptorHy, - NULL -}; - -VOID *MemS3RegListHy[] = { - (VOID *)&S3PciPreSelfRefHy, - NULL, - (VOID *)&S3CPciPreSelfRefHy, - (VOID *)&S3CPciPostSelfRefHy, - (VOID *)&S3MSRPreSelfRefHy, - NULL, - NULL, - NULL -}; - -CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = { - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), - SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) -}; - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for S3 resume - * - * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. - * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. - * @param[in] NodeID - Node ID of the target node. - * - * @return BOOLEAN - * TRUE - This is the correct constructor for the targeted node. - * FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemS3ResumeConstructNBBlockHy ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - INT32 i; - MEM_NB_BLOCK *NBPtr; - - NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->Ganged = FALSE; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - - for (i = 0; i < EnumSize; i++) { - NBPtr->IsSupported[i] = FALSE; - } - - for (i = 0; i < NumberOfHooks; i++) { - NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; - } - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); - - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->SwitchDCT = MemNSwitchDCTNb; - NBPtr->SwitchChannel = MemNSwitchChannelNb; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy; - ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32); - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function returns the register list for each device for HY - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP - * @return UINT16 - size of the device descriptor on the target node. - */ -UINT16 -STATIC -MemNS3GetRegLstPtrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT DESCRIPTOR_GROUP *DescriptPtr - ) -{ - UINT8 i; - UINT16 Size; - Size = 0; - for (i = PRESELFREF; i <= POSTSELFREF; i ++) { - DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); - DescriptPtr->PCIDevice[i].Node = NBPtr->Node; - DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i; - Size += sizeof (PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); - DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; - DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i; - Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); - } - DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); - DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i; - Size += sizeof (MSR_DEVICE_DESCRIPTOR); - } - DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); - DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; - if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { - DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i; - Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); - } - } - return Size; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function return the register list according to the register ID. - * - * @param[in] RegisterLstID - value of the Register list ID. - * @param[out] **RegisterHeader - pointer to the address of the register list. - * @return none - */ -AGESA_STATUS -STATIC -MemNS3GetDeviceRegLstHy ( - IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader - ) -{ - if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) { - ASSERT(FALSE); // RegisterListID exceeded size of Register list - return AGESA_FATAL; - } - if (MemS3RegListHy[RegisterLstID] != NULL) { - *RegisterHeader = MemS3RegListHy[RegisterLstID]; - return AGESA_SUCCESS; - } - ASSERT(FALSE); // Device register list error - return AGESA_FATAL; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in] AccessWidth - Access width of the register - * @param[in] Address - address of the CSR register in PCI_ADDR format. - * @param[in, out] *Value - Pointer to the value be read. - * @param[in, out] *ConfigPtr - Pointer to Config handle. - * @return none - */ -VOID -STATIC -MemNS3SetSpecialPCIRegHy ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR Address, - IN VOID *Value, - IN OUT VOID *ConfigPtr - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (Address.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_HY); - // Save the value in the heap at appropriate offset based on the index - // of the target register in the special case array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { - if (SpecialCasePCIRegHy[i] == Address.Address.Register) { - *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; - } - } - } - } -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function stores special case register on the heap. - * - * @param[in,out] *NBPtr - Pointer to the northbridge block. - * @param[in,out] *StdHeader - Config handle for library and services. - * @return none - */ -VOID -STATIC -MemNS3ExitSelfRefRegHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - LOCATE_HEAP_PTR LocateBufferPtr; - UINT8 i; - PCI_ADDR PciAddr; - UINT32 Value; - UINT8 NodeID; - UINT8 Offset; - S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; - - Offset = 0; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - PciAddr.Address.Function = 2; - LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; - if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { - SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; - // Get the node ID of the target die. - NodeID = (UINT8) (PciAddr.Address.Device - 24); - for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { - if (SpecialHeapHeader[i].Node == NodeID) { - // Get the offset in the heap for the target die. - Offset = SpecialHeapHeader[i].Offset; - break; - } - } - ASSERT (i < MAX_NODES_SUPPORTED_HY); - // Restore the value one by one in the sequence of the special case register array. - if (Offset != 0) { - for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { - PciAddr.Address.Register = SpecialCasePCIRegHy[i]; - Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); - MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); - } - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h deleted file mode 100644 index f644e7d349..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h +++ /dev/null @@ -1,84 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnS3hy.h - * - * S3 resume memory related function for HY. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -#ifndef _MNS3HY_H_ -#define _MNS3HY_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -/// ID for register list of HY -typedef enum { - PCI_LST_ESR_HY, ///< Assign 0x0000 for PCI register list for pre exit self refresh. - PCI_LST_HY, ///< Assign 0x0001 for PCI register list for post exist self refresh. - CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. - CPCI_LST_HY, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. - MSR_LST_ESR_HY, ///< Assign 0x0004 for MSR register list for pre exit self refresh. - MSR_LST_HY, ///< Assign 0x0005 for MSR register list for post exit self refresh. - CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. - CMSR_LST_HY ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. -} RegisterListIDHy; - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -#endif //_MNS3HY_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c deleted file mode 100644 index f808280184..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c +++ /dev/null @@ -1,456 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mndctHy.c - * - * Northbridge DCT support for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "merrhdl.h" -#include "cpuFamRegisters.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function programs the memory controller with configuration parameters - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - An Error value lower than AGESA_FATAL may have occurred - * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred - * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value - */ - -BOOLEAN -MemNAutoConfigHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 PowerDownMode; - UINT32 Value32; - DIE_STRUCT *MCTPtr; - DCT_STRUCT *DCTPtr; - MEM_PARAMETER_STRUCT *RefPtr; - - RefPtr = NBPtr->RefPtr; - MCTPtr = NBPtr->MCTPtr; - DCTPtr = NBPtr->DCTPtr; - //====================================================================== - // Build Dram Control Register Value (F2x78) - //====================================================================== - // - //It is recommended that these bits remain in the default state. - //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); - - MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); - - //====================================================================== - // Build Dram Config Lo Register Value - //====================================================================== - // - - if (MCTPtr->Status[SbParDimms]) { - // - // SbParDimms should be set for all DDR3 RDIMMS - // Cannot turn off ParEn for DDR3 - // - //@attention - add debug option for parity control - MemNSetBitFieldNb (NBPtr, BFParEn, 1); - } - - - if (MCTPtr->GangedMode) { - MemNSetBitFieldNb (NBPtr, BFWidth128, 1); - } - - MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); - - if (!MCTPtr->Status[SbRegistered]) { - MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); - } - - if (MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); - } - - //====================================================================== - // Build Dram Config Hi Register Value - //====================================================================== - // - - MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); - - if (MCTPtr->Status[SbRegistered]) { - if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { - MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); - } - } - - if (RefPtr->EnableBankSwizzle) { - MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); - } - - if (DCTPtr->Timings.DimmQrPresent) { - if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1); - } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { - MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); - } - } - - MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); - MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); - //====================================================================== - // Build Dram Config Misc Register Value - //====================================================================== - // - if (MCTPtr->Status[SbRegistered]) { - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { - MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); - } - } - //====================================================================== - // Build Dram Config Misc 2 Register Value - //====================================================================== - // - // - // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms - // - if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { - MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); - } - // - // DTaxTxFifpWrDly - // - Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); - if ((Value32 >= 2) && (Value32 <= 5)) { - MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); - } - - // - // ProgOdtEn - // - if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); - } else { - MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); - } - // - // OdtSwizzle - // - if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { - PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode); - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode == 1) { - MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); - } - } - - - return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNSendMrsCmdHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwapBitsNb (NBPtr); - - IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n", - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, - (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); - - // 1.Set SendMrsCmd=1 - MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); - - // 2.Wait for SendMrsCmd=0 - MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sends an MRS command to all CS of all channels - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *DummyPtr - Unused pointer - * - * @return TRUE - */ - -BOOLEAN -MemNSendMrsCmdPerCsHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *DummyPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 Dummy; - - if (!NBPtr->MCTPtr->Status[SbRegistered]) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { - if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) { - IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); - // if chip select present - NBPtr->TechPtr->SendAllMRCmds (NBPtr->TechPtr, ChipSel); - // NOTE: wait 512 clocks for DLL-relock - MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us - } - } - } - } - } - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM init - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDramInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - //Set PllLockTime and DllLockTime to default. - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Enable DLL Shut down - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNEnDLLShutDownHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - BOOLEAN DllShutDownEn; - - DllShutDownEn = TRUE; - IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); - - if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { - if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); - MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); - MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - } - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * Workaround for erratum 322 and 263 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -VOID -MemNBeforePlatformSpecHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - // Errata 263 - if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { - MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); - } else { - MemNSetBitFieldNb (NBPtr, BFErr263, 0); - } - - // Errata 322 - // 1.Write 00000000h to F2x[1,0]9C_xD08E000 - MemNSetBitFieldNb (NBPtr, BFErr322I, 0); - // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is - // greater than or equal to 011b (DDR-800 and higher), - // then write 00000080h to F2x[1,0]9C_xD02E001, - // else write 00000090h to F2x[1,0]9C_xD02E001. - MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * Initializes extended MMIO address space - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] OptParam - Optional parameter - * - * @return TRUE - */ -BOOLEAN -MemNInitExtMMIOAddrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ) -{ - UINT8 Index; - UINT32 Value; - PCI_ADDR PciAddr; - - if (NBPtr->RefPtr->SysLimit >= _1TB_RJ16) { - // Initialize all indices of F1x114_x2 and F1x114_x3. - for (Index = 0; Index < 32; Index++) { - PciAddr = NBPtr->PciAddr; - PciAddr.Address.Function = 1; - - PciAddr.Address.Register = 0x110; - Value = 0x20000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x110; - Value = 0x30000000 | Index; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - - PciAddr.Address.Register = 0x114; - Value = 0; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - } - } - return TRUE; -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c deleted file mode 100644 index 588f27a824..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnflowhy.c - * - * Hydra initializer for MCT and DCT - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/Main) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE -/* features */ - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the platform specific block - * - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - AGESA_SUCCESS at least one dorm factor was found - * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found - */ - -BOOLEAN -MemNPlatformSpecificFormFactorInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 f; - UINT8 ErrUnSuppFFCount; - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - NBPtr->SwitchDCT (NBPtr, Dct); - if (NBPtr->ChannelPtr->ChDimmValid != 0) { - ErrUnSuppFFCount = 0; - for (f = 0; f < MAX_FF_TYPES; f++) { - ASSERT (memPlatSpecFFInstalledHy[f] != NULL); - if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { - ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors - } else { - break; - } - } - if (ErrUnSuppFFCount == MAX_FF_TYPES) { - return FALSE; // No FF types are supported - } - } - } - return TRUE; -} -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c deleted file mode 100644 index 16f6b13c94..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c +++ /dev/null @@ -1,496 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnhy.c - * - * Common Northbridge functions for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "mu.h" -#include "S3.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "heapManager.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -#define SPLIT_CHANNEL (UINT32) 0x20000000 -#define CHANNEL_SELECT (UINT32) 0x10000000 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; -extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB - * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA - * @param[in] NodeID - UINT8 indicating node ID of the NB object. - * - * @return Boolean indicating that this is the correct memory - * controller type for the node number that was passed in. - */ - -BOOLEAN -MemConstructNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ) -{ - UINT8 Dct; - UINT8 Channel; - UINT8 SpdSocketIndex; - UINT8 SpdChannelIndex; - DIE_STRUCT *MCTPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; - - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->MemPtr = MemPtr; - NBPtr->RefPtr = MemPtr->ParameterListPtr; - NBPtr->SharedPtr = SharedPtr; - - MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->MCTPtr = MCTPtr; - NBPtr->MCTPtr->NodeId = NodeID; - NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; - NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - - // - // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - // - AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * ( - sizeof (DCT_STRUCT) + ( - MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) - ) - ); - AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); - SetMemError (AGESA_FATAL, MCTPtr); - ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs - return FALSE; - } - - MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY; - MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT); - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - MCTPtr->DctData[Dct].Dct = Dct; - MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY; - MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; - MCTPtr->DctData[Dct].ChData[0].Dct = Dct; - AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT); - } - NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; - - // - // Initialize Socket List - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); - MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); - MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; - } - - MemNInitNBDataHy (NBPtr); - - FeatPtr->InitCPG (NBPtr); - NBPtr->FeatPtr = FeatPtr; - FeatPtr->InitHwRxEn (NBPtr); - // - // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel - // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that - // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the - // dimm types(QR or not) are known. This is done in the Technology block constructor. - // - // Calculate the SpdSocketIndex separately from the SpdChannelIndex. - // This will facilitate modifications due to some processors that might - // map the DCT-CHANNEL differently. - // - SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); - // - // Traverse the Dct/Channel structures - // - for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) { - // - // Calculate the number of Dimms on this channel using the - // die/dct/channel to Socket/channel conversion. - // - SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, - NBPtr->MCTPtr->SocketId, - MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), - &MemPtr->StdHeader); - NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); - } - } - - MemNSwitchDCTNb (NBPtr, 0); - - return TRUE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initializes member functions and variables of NB block. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitNBDataHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - NBPtr->DctCachePtr = NBPtr->DctCache; - NBPtr->PsPtr = NBPtr->PSBlock; - - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Dct = 0; - NBPtr->Channel = 0; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY; - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->Ganged = FALSE; - NBPtr->PosTrnPattern = POS_PATTERN_256B; - NBPtr->MemCleared = FALSE; - NBPtr->StartupSpeed = DDR800_FREQUENCY; - NBPtr->RcvrEnDlyLimit = 0x1FF; - NBPtr->DefDctSelIntLvAddr = 3; - NBPtr->CsRegMsk = 0x1FF83FE0; - - LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); - - NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; - NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; - NBPtr->InitializeMCT = MemNInitializeMctHy; - NBPtr->FinalizeMCT = MemNFinalizeMctHy; - NBPtr->SendMrsCmd = MemNSendMrsCmdHy; - NBPtr->sendZQCmd = MemNSendZQCmdNb; - NBPtr->WritePattern = MemNWritePatternHy; - NBPtr->ReadPattern = MemNReadPatternHy; - NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->CompareTestPattern = MemNCompareTestPatternNb; - NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; - NBPtr->StitchMemory = MemNStitchMemoryNb; - NBPtr->AutoConfig = MemNAutoConfigHy; - NBPtr->PlatformSpec = MemNPlatformSpecNb; - NBPtr->InitMCT = MemNInitMCTNb; - NBPtr->DisableDCT = MemNDisableDCTNb; - NBPtr->StartupDCT = MemNStartupDCTNb; - NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; - NBPtr->ChangeFrequency = MemNChangeFrequencyNb; - NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; - NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse; - NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; - NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; - NBPtr->HtMemMapInit = MemNHtMemMapInitNb; - NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; - NBPtr->CpuMemTyping = MemNCPUMemTypingNb; - NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingHy; - NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->OtherTiming = MemNOtherTimingHy; - NBPtr->UMAMemTyping = MemNUMAMemTypingNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; - NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; - NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) MemNTrainingFlowNb; - MemNInitNBDataNb (NBPtr); - NBPtr->PollBitField = MemNPollBitFieldNb; - NBPtr->BrdcstCheck = MemNBrdcstCheckNb; - NBPtr->BrdcstSet = MemNBrdcstSetNb; - NBPtr->GetTrainDly = MemNGetTrainDlyNb; - NBPtr->SetTrainDly = MemNSetTrainDlyNb; - NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; - NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; - NBPtr->RankEnabled = MemNRankEnabledNb; - NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy; - NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; - NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; - NBPtr->MemNInitPhyComp = MemNInitPhyCompHy; - NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy; - NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy; - NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, INT16 *)) memDefRet; - NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; - NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; - NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; - NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; - NBPtr->CSPerChannel = MemNCSPerChannelNb; - NBPtr->CSPerDelay = MemNCSPerDelayNb; - NBPtr->FlushPattern = MemNFlushPatternNb; - NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; - NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->GetUmaSize = MemNGetUmaSizeNb; - NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; - NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; - NBPtr->WaitXMemClks = MemNWaitXMemClksNb; - NBPtr->MemNGetDramTerm = MemNGetDramTermNb; - NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb; - NBPtr->MemNGetMR0CL = MemNGetMR0CLNb; - NBPtr->MemNGetMR0WR = MemNGetMR0WRNb; - NBPtr->MemNSaveMR0 = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; - NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb; - NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - - NBPtr->IsSupported[SetSpareEn] = TRUE; - NBPtr->IsSupported[CheckSpareEn] = TRUE; - NBPtr->IsSupported[SetDllShutDown] = TRUE; - NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; - NBPtr->IsSupported[CheckMaxDramRate] = TRUE; - NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; - NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; - NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; - NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; - NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; - NBPtr->IsSupported[CheckODTControls] = TRUE; - NBPtr->IsSupported[CheckDummyCLRead] = TRUE; - NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; - NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; - NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; - - NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy; - NBPtr->FamilySpecificHook[InitExtMMIOAddr] = MemNInitExtMMIOAddrHy; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the default values in the MEM_DATA_STRUCT - * - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * - */ -VOID -MemNInitDefaultsHY ( - IN OUT MEM_DATA_STRUCT *MemPtr - ) -{ - UINT8 Socket; - UINT8 Channel; - MEM_PARAMETER_STRUCT *RefPtr; - ASSERT (MemPtr != NULL); - RefPtr = MemPtr->ParameterListPtr; - - // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; - RefPtr->UmaMode = UserOptions.CfgUmaMode; - RefPtr->UmaSize = UserOptions.CfgUmaSize; - RefPtr->MemHoleRemapping = TRUE; - RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; - // - - - // Dram Timing - RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; - RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; - for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { - for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { - MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; - MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; - } - } - - // Memory Clear - RefPtr->EnableMemClr = TRUE; - - // TableBasedAlterations - RefPtr->TableBasedAlterations = NULL; - - // Platform config table - RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; - - // Memory Restore - RefPtr->MemRestoreCtl = FALSE; - RefPtr->SaveMemContextCtl = FALSE; - AmdS3ParamsInitializer (&RefPtr->MemContext); - - // Dram Configuration - RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; - RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; - RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; - RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; - RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; - RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; - - // Dram Power - RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; - - // ECC - RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; - - // Vref - RefPtr->ExternalVrefCtl = UserOptions.CfgExternalVrefCtlFeature; - - //Training Mode - RefPtr->ForceTrainMode = UserOptions.CfgForceTrainMode; -} -/*-----------------------------------------------------------------------------*/ -/** - * - * This function writes training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Pattern[] - Pattern to write - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNWritePatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUWriteCachelines (Address, Pattern, ClCount); -} - -/*-----------------------------------------------------------------------------*/ -/** - * - * This function reads training pattern - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Buffer[] - Buffer to fill - * @param[in] Address - System Address [47:16] - * @param[in] ClCount - Number of cache lines - * - */ - -VOID -MemNReadPatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ) -{ - Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); - MemUReadCachelines (Buffer, Address, ClCount); -} -/* -----------------------------------------------------------------------------*/ -/** - * - * This function initiates DQS training for Server NB - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -BOOLEAN -memNEnableTrainSequenceHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - BOOLEAN Retval; - Retval = TRUE; - if (!MemNIsIdSupportedHy (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) { - Retval = FALSE; - } - return Retval; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h deleted file mode 100644 index a2379fc26d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h +++ /dev/null @@ -1,212 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnhy.h - * - * Northbridge Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem) - * @e \$Revision: 47408 $ @e \$Date: 2011-02-18 09:56:31 -0700 (Fri, 18 Feb 2011) $ - * - **/ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _MNHY_H_ -#define _MNHY_H_ - -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ -#define MAX_CHANNELS_PER_SOCKET_HY 4 -#define MAX_DCTS_PER_NODE_HY 2 -#define MAX_CHANNELS_PER_DCT_HY 1 -#define MAX_NODES_SUPPORTED_HY 8 - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -MemConstructNBBlockHY ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *SharedPtr, - IN UINT8 NodeID - ); - -VOID -MemNInitNBDataHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitDefaultsHY ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -BOOLEAN -MemNInitializeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNFinalizeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNSendMrsCmdHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNAutoConfigHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNOtherTimingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNInitPhyCompHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNWritePatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT32 Address, - IN UINT8 Pattern[], - IN UINT16 ClCount - ); - -VOID -MemNReadPatternHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Buffer[], - IN UINT32 Address, - IN UINT16 ClCount - ); - -VOID -InitNBRegTableHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ); - -UINT8 -MemNGetSocketRelativeChannelHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ); - -BOOLEAN -MemNIsIdSupportedHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ); - -VOID -MemNBeforeDramInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNPlatformSpecificFormFactorInitHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemNEnDLLShutDownHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -UINT32 -MemNCmnGetSetFieldHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ); - -VOID -MemNBeforePlatformSpecHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -memNEnableTrainSequenceHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -BOOLEAN -MemNSendMrsCmdPerCsHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *DummyPtr - ); - -BOOLEAN -MemNInitExtMMIOAddrHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT VOID *OptParam - ); - -VOID -MemNBeforeDQSTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif /* _MNHY_H_ */ - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c deleted file mode 100644 index fdfa5ead3c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c +++ /dev/null @@ -1,140 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnidendimmhy.c - * - * Hy northbridge constructor for dimm identification translator. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 45911 $ @e \$Date: 2011-01-24 13:55:11 -0700 (Mon, 24 Jan 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "mfidendimm.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the northbridge block for dimm identification translator - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT - * @param[in,out] NodeID - ID of current node to construct - * @return TRUE - This is the correct constructor for the targeted node. - * @return FALSE - This isn't the correct constructor for the targeted node. - */ - -BOOLEAN -MemNIdentifyDimmConstructorHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ) -{ - // - // Determine if this is the expected NB Type - // - GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); - if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { - return FALSE; - } - - NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; - NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; - NBPtr->CsRegMsk = 0x1FF83FE0; - NBPtr->MemPtr = MemPtr; - NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); - NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; - NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; - NBPtr->Ganged = FALSE; - InitNBRegTableHy (NBPtr, NBPtr->NBRegTable); - NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; - NBPtr->GetBitField = MemNGetBitFieldNb; - NBPtr->SetBitField = MemNSetBitFieldNb; - NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; - - return TRUE; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c deleted file mode 100644 index 91580b745d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c +++ /dev/null @@ -1,213 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnmcthy.c - * - * Northbridge Hydra MCT supporting functions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "mport.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets final values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNFinalizeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - DRAM_PREFETCH_MODE DramPrefetchMode; - S_UINT64 SMsr; - UINT16 Speed; - UINT32 ExtMctCfgLoRegVal; - - MemPtr = NBPtr->MemPtr; - DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; - Speed = NBPtr->DCTPtr->Timings.Speed; - MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); - - ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); - ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; - - ExtMctCfgLoRegVal &= 0x0FFFFFFF; - if (Speed == DDR667_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x40000000; - } else if (Speed == DDR800_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x50000000; - } else if (Speed == DDR1066_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x60000000; - } else if (Speed == DDR1333_FREQUENCY) { - ExtMctCfgLoRegVal |= 0x80000000; - } else { - ExtMctCfgLoRegVal |= 0x90000000; - } - // - // PrefFiveConf, PrefFourConf - // - ExtMctCfgLoRegVal |= 0x0FC00000; - // - // EnSplitDctLimits - // - if (!NBPtr->Ganged) { - ExtMctCfgLoRegVal |= 0x00001000; - } - MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); - } - - if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { - MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); - } - - if (NBPtr->Node == BSP_DIE) { - if (!NBPtr->ClToNbFlag) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets initial values in BUCFG and BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNInitializeMctHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_DATA_STRUCT *MemPtr; - S_UINT64 SMsr; - - MemPtr = NBPtr->MemPtr; - - if (NBPtr->Node == BSP_DIE) { - LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - if (SMsr.lo & ((UINT32)1 << 15)) { - NBPtr->ClToNbFlag = 1; - } - SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis - LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); - - LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c deleted file mode 100644 index 1c6cab087c..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c +++ /dev/null @@ -1,247 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnothy.c - * - * Northbridge Non-SPD timings for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "Ids.h" -#include "mm.h" -#include "mn.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -STATIC -MemNSetOtherTimingHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -/* -UINT32 -STATIC -MemNGetODTDelaysHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -*/ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -extern BUILD_OPT_CFG UserOptions; - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - * @return TRUE - No fatal error occurs. - * @return FALSE - Fatal error occurs. - */ - -BOOLEAN -MemNOtherTimingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MemNSwitchDCTNb (NBPtr, 0); - if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { - MemNSetOtherTimingHY (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownHy (NBPtr); - } - - MemNSwitchDCTNb (NBPtr, 1); - if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { - MemNSetOtherTimingHY (NBPtr); - MemNPowerDownCtlNb (NBPtr); - MemNEnDLLShutDownHy (NBPtr); - } - return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); -} - -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function sets the non-SPD timings in PCI registers - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemNSetOtherTimingHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - - MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); - MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the ODT delays - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -/* -UINT32 -STATIC -MemNGetODTDelaysHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Ld; - UINT32 ODTDelays; - // - // On revision D processors, the BIOS must additionally configure the ODT pattern - // and the ODT switching delays. - // - // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. - // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. - // -Value of 2, BL = 4 else assume BL=8. - // -Initialize ODTDelays based on BL value - // -WrOdtOnDuration [14:12] = BL / 2 + 1 - // -WrOdtTrnOnDly [10:8] = 0 - // -RdOdtOnDuration [6:4] = BL / 2 + 1 - // - ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; - - // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) - // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] - Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if (Ld < 0) { - Ld = 0; - } - if (Ld > 7) { - Ld = 7; - } - ODTDelays += Ld; - return ODTDelays; -} -*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function enables power down mode - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -/* -VOID -STATIC -MemNPowerDownCtlHY ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - MEM_PARAMETER_STRUCT *RefPtr; - UINT8 PowerDownMode; - - RefPtr = NBPtr->RefPtr; - - // we can't enable powerdown mode when doing WL - if (RefPtr->EnablePowerDown) { - MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); - PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; - IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); - if (PowerDownMode) { - MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); - } - } -} -*/
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c deleted file mode 100644 index d7b587b492..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c +++ /dev/null @@ -1,238 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnphyHy.c - * - * Northbridge Phy support for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - - - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "ma.h" -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "mu.h" -#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB -#include "mnhy.h" -#include "PlatformMemoryConfiguration.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define UNUSED_CLK 4 - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/* -----------------------------------------------------------------------------*/ - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNInitPhyCompHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; - CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; - CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; - CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; - UINT8 i; - UINT8 j; - UINT8 CurrDct; - UINT8 MaxDimmsPerChannel; - UINT8 *DimmsPerChPtr; - - CurrDct = NBPtr->Dct; - - // - // Get Platform Information - // - DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID, 0, NULL, NULL); - if (DimmsPerChPtr != NULL) { - MaxDimmsPerChannel = *DimmsPerChPtr; - } else { - MaxDimmsPerChannel = 2; - } - - // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 - // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. - // DisAutoComp will be cleared after Dram init has completed - // - MemNSwitchDCTNb (NBPtr, 0); - MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); - MemUWait10ns (500, NBPtr->MemPtr); - MemNSwitchDCTNb (NBPtr, CurrDct); - - // 3. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the - // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. - // - // 4. For each normalized driver strength code read from - // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding - // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, - // D3Cmp2PCal]. - // - j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); - i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); - - MemNSwitchDCTNb (NBPtr, 0); - ASSERT (j <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); - - ASSERT (i <= 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); - - // - // Special Case for certain configs - // - // 3DPCH Fully populated. - if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { - MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3); - MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5); - } - - MemNSwitchDCTNb (NBPtr, CurrDct); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This is a general purpose function that executes before DRAM training - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemNBeforeDQSTrainingHy ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - UINT8 Dct; - UINT8 ChipSel; - UINT32 TestAddrRJ16; - UINT32 RealAddr; - - MemTBeginTraining (NBPtr->TechPtr); - - for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { - MemNSwitchDCTNb (NBPtr, Dct); - if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { - for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { - if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { - - RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); - - MemUDummyCLRead (RealAddr); - - MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); - MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns - MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); - MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us - MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); - break; - } - } - } - if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { - if (!NBPtr->MCTPtr->Status[SbEccDimms]) { - MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); - } - if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { - MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); - } - } - } - - MemTEndTraining (NBPtr->TechPtr); - - MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c deleted file mode 100644 index 62288a4fe6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c +++ /dev/null @@ -1,66 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnprotohy.c - * - * Northbridge support functions for Errata and early samples - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - - - -#include "AGESA.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/* - *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *----------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c deleted file mode 100644 index 5177cec4bd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c +++ /dev/null @@ -1,639 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * mnreghy.c - * - * Common Northbridge register related functions for Hydra - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: (Mem/NB/HY) - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - **/ -/***************************************************************************** -* -* Copyright (C) 2012 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of Advanced Micro Devices, Inc. nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* *************************************************************************** -* -*/ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "AdvancedApi.h" -#include "amdlib.h" -#include "Ids.h" -#include "OptionMemory.h" -#include "mm.h" -#include "mn.h" -#include "mnhy.h" -#include "merrhdl.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G1_PEICC) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -/*-----------------------------------------------------------------------------*/ -/** - * MemNIsIdSupportedHy - * This function matches the CPU_LOGICAL_ID with certain criteria to - * determine if it is supported by this NBBlock. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID - * - * @return TRUE - This node is a Hydra. - * @return FALSE - This node is not a Hydra. - * - */ -BOOLEAN -MemNIsIdSupportedHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN CPU_LOGICAL_ID *LogicalIdPtr - ) -{ - if (((LogicalIdPtr->Family & AMD_FAMILY_10_HY) != 0) - && ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0)) { - return TRUE; - } else { - return FALSE; - } -} - -/*-----------------------------------------------------------------------------*/ -/** - * This function calculates the memory channel index relative to the - * socket, taking the Die number, the Dct, and the channel. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] Dct - * @param[in] Channel - * - */ -UINT8 -MemNGetSocketRelativeChannelHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 Dct, - IN UINT8 Channel - ) -{ - return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct); -} -/*---------------------------------------------------------------------------- - * LOCAL FUNCTIONS - * - *----------------------------------------------------------------------------*/ - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets or sets a value to a bit field in a PCI register. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] FieldName - Bit Field to be programmed - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -MemNCmnGetSetFieldHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN BIT_FIELD_NAME FieldName, - IN UINT32 Field - ) -{ - TSEFO Address; - PCI_ADDR PciAddr; - UINT8 Type; - UINT8 IsLinked; - UINT32 Value; - UINT32 Highbit; - UINT32 Lowbit; - UINT32 Mask; - - Value = 0; - if (FieldName < BFEndOfList) { - Address = NBPtr->NBRegTable[FieldName]; - if (Address) { - Lowbit = TSEFO_END (Address); - Highbit = TSEFO_START (Address); - Type = (UINT8) TSEFO_TYPE (Address); - IsLinked = (UINT8) TSEFO_LINKED (Address); - - // If Fn2 and DCT1 selected, set Address to be 1xx - if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { - if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { - Address |= 0x0100; - } - } - - ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported - - if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { - // Special DCT Phy access - Address &= 0x0FFFFFFF; - Lowbit = 0; - Highbit = 16; - IsLinked = 0; - } else { - // Normal DCT Phy access - Address = TSEFO_OFFSET (Address); - } - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; - PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; - PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; - Address = PciAddr.AddressValue; - LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); - } else { - IDS_ERROR_TRAP; - } - - if (IsSet) { - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32)0xFFFFFFFF; - } - Value &= ~(Mask << Lowbit); - Value |= (Field & Mask) << Lowbit; - - if (Type == NB_ACCESS) { - PciAddr.AddressValue = Address; - LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); - if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && - (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); - } - } else if (Type == DCT_PHY_ACCESS) { - MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else if (Type == DCT_EXTRA) { - MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); - MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); - } else { - IDS_ERROR_TRAP; - } - if (IsLinked) { - MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); - } - } else { - Value = Value >> Lowbit; // Shift - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - if ((Highbit - Lowbit) != 31) { - Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); - } - if (IsLinked) { - Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); - } - } - } - } else { - IDS_ERROR_TRAP; // Invalid bit field index - } - return Value; -} - - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes bit field translation table - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in,out] NBRegTable[] - Pointer to the bit field data structure - * - */ - -VOID -InitNBRegTableHy ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT TSEFO NBRegTable[] - ) -{ - UINT16 i; - - // Allocate heap for NB register table - if (!MemNAllocateNBRegTableNb (NBPtr, NbRegTabHY)) { - return; // escape if fails - } - NBRegTable = NBPtr->NBRegTable; - - for (i = 0; i < BFEndOfList; i++) { - NBRegTable[i] = 0; - } - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFReserved00B); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFReserved001); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 12, 12, BFEnSplitDctLimits); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 24, 22, BFPrefFourConf); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 27, 25, BFPrefFiveConf); - - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); - MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn); - - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); - - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); - - LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); - LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); - LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); - -} |