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-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c13
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h7
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h36
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c7
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h5
-rw-r--r--src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c5
12 files changed, 47 insertions, 56 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
index fcd149b5ee..7cd57a1de3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 00:59:55 -0700 (Wed, 05 Jan 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h
index ffa5584864..27c87684b8 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 00:59:55 -0700 (Wed, 05 Jan 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
index b47960e106..dba9b71292 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55374 $ @e \$Date: 2011-06-20 17:29:27 -0600 (Mon, 20 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
index 528d4ba0a4..0450263914 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
index 4a83c76e25..df868ffcad 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
@@ -86,11 +85,11 @@ GetF15CacheInfo (
*----------------------------------------------------------------------------------------
*/
#define MEM_TRAINING_BUFFER_SIZE 16384
-#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFF
-#define VAR_MTRR_MASK_CP 0x0000FFFFFFFEFFFF
+#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFFul
+#define VAR_MTRR_MASK_CP 0x0000FFFFFFFEFFFFul
-#define HEAP_BASE_MASK_CP 0x0000FFFFFFFEFF00
-#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFF
+#define HEAP_BASE_MASK_CP 0x0000FFFFFFFEFF00ul
+#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFFul
#define SHARED_MEM_SIZE 0
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
index 0582a9c4b9..90c2ca543f 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c
@@ -9,12 +9,12 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,7 +38,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h
index a5a021f111..f7894ffc25 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 44737 $ @e \$Date: 2011-01-05 00:59:55 -0700 (Wed, 05 Jan 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h
index ae613bee9b..ece2f364e2 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h
@@ -7,13 +7,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 56273 $ @e \$Date: 2011-07-11 12:53:52 -0600 (Mon, 11 Jul 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,7 +37,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
@@ -63,7 +62,9 @@
*/
/// Power Check Error Data
typedef struct {
+ UINT8 SocketNumber; ///< Socket Number
UINT8 HwPstateNumber; ///< Number of hardware P-states
+ UINT8 AllowablePstateNumber; ///< Number of allowable P-states
UINT8 NumberOfBoostStates; ///< Number of boosted P-states
UINT8 NumberOfSwPstatesDisabled; ///< Number of software P-states disabled
} PWRCHK_ERROR_DATA;
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h
index aba4b41a29..ae3a81a8b3 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h
@@ -7,13 +7,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 52710 $ @e \$Date: 2011-05-10 15:58:53 -0600 (Tue, 10 May 2011) $
+ * @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,7 +37,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
@@ -51,10 +50,10 @@
/* Last Branch From IP Register 0x000001DB */
-#define MSR_BR_FROM 0x000001DB
+#define MSR_BR_FROM 0x000001DBul
/* P-state Current Limit Register 0xC0010061 */
-#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061 // F15 Shared
+#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F15 Shared
/// Pstate Current Limit MSR Register
typedef struct {
@@ -66,7 +65,7 @@ typedef struct {
/* P-state Control Register 0xC0010062 */
-#define MSR_PSTATE_CTL 0xC0010062 // F15 Shared
+#define MSR_PSTATE_CTL 0xC0010062ul // F15 Shared
/// Pstate Control MSR Register
typedef struct {
@@ -76,7 +75,7 @@ typedef struct {
/* P-state Status Register 0xC0010063 */
-#define MSR_PSTATE_STS 0xC0010063
+#define MSR_PSTATE_STS 0xC0010063ul
/// Pstate Status MSR Register
typedef struct {
@@ -86,14 +85,14 @@ typedef struct {
/* P-state Registers 0xC001006[B:4] */
-#define MSR_PSTATE_0 0xC0010064
-#define MSR_PSTATE_1 0xC0010065
-#define MSR_PSTATE_2 0xC0010066
-#define MSR_PSTATE_3 0xC0010067
-#define MSR_PSTATE_4 0xC0010068
-#define MSR_PSTATE_5 0xC0010069
-#define MSR_PSTATE_6 0xC001006A
-#define MSR_PSTATE_7 0xC001006B
+#define MSR_PSTATE_0 0xC0010064ul
+#define MSR_PSTATE_1 0xC0010065ul
+#define MSR_PSTATE_2 0xC0010066ul
+#define MSR_PSTATE_3 0xC0010067ul
+#define MSR_PSTATE_4 0xC0010068ul
+#define MSR_PSTATE_5 0xC0010069ul
+#define MSR_PSTATE_6 0xC001006Aul
+#define MSR_PSTATE_7 0xC001006Bul
#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
@@ -108,7 +107,7 @@ typedef struct {
/* C-state Address Register 0xC0010073 */
-#define MSR_CSTATE_ADDRESS 0xC0010073
+#define MSR_CSTATE_ADDRESS 0xC0010073ul
/// C-state Address MSR Register
typedef struct {
@@ -146,6 +145,7 @@ typedef struct {
/* Hardware thermal control register F3x64 */
#define HTC_REG 0x64
+#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
/// Hardware Thermal Control PCI Register
typedef struct {
@@ -153,8 +153,8 @@ typedef struct {
UINT32 :3; ///< Reserved
UINT32 HtcAct:1; ///< HTC Active State
UINT32 HtcActSts:1; ///< HTC Active Status
- UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
- UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
+ UINT32 PslApicHiEn:1; ///< P-state limit higher APIC interrupt enable
+ UINT32 PslApicLoEn:1; ///< P-state limit lower APIC interrupt enable
UINT32 :8; ///< Reserved
UINT32 HtcTmpLmt:7; ///< HTC temperature limit
UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
index 55b6a052ab..b1aa92b6ba 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.c
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 54901 $ @e \$Date: 2011-06-13 21:51:47 -0600 (Mon, 13 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
@@ -1021,7 +1020,7 @@ F15HtPhyOverrideDllCompensation (
OptionMultiSocketConfiguration.GetCurrPciAddr (&StartingCapabilitySet, StdHeader);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Check if the hardware reported any compensation values.
IsEarlyRevProcessor = (BOOLEAN) ((Data == 0) ? TRUE : FALSE);
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h
index e4210373b4..f7d6bb630b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Utilities.h
@@ -9,13 +9,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
index d969d66ab2..2f8a90539d 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
@@ -7,13 +7,13 @@
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x15
- * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $
+ * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
******************************************************************************
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,7 +37,6 @@
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
******************************************************************************
*/