diff options
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR')
41 files changed, 0 insertions, 20532 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c deleted file mode 100644 index 5863af857b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c +++ /dev/null @@ -1,186 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi C6 C-state feature support functions. - * - * Provides the functions necessary to initialize the C6 feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuFeatures.h" -#include "cpuC6State.h" -#include "cpuApicUtilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "OptionFamily15hEarlySample.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_C6_SUPPORT F15OrEarlySampleC6Support; -extern F15_OR_ES_MCU_PATCH F15OrEarlySampleLoadMcuPatch; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] Socket This core's zero-based socket number. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE C6 state is supported. - * @retval FALSE C6 state is not supported. - * - */ -BOOLEAN -STATIC -F15OrIsC6Supported ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT32 Socket, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsEnabled; - - IsEnabled = TRUE; - IsEnabled = IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader); - - F15OrEarlySampleC6Support.F15OrIsC6SupportedHook (&IsEnabled, StdHeader); - - return IsEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable C6 on a family 15h CPU. - * - * @param[in] C6Services Pointer to this CPU's C6 family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeC6 ( - IN C6_FAMILY_SERVICES *C6Services, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 PciMask; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - // Initialize F4x118 - // bits[24] PwrGateEnCstAct1 = 1 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_CTRL1_REG; - LocalPciRegister = 0x01000000; - PciMask = 0xFFFFFFFF; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, PciMask, LocalPciRegister, StdHeader); - } - - return AGESA_SUCCESS; -} - -/** - * Reload microcode patch after memory is initialized. - * - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrReloadMicrocodePatchAfterMemInit ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader); -} - -CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support = -{ - 0, - F15OrIsC6Supported, - F15OrInitializeC6, - F15OrReloadMicrocodePatchAfterMemInit -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c deleted file mode 100644 index f6c9f5f0c1..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c +++ /dev/null @@ -1,183 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 CPB Initialization - * - * Enables core performance boost. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/F15/OR - * @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuFeatures.h" -#include "cpuCpb.h" -#include "F15PackageType.h" -#include "OptionFamily15hEarlySample.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_CPB_SUPPORT F15OrEarlySampleCpbSupport; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for checking whether or not CPB is supported. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval TRUE CPB is supported. - * @retval FALSE CPB is not supported. - * - */ -BOOLEAN -STATIC -F15OrIsCpbSupported ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - BOOLEAN IsEnabled; - - IsEnabled = TRUE; - - GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - IsEnabled = (BOOLEAN) (((CPB_CTRL_REGISTER *) (&CpbControl))->NumBoostStates != 0); - - F15OrEarlySampleCpbSupport.F15OrIsCpbSupportedHook (&IsEnabled, StdHeader); - - return IsEnabled; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * BSC entry point for for enabling Core Performance Boost. - * - * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. - * - * @param[in] CpbServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] EntryPoint Current CPU feature dispatch point. - * @param[in] Socket Zero based socket number to check. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeCpb ( - IN CPB_FAMILY_SERVICES *CpbServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN UINT64 EntryPoint, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpbControl; - UINT32 Module; - UINT32 PackageType; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_S3_LATE_RESTORE_END)) != 0) { - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - PackageType = LibAmdGetPackageType (StdHeader); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CPB_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); - if (PackageType == PACKAGE_TYPE_AM3r2) { - ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1; - } else { - if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { - ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 1; - } - } - LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); - } - } - return AGESA_SUCCESS; -} - -CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport = -{ - 0, - F15OrIsCpbSupported, - F15OrInitializeCpb -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c deleted file mode 100644 index afcea1ddd8..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +++ /dev/null @@ -1,834 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 OR early sample support. - * - * Provides the code and data required to support pre-production silicon. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "F15OrUtilities.h" -#include "cpuF15Utilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -typedef union { - UINT64 RawData; - PATCH_LOADER_MSR BitFields; -} PATCH_LOADER; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrHtcInitEarlySampleHook ( - IN OUT UINT32 *HtcRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrIsCpbDisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrIsC6DisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrEarlySamplesAvoidNbCyclesStart ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT UINT64 *SavedMsrValue - ); - -VOID -F15OrEarlySamplesAvoidNbCyclesEnd ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT64 *SavedMsrValue - ); - -VOID -F15OrEarlySamplesAfterPatchLoaded ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN BOOLEAN IsPatchLoaded - ); - -BOOLEAN -F15OrEarlySamplesLoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - - - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F15OrB0WeightsInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * D A T A D E C L A R A T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------- - * Early Sample PCI registers - *----------------------------- - */ - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrEarlySamplePciRegisters[] = -{ -// F3x188 - NB Configuration 2 Register -// bit[30] Reserved = 1 Erratum #620, only on OR A0, A1 and B0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_LT_B1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x40000000, // regData - 0x40000000, // regMask - }} - }, -// F3x18C - Reserved -// bit[31] Reserved = 1 Erratum #603, only on OR A0, A1 and B0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_LT_B1 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x18C), // Address - 0x80000000, // regData - 0x80000000, // regMask - }} - }, - -// F3x1B8 - L3 Control 1 -// bit[7] Reserved = 1, Erratum #574 -// bit[29] Reserved = 1, Erratum #574 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x20000080, // regData - 0x20000080, // regMask - }} - }, -// F4x110 - Sample and Residency Timers -// bits[20:13] MinResTmr = 0x64 - { - PciRegister, - { - AMD_FAMILY_15_OR, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address - 0x000C8000, // regData - 0x001FE000, // regMask - }} - }, -// F4x1A0 - Reserved -// bits[31:0] Reserved = 4 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A0), // Address - 0x00000004, // regData - 0xFFFFFFFF, // regMask - }} - }, -// F4x1A4 - Reserved -// bits[31:0] Reserved = 0x24 Erratum #553 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address - 0x00000024, // regData - 0xFFFFFFFF, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable = { - PrimaryCores, - (sizeof (F15OrEarlySamplePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrEarlySamplePciRegisters, -}; - -/*----------------------------- - * Early Sample MSR registers - *----------------------------- - */ - -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleMsrRegisters[] = -{ -// MSR_LS_CFG (0xC0011020) -// bit[0] = 1, Erratum #500 for OR-A0 only -// bit[4] = 1, Erratum #501 for OR-A0 only -// bit[28] DisSS = 1, Erratum #495, #496 for OR-A0 only -// bit[30] = 1, Erratum #544 for OR-A0 only -// bit[62] = 1, Erratum #494 for OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_LS_CFG, // MSR Address - 0x4000000050000011, // OR Mask - 0x4000000050000011, // NAND Mask - }} - }, -// MSR_DC_CFG (0xC0011022) -// bit[13] DisHwPf = 1, Erratum #498, OR-A0 only -// bit[10] = 1, Erratum #575, OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DC_CFG, // MSR Address - 0x0000000000002400, // OR Mask - 0x0000000000002400, // NAND Mask - }} - }, -// MSR_DE_CFG (0xC0011029) -// bit[7:2] = 111111b, Erratum #497, OR-A0 only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_A0 // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DE_CFG, // MSR Address - Shared - 0x00000000000000FC, // OR Mask - 0x00000000000000FC, // NAND Mask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable = { - AllCores, - (sizeof (F15OrEarlySampleMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleMsrRegisters, -}; - -/*----------------------------- - * Early Sample Shared MSR registers - *----------------------------- - */ - -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleSharedMsrRegisters[] = -{ -// MSR_CU_CFG2 (0xC001102A) -// bit[27] = 1, Erratum #572, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000008000000, // OR Mask - 0x0000000008000000, // NAND Mask - }} - }, - -// MSR_CU_CFG3 (0xC001102B) -// bit[34] Reserved = 1, Erratum #568, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG3, // MSR Address - 0x0000000400000000, // OR Mask - 0x0000000400000000, // NAND Mask - }} - }, -// MSR_C001_1070 -// bit[41] = 0, Erratum #597, OR-Ax only - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Ax // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_C001_1070, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0x0000020000000000, // NAND Mask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable = { - CorePairPrimary, - (sizeof (F15OrEarlySampleSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleSharedMsrRegisters, -}; - -/*----------------------------- - * Early Sample Workarounds - *----------------------------- - */ - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleWorkarounds[] = -{ - // HT PHY DLL Compensation setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15HtPhyOverrideDllCompensation, - 0x00000000 - }} - }, - // CPU TDP Limit 2 setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15OrOverrideNodeTdpLimit, - 0x00000000 - }} - }, - // CPU Node TDP Accumulator Throttle Threshold setting for Ax - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_Ax - }, - {AMD_PF_ALL}, - {{ - F15OrOverrideNodeTdpAccumulatorThrottleThreshold, - 0x00000000 - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable = { - PrimaryCores, - (sizeof (F15OrEarlySampleWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F15OrEarlySampleWorkarounds, -}; - -/*----------------------------- - * Early Sample shared MSRs with Special Programming Requirements Table - *----------------------------- - */ - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrEarlySampleSharedMsrWorkarounds[] = -{ - // MSRC001_1072 - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_B0 - }, - {AMD_PF_ALL}, - {{ - F15OrB0WeightsInit, - 0x00000000 - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable = { - CorePairPrimary, - (sizeof (F15OrEarlySampleSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrEarlySampleSharedMsrWorkarounds, -}; - - -CONST UINT32 ROMDATA F15OrB0WeightsTable [] = { - 0x1300005A, //MSRC001_1072_x00 - 0x10ABD100, //MSRC001_1072_x01 - 0xBF1A1A44, //MSRC001_1072_x02 - 0xC4DABEA4, //MSRC001_1072_x03 - 0x147B7B6A, //MSRC001_1072_x04 - 0x320C0C00, //MSRC001_1072_x05 - 0xE6D6C6DC, //MSRC001_1072_x06 - 0x00911C06, //MSRC001_1072_x07 - 0x1F473727, //MSRC001_1072_x08 - 0x9FA3A32B, //MSRC001_1072_x09 - 0xDFCFBFAF, //MSRC001_1072_x0A - 0xCFBFAF9F, //MSRC001_1072_x0B - 0x606060DF, //MSRC001_1072_x0C - 0x00000060, //MSRC001_1072_x0D - 0xBAAA9A00, //MSRC001_1072_x0E - 0xFF00DACA, //MSRC001_1072_x0F - 0xFEFEFF64, //MSRC001_1072_x10 - 0x41FCFEFE, //MSRC001_1072_x11 - 0xE14C2F0D, //MSRC001_1072_x12 - 0x95A371EA, //MSRC001_1072_x13 - 0x002EE260, //MSRC001_1072_x14 - 0x00F907D2, //MSRC001_1072_x15 - 0xF9F2A5A5, //MSRC001_1072_x16 - 0x97C100E3, //MSRC001_1072_x17 - 0x91C5B577, //MSRC001_1072_x18 - 0x95C1B1A1, //MSRC001_1072_x19 - 0x68584800, //MSRC001_1072_x1A - 0x67000000, //MSRC001_1072_x1B - 0xB2003109, //MSRC001_1072_x1C - 0x3F8DCDC4, //MSRC001_1072_x1D - 0xD2D4D409, //MSRC001_1072_x1E - 0x090000D2, //MSRC001_1072_x1F - 0x00160000, //MSRC001_1072_x20 - 0x0000E300 //MSRC001_1072_x21 -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Early sample hook point during HTC initialization - * - * @param[in,out] HtcRegister Value of F3x64 to be written. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrHtcInitEarlySampleHook ( - IN OUT UINT32 *HtcRegister, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MsrAddr; - UINT64 Msr; - - if (((HTC_REGISTER *) HtcRegister)->HtcPstateLimit == 0) { - // HtcPstateLimit is set to Pb0. Reprogram it to the minimum enabled P-state with - // with NbPstate = 0 - for (MsrAddr = PS_MAX_REG; MsrAddr > PS_MIN_REG; MsrAddr--) { - LibAmdMsrRead (MsrAddr, &Msr, StdHeader); - if ((((PSTATE_MSR *) &Msr)->PsEnable == 1) && (((PSTATE_MSR *) &Msr)->NbPstate == 0)) { - break; - } - } - ((HTC_REGISTER *) HtcRegister)->HtcPstateLimit = (MsrAddr - PS_MIN_REG); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is CPB supported on this CPU - * - * @param[in,out] IsEnabled Whether or not CPB should be enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrIsCpbDisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR A0, then disable CPB support. - if ((LogicalId.Revision & AMD_F15_OR_A0) != 0) { - *IsEnabled = FALSE; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Is C6 supported on this CPU - * - * @param[in,out] IsEnabled Whether or not C6 should be enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -F15OrIsC6DisabledEarlySample ( - IN OUT BOOLEAN *IsEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR A0, then disable C6 support. - if ((LogicalId.Revision & AMD_F15_OR_A0) != 0) { - *IsEnabled = FALSE; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Update the weights for affected OR B0 CPUs. - * - * This function implements a workaround for OR B0 when applicable. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrB0WeightsInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 ProductInfo; - UINT64 LocalMsr; - PCI_ADDR PciAddress; - - if (IsWarmReset (StdHeader)) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PRCT_INFO_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); - - if ((ProductInfo & BIT31) == 0) { - for (i = 0; i < ((sizeof F15OrB0WeightsTable) / (sizeof F15OrB0WeightsTable[0])); i++) { - LocalMsr = (((((UINT64) F15OrB0WeightsTable[i]) << 32) | i) | BIT14); - LibAmdMsrWrite (0xC0011072, &LocalMsr, StdHeader); - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround to avoid patch loading from causing NB cycles - * - * - * @param[in,out] StdHeader - Config handle for library and services. - * @param[in,out] SavedMsrValue - Saved a MSR value - * - */ -VOID -F15OrEarlySamplesAvoidNbCyclesStart ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT UINT64 *SavedMsrValue - ) -{ - UINT64 MsrValue; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - // Check if this CPU is OR Ax, expected fix in OR-B0 - if ((LogicalId.Revision & AMD_F15_OR_Ax) != 0) { - // Workaround for F15 OR-Ax workaround to avoid patch loading from causing NB cycles - // Start - Set MSR C001_102A [8] - LibAmdMsrRead (MSR_BU_CFG2, SavedMsrValue, StdHeader); - MsrValue = *SavedMsrValue | BIT8; - LibAmdMsrWrite (MSR_BU_CFG2, &MsrValue, StdHeader); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround to avoid patch loading from causing NB cycles - * - * - * @param[in,out] StdHeader - Config handle for library and services. - * @param[in] SavedMsrValue - Saved a MSR value - * - */ -VOID -F15OrEarlySamplesAvoidNbCyclesEnd ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN UINT64 *SavedMsrValue - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_OR_Ax) != 0) { - // Restore Workaround for F15 OR-Ax workaround to avoid patch loading from causing NB cycles - // End - Restore MSR C001_102A - LibAmdMsrWrite (MSR_BU_CFG2, SavedMsrValue, StdHeader); - } - -} - -/* -----------------------------------------------------------------------------*/ -/** - * Workaround for Ax processors after patch is loaded. - * - * - * @param[in] StdHeader - Config handle for library and services. - * @param[in] IsPatchLoaded - Is patch loaded - * - */ -VOID -F15OrEarlySamplesAfterPatchLoaded ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN BOOLEAN IsPatchLoaded - ) -{ - UINT64 MsrValue; - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - - // MSR C001_1023[4:3] = 11b - // Erratum #502, OR-A0 only after microcode patch has been loaded - if (((LogicalId.Revision & AMD_F15_OR_A0) != 0) && (IsPatchLoaded)) { - LibAmdMsrRead (MSR_CU_CFG, &MsrValue, StdHeader); - MsrValue |= 0x18; - LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader); - } - - // Erratum #590, OR-A1 only, if any patch is applied - // MSR C001_0028 = 0x2E00_0080 - // MSR C001_0029 = 0xFE00_0080 - // MSR C001_002C = 0x0400_1029 - if (((LogicalId.Revision & AMD_F15_OR_A1) != 0) && (IsPatchLoaded)) { - MsrValue = 0x2E000080; - LibAmdMsrWrite (0xC0010028, &MsrValue, StdHeader); - - MsrValue = 0xFE000080; - LibAmdMsrWrite (0xC0010029, &MsrValue, StdHeader); - - MsrValue = 0x04001029; - LibAmdMsrWrite (0xC001002C, &MsrValue, StdHeader); - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor. - * - * Then reads the patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * @param[in] StdHeader - Config handle for library and services. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocodePatch ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PatchNumber; - UINT8 TotalPatches; - UINT16 ProcessorEquivalentId; - BOOLEAN Status; - MICROCODE_PATCH **MicrocodePatchPtr; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - Status = FALSE; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - // Get the patch pointer - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); - - IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader); - - // Get the processor microcode path equivalent ID - if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) { - // parse the patch table to see if we have one for the current cpu - for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) { - if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) { - if (F15OrEarlySamplesLoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) { - Status = TRUE; - } else { - PutEventLog (AGESA_ERROR, - CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, - 0, 0, 0, 0, StdHeader); - } - break; // Once we find a microcode patch that matches the processor, exit the for loop - } - } - } - } - return Status; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * F15OrEarlySamplesLoadMicrocode - * - * Update microcode patch in current processor, then reads the - * patch id, and compare it to the expected, in the Microprocessor - * patch block. - * - * Note: This is a special version of the normal LoadMicrocode() - * function which lives in cpuMicrocodePatch.c. This version - * implements a workaround (on Or-B0 only) before applying the - * microcode patch. - * - * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. - * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - * @retval TRUE - Patch Loaded Successfully. - * @retval FALSE - Patch Did Not Get Loaded. - * - */ -BOOLEAN -F15OrEarlySamplesLoadMicrocode ( - IN MICROCODE_PATCH *MicrocodePatchPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 MicrocodeVersion; - UINT64 MsrData; - PATCH_LOADER PatchLoaderMsr; - CPU_LOGICAL_ID LogicalId; - - // Load microcode patch into CPU - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - PatchLoaderMsr.RawData = (UINT64)(intptr_t) MicrocodePatchPtr; - PatchLoaderMsr.BitFields.SBZ = 0; - // Check if this CPU is OR-B0, expected fix in OR-B1 - if ((LogicalId.Revision & AMD_F15_OR_B0) != 0) { - LibAmdMsrRead (MSR_BR_FROM, &MsrData, StdHeader); - } - - LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader); - - // Do ucode patch Authentication - // Read microcode version back from CPU, determine if - // it is the same patch level as contained in the source - // microprocessor patch block passed in - GetMicrocodeVersion (&MicrocodeVersion, StdHeader); - if (MicrocodeVersion == MicrocodePatchPtr->PatchID) { - return (TRUE); - } else { - return (FALSE); - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c deleted file mode 100644 index 78057a7847..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Bulldozer Equivalence Table related data - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "amdlib.h" -#include "cpuRegisters.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST UINT16 ROMDATA CpuF15OrMicrocodeEquivalenceTable[] = -{ - 0x6012, 0x6012, - 0x6011, 0x6011, - 0x6010, 0x6010, - 0x6001, 0x6001, - 0x6000, 0x6000 -}; - -// Unencrypted equivalent -STATIC CONST UINT16 ROMDATA CpuF15OrUnEncryptedMicrocodeEquivalenceTable[] = -{ - 0x6012, 0x6812, - 0x6011, 0x6811, - 0x6010, 0x6810, - 0x6001, 0x6801, - 0x6000, 0x6800 -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate microcode patch equivalent ID table. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] OrEquivalenceTablePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrMicrocodeEquivalenceTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrEquivalenceTablePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrDeCfg; - - LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader); - if ((MsrDeCfg & 0x80000) == 0) { - *NumberOfElements = ((sizeof (CpuF15OrUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *OrEquivalenceTablePtr = CpuF15OrUnEncryptedMicrocodeEquivalenceTable; - } else { - *NumberOfElements = ((sizeof (CpuF15OrMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); - *OrEquivalenceTablePtr = CpuF15OrMicrocodeEquivalenceTable; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c deleted file mode 100644 index 2129d59d07..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c +++ /dev/null @@ -1,833 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Ht Phy tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53592 $ @e \$Date: 2011-05-23 00:27:15 -0600 (Mon, 23 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_REVD_HY_F15HYHTPHYTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// HT Phy T a b l e s -// ------------------------- -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrHtPhyRegisters[] = -{ -// -// All the entries for XmtRdPtr -// -// 0xCF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xCF, // Address - 0x00000D4D, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xDF -// HT_PHY_HT1_FIFO_PTR_OPT_VALUE - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xDF, // Address - 0x00000D4D, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xCF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xCF, // Address - 0x00000A2A, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xDF -// Default for HT3, unless overridden below. - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xDF, // Address - 0x00000A2A, // regData - 0x0000FFFF, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT3, // - 0xC1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT3, // - 0xD1, // Address - 0x08040000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xD1 -// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD1, // Address - 0x04020000, // regData - 0x3FFFC000, // regMask - }} - }, -// 0xC5 -// [7] TxLs23ClkGateEn = 1 - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xC5, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, -// 0xD5 -// [7] TxLs23ClkGateEn = 1 - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xD5, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, - -// -// Deemphasis Settings -// -// HT1: clear any warm reset deemphasis settings. - - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0xC4, // Address - 0x00000000, // regData - 0x0003FC00, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0xD4, // Address - 0x00000000, // regData - 0x0003FC00, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_HT1, // - 0x720C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_HT1, // - 0x730C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - -//deemphasis level Post2[31, 24] Post1[23, 16] Pre1[15, 8] Margin[7, 0] -// No deemphasis 00h 00h 00h 00h -// -3dB postcursor 00h 26h 00h 00h -// -6dB postcursor 00h 40h 00h 00h -// -8dB postcursor 00h 4Dh 00h 00h -// -11dB postcursor 00h 5Ch 00h 00h -// 00h 4Dh 0Fh 00h -// -11dB postcursor with -8dB precursor - - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00000000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00260000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00260000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x00400000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x00400000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x004D0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x004D0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x005C0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x005C0000, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL0_HT3, // - 0x720C, // Address - 0x004D0F00, // regData - 0xFFFFFFFF, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DEEMPHASIS_LEVEL__11_8, - HTPHY_LINKTYPE_SL1_HT3, // - 0x730C, // Address - 0x004D0F00, // regData - 0xFFFFFFFF, // regMask - }} - }, - -// Far-device deemphasis setting DCV[15:10] -// No deemphasis 4Dh -// -2dB postcursor 3Dh -// -3dB postcursor 36h -// -5dB postcursor 2Bh -// -6dB postcursor 27h -// -7dB postcursor 22h -// -8dB postcursor 1Fh -// -9dB postcursor 1Bh -// -11dB postcursor 16h - - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00013400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL_NONE, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00013400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000F400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__2, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000F400, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000D800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__3, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000D800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x0000AC00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__5, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x0000AC00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00009C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__6, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00009C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00008800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__7, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00008800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00007C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__8, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00007C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00006C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__9, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00006C00, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL0_HT3, // - 0xC4, // Address - 0x00005800, // regData - 0x0003FC00, // regMask - }} - }, - { - DeemphasisRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - DCV_LEVEL__11, - HTPHY_LINKTYPE_SL1_HT3, // - 0xD4, // Address - 0x00005800, // regData - 0x0003FC00, // regMask - }} - }, -// 0x520A -// [14:13] AnalogWaitTime = 10b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL0_ALL, // - 0x520A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -// 0x530A -// [14:13] AnalogWaitTime = 10b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_SL1_ALL, // - 0x530A, // Address - 0x00004000, // regData - 0x00006000, // regMask - }} - }, -// 0xE3 -// [7] RoCalEn = 1b - { - HtPhyRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HTPHY_LINKTYPE_ALL, // - 0xE3, // Address - 0x00000080, // regData - 0x00000080, // regMask - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable = { - PrimaryCores, - (sizeof (F15OrHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrHtPhyRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c deleted file mode 100644 index 2f0f43e33a..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c +++ /dev/null @@ -1,187 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Initialize the Family 15h Orochi specific way of running early initialization. - * - * Returns the table of initialization steps to perform at - * AmdInitEarly. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -#include "cpuEarlyInit.h" -#include "OptionFamily15hEarlySample.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrLoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -GetF15OrEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly; -extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; -extern F15_OR_ES_MCU_PATCH F15OrEarlySampleLoadMcuPatch; - -/*---------------------------------------------------------------------------------------- - * D A T A D E C L A R A T I O N S - *---------------------------------------------------------------------------------------- - */ -CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15OrEarlyInitOnCoreTable[] = -{ - {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, - {F15OrLoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET}, - {NULL, 0} -}; - -/*------------------------------------------------------------------------------------*/ -/** - * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a - * processor that uses the standard initialization steps should take. - * - * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[out] Table Table of appropriate init steps for the executing core. - * @param[in] EarlyParams Service Interface structure to initialize. - * @param[in] StdHeader Opaque handle to standard config header. - * - */ -VOID -GetF15OrEarlyInitOnCoreTable ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *Table = F15OrEarlyInitOnCoreTable; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Update microcode patch in current processor for Family15h OR. - * - * This function acts as a wrapper for calling the LoadMicrocodePatch - * routine at AmdInitEarly. - * - * This particualr version implements a workaround to a potential problem caused - * when upgrading the microcode on Orochi B1 processors. - * - * @param[in] FamilyServices The current Family Specific Services. - * @param[in] EarlyParams Service parameters. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrLoadMicrocodePatchAtEarly ( - IN CPU_SPECIFIC_SERVICES *FamilyServices, - IN AMD_CPU_EARLY_PARAMS *EarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrValue; - UINT64 BuCfg2MsrValue; - UINT64 CuCfgMsrValue; - BOOLEAN IsPatchLoaded; - - AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - - F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesStart (StdHeader, &BuCfg2MsrValue); - - // Erratum #655 - // Set MSR C001_1023[1] = 1b, prior to writing to MSR C001_1020 - LibAmdMsrRead (MSR_CU_CFG, &CuCfgMsrValue, StdHeader); - MsrValue = CuCfgMsrValue | BIT1; - LibAmdMsrWrite (MSR_CU_CFG, &MsrValue, StdHeader); - - IsPatchLoaded = F15OrEarlySampleLoadMcuPatch.F15OrUpdateMcuPatchHook (StdHeader); - - // Erratum #655 - // Restore MSR C001_1023[1] = previous setting - LibAmdMsrWrite (MSR_CU_CFG, &CuCfgMsrValue, StdHeader); - - F15OrEarlySampleLoadMcuPatch.F15OrESAvoidNbCyclesEnd (StdHeader, &BuCfg2MsrValue); - F15OrEarlySampleLoadMcuPatch.F15OrESAfterPatchLoaded (StdHeader, IsPatchLoaded); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c deleted file mode 100644 index 6c94521624..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c +++ /dev/null @@ -1,377 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi IO C-state feature support functions. - * - * Provides the functions necessary to initialize the IO C-state feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuFeatures.h" -#include "cpuIoCstate.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "CommonReturns.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrInitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrIsCsdObjGenerated ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable IO Cstate on a family 15h Orochi CPU. - * Implement BIOS Requirements for Initialization of C-states - * - * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeIoCstate ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT32 PciMask; - UINT64 LocalMsrRegister; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { - // Initialize MSRC001_0073[CstateAddr] on each core to a region of - // the IO address map with 8 consecutive available addresses. - LocalMsrRegister = 0; - - ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - - TaskPtr.FuncAddress.PfApTaskI = F15OrInitializeIoCstateOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - - // Initialize F4x128 - // bits[0] CoreCstateMode = 0 - // bits[1] CoreCstatePolicy = 0 - // bits[4:2] HaltCstateIndex = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - LocalPciRegister = 0x00000000; - PciMask = 0xFFFFFFE0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, PciMask, LocalPciRegister, StdHeader); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable CState on a family 15h Orochi core. - * - * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrInitializeIoCstateOnCore ( - IN VOID *CstateBaseMsr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // Initialize MSRC001_0073[CstateAddr] on each core - LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the size of CST object - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data - * @param[in] StdHeader Config Handle for library, services. - * - * @retval CstObjSize Size of CST Object - * - */ -UINT32 -STATIC -F15OrGetAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN GenerateCsdObj; - UINT32 CStateAcpiObjSize; - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - ACPI_CST_GET_INPUT CstGetInput; - - CstGetInput.IoCstateServices = IoCstateServices; - CstGetInput.PlatformConfig = PlatformConfig; - CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize; - - IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) { - CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE; - - // If CSD Object is generated, add the size of CSD Object to the total size of - // CState ACPI Object size - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); - - if (GenerateCsdObj) { - CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE; - } - } - return CStateAcpiObjSize; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to generate the C-State ACPI objects - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] LocalApicId Local Apic Id for each core. - * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrCreateAcpiCstObj ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN UINT8 LocalApicId, - IN OUT VOID **PstateAcpiBufferPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - BOOLEAN GenerateCsdObj; - CST_HEADER_STRUCT *CstHeaderPtr; - CST_BODY_STRUCT *CstBodyPtr; - CSD_HEADER_STRUCT *CsdHeaderPtr; - CSD_BODY_STRUCT *CsdBodyPtr; - IO_CSTATE_FAMILY_SERVICES *FamilyServices; - ACPI_CST_CREATE_INPUT CstInput; - - CstInput.IoCstateServices = IoCstateServices; - CstInput.LocalApicId = LocalApicId; - CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr; - - IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) { - // Read from MSR C0010073 to obtain CstateAddr - LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); - - // Typecast the pointer - CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CST Header - CstHeaderPtr->NameOpcode = NAME_OPCODE; - CstHeaderPtr->CstName_a__ = CST_NAME__; - CstHeaderPtr->CstName_a_C = CST_NAME_C; - CstHeaderPtr->CstName_a_S = CST_NAME_S; - CstHeaderPtr->CstName_a_T = CST_NAME_T; - - // Typecast the pointer - CstHeaderPtr++; - CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; - - // Set CST Body - CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CstBodyPtr->PkgLength = CST_LENGTH; - CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; - CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CstBodyPtr->Count = CST_COUNT; - CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; - CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; - CstBodyPtr->BufferOpcode = BUFFER_OPCODE; - CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; - CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; - CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; - CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; - CstBodyPtr->GdrLength = CST_GDR_LENGTH; - CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; - CstBodyPtr->RegBitWidth = 0x08; - CstBodyPtr->RegBitOffset = 0x00; - CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; - CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; - CstBodyPtr->EndTag = 0x0079; - CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CstBodyPtr->Type = CST_C2_TYPE; - CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; - CstBodyPtr->Latency = 100; - CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CstBodyPtr->Power = 0; - - CstBodyPtr++; - //Update the pointer - *PstateAcpiBufferPtr = CstBodyPtr; - - - // Check whether CSD object should be generated - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); - ASSERT (FamilyServices != NULL); - GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); - - if (GenerateCsdObj) { - CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr; - - // Set CSD Header - CsdHeaderPtr->NameOpcode = NAME_OPCODE; - CsdHeaderPtr->CsdName_a__ = CST_NAME__; - CsdHeaderPtr->CsdName_a_C = CST_NAME_C; - CsdHeaderPtr->CsdName_a_S = CST_NAME_S; - CsdHeaderPtr->CsdName_a_D = CSD_NAME_D; - - CsdHeaderPtr++; - CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr; - - // Set CSD Body - CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE; - CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1; - CsdBodyPtr->PkgElements = 1; - CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; - CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode - CsdBodyPtr->PkgElements2 = 6; - CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; - CsdBodyPtr->NumEntries = 6; - CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; - CsdBodyPtr->Revision = 0; - CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; - CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1; - CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL; - CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->NumProcessors = 0x2; - CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE; - CsdBodyPtr->Index = 0x0; - - CsdBodyPtr++; - - // Update the pointer - *PstateAcpiBufferPtr = CsdBodyPtr; - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Routine to check whether CSD object should be created. - * - * @param[in] IoCstateServices IO Cstate services. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE CSD Object should be created. - * @retval FALSE CSD Object should not be created. - * - */ -BOOLEAN -F15OrIsCsdObjGenerated ( - IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - // CSD Object should only be created when there are two cores per compute unit - if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) { - return TRUE; - } - return FALSE; -} - -CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport = -{ - 0, - (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, - F15OrInitializeIoCstate, - F15OrGetAcpiCstObj, - F15OrCreateAcpiCstObj, - F15OrIsCsdObjGenerated -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c deleted file mode 100644 index 1c3b0bd100..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c +++ /dev/null @@ -1,549 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi L3 dependent feature support functions. - * - * Provides the functions necessary to initialize L3 dependent features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "CommonReturns.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuLateInit.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuL3Features.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -#define L3Cache8_0M 0xCCCC - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/** - * The family 15h background scrubber context structure. - * - * These fields need to be saved, modified, then restored - * per die as part of HT Assist initialization. - */ -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :3; ///< Reserved - UINT32 L3Scrub:5; ///< L3 scrub rate - UINT32 :3; ///< Reserved - UINT32 Redirect:1; ///< DRAM scrubber redirect enable - UINT32 :15; ///< Reserved -} F15_SCRUB_CONTEXT; - - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -BOOLEAN -F15OrIsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------- - * EXPORTED FUNCTIONS - * - *---------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports L3 dependent features. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * - * @retval TRUE L3 dependent features are supported. - * @retval FALSE L3 dependent features are not supported. - * - */ -BOOLEAN -STATIC -F15OrIsL3FeatureSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - BOOLEAN IsSupported; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsSupported = FALSE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) { - IsSupported = TRUE; - } - break; - } - } - return IsSupported; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the Probe filter feature - * - * @param[in] L3FeatureServices L3 family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrHtAssistInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 L3CacheParamRegister; - UINT32 PfCtrlRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_CACHE_PARAM_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - ((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - do { - LibAmdPciRead (AccessWidth32, PciAddress, &L3CacheParamRegister, StdHeader); - } while (((L3_CACHE_PARAM_REGISTER *) &L3CacheParamRegister)->L3TagInit != 0); - - PciAddress.Address.Register = PROBE_FILTER_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayHashEn = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFLoIndexHashEn = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFWayNum = 2; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheEn = 0xF; - if ((L3CacheParamRegister & 0xFFFF) == L3Cache8_0M) { - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 1; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 3; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 2; - } else { - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize0 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize1 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize2 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFSubCacheSize3 = 0; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFMode = 2; - ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl = 0; - } - LibAmdPciWrite (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - - do { - LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader); - } while (((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFInitDone != 1); - IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable the ATM Mode feature. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrAtmModeInit ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - PciAddress.Address.Function = FUNC_0; - PciAddress.Address.Register = LTC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((LTC_REGISTER *) &LocalPciRegister)->ATMModeEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_CONTROL_1_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((L3_CONTROL_1_REGISTER *) &LocalPciRegister)->L3ATMModeEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Save the current settings of the scrubbers, and disabled them. - * - * @param[in] L3FeatureServices L3 feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrGetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 ScrubCtrl; - UINT32 ScrubAddr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub; - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub = - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub; - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect = - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn; - - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0; - ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0; - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader); - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Restore the initial settings for the scrubbers. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] ScrubSettings Location to store current L3 scrubber settings. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrSetL3ScrubCtrl ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - - ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = SCRUB_RATE_CTRL_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub; - ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn = - ((F15_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set MSR bits required for L3 feature support on each core. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrHookDisableCache ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN BOOLEAN HtAssistEnabled, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - // This bit is set only if Probe Filter is enabled. - if (HtAssistEnabled) { - LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT42; - LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU is running in the optimal configuration. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is running sub-optimally. - * @retval FALSE HT Assist is running optimally. - * - */ -BOOLEAN -F15OrIsNonOptimalConfig ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsNonOptimal; - BOOLEAN IsMemoryPresent; - UINT32 Module; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - IsNonOptimal = FALSE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) { - IsMemoryPresent = FALSE; - PciAddress.Address.Function = FUNC_2; - PciAddress.Address.Register = DRAM_CFG_HI_REG0; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) { - IsNonOptimal = TRUE; - break; - } - } - - PciAddress.Address.Register = DRAM_CFG_HI_REG1; - - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) { - IsMemoryPresent = TRUE; - if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 0x0a) { - IsNonOptimal = TRUE; - break; - } - } - if (!IsMemoryPresent) { - IsNonOptimal = TRUE; - break; - } - } - } - return IsNonOptimal; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports HT Assist. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE HT Assist is supported. - * @retval FALSE HT Assist cannot be enabled. - * - */ -BOOLEAN -STATIC -F15OrIsHtAssistSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsSupported; - UINT32 CpuCount; - AP_MAILBOXES ApMailboxes; - - IsSupported = FALSE; - - if (PlatformConfig->PlatformProfile.UseHtAssist) { - CpuCount = GetNumberOfProcessors (StdHeader); - ASSERT (CpuCount != 0); - - if (CpuCount == 1) { - GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); - if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) { - IsSupported = TRUE; - } - } else if (CpuCount > 1) { - IsSupported = TRUE; - } - } - return IsSupported; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the input CPU supports ATM Mode. - * - * @param[in] L3FeatureServices L3 Feature family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE ATM Mode is supported. - * @retval FALSE ATM Mode cannot be enabled. - * - */ -BOOLEAN -STATIC -F15OrIsAtmModeSupported ( - IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - BOOLEAN IsSupported; - - IsSupported = TRUE; - - if (!PlatformConfig->PlatformProfile.UseAtmMode) { - IsSupported = FALSE; - } - return IsSupported; -} - -CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features = -{ - 0, - F15OrIsL3FeatureSupported, - F15OrGetL3ScrubCtrl, - F15OrSetL3ScrubCtrl, - (PF_L3_FEATURE_BEFORE_INIT) CommonVoid, - (PF_L3_FEATURE_AFTER_INIT) CommonVoid, - F15OrHookDisableCache, - (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid, - F15OrIsHtAssistSupported, - F15OrHtAssistInit, - F15OrIsNonOptimalConfig, - F15OrIsAtmModeSupported, - F15OrAtmModeInit, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c deleted file mode 100644 index 158cd8011d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c +++ /dev/null @@ -1,120 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Logical ID Table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **OrIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15OrLogicalIdAndRevArray[] = -{ - { - 0x6012, - AMD_F15_OR_B2 - }, - { - 0x6011, - AMD_F15_OR_B1 - }, - { - 0x6010, - AMD_F15_OR_B0 - }, - { - 0x6001, - AMD_F15_OR_A1 - }, - { - 0x6000, - AMD_F15_OR_A0 - } -}; - -VOID -GetF15OrLogicalIdAndRev ( - OUT CONST CPU_LOGICAL_ID_XLAT **OrIdPtr, - OUT UINT8 *NumberOfElements, - OUT UINT64 *LogicalFamily, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF15OrLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); - *OrIdPtr = CpuF15OrLogicalIdAndRevArray; - *LogicalFamily = AMD_FAMILY_15_OR; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c deleted file mode 100644 index c2d8bb9a59..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c +++ /dev/null @@ -1,234 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Low Power P-state Initialization - * - * Enables Low Power P-state. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 54780 $ @e \$Date: 2011-06-12 21:25:20 -0600 (Sun, 12 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "CommonReturns.h" -#include "cpuLowPwrPstate.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine will be run by every cores for enabling low power Pstate. - * - * This function must be run after P-states initialization and before creating ACPI objects - * - * @param[in] LowPwrPstateServices The current CPU's family services. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config handle for library and services. - * - * @retval AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeLowPwrPstate ( - IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 OriginalPstate; - UINT8 PstateMaxVal; - UINT8 CurPstateLimit; - UINT8 PstateToWaitFor; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 PciData; - UINT64 LocalMsrRegister; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - PCI_ADDR PciAddress; - PCI_ADDR IntNode0PciAddress; - AGESA_STATUS IgnoredSts; - - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - FamilySpecificServices = NULL; - OriginalPstate = 0; - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - - // Step 1 --- Read MSR_C001_0063[CurPstate] and store the value in OriginalPstate - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - OriginalPstate = (UINT8) ((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate; - - // Step 2 --- Write 0 to MSR_C001_0062[PstateCmd] - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) 0; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - - // Step 3 --- Wait for MSR_C001_0063[CurPstate] == MSR_C001_0061[CurPstateLimit] - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - CurPstateLimit = (UINT8) ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->CurPstateLimit; - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) CurPstateLimit); - - // Step 4 --- Copy MSR_C001_00[6B:64] pointed to by F3xDC[PstateMaxVal] to MSR_C001_00[6B:64] - // pointed to by F3xDC[PstateMaxVal]+1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PstateMaxVal = (UINT8) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciData)->PstateMaxVal; - // In case that F3xDC[PstateMaxVal] was increased by step 5 during the first time of running this function. - // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable] - while (PstateMaxVal != 0) { - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - break; - } - PstateMaxVal--; - } - - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - LibAmdMsrWrite ((PS_REG_BASE + PstateMaxVal + 1), &LocalMsrRegister, StdHeader); - - // Step 5 --- Increment the value in F3xDC[PstateMaxVal] by 1 - PstateMaxVal++; - if (Core == 0) { - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciData)->PstateMaxVal = PstateMaxVal; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0, PciData, StdHeader); - } - - // Step 6 --- Write 100b to CpuFid from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - // Step 7 --- Write 10b to CpuDid from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - // Step 8 --- Write 0b to PstateEn from MSR_C001_00[6B:64] indexed by F3xDC[PstateMaxVal] - LibAmdMsrRead ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid = 4; - ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid = 2; - ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; - LibAmdMsrWrite ((PS_REG_BASE + PstateMaxVal), &LocalMsrRegister, StdHeader); - - // Step 9 --- If F3x64[HtcTmpLmt] == 0, write 7Fh to F3x64[HtcTmpLmt] - // Step 10 --- Write 1b to F3x64[HtcEn] - GetPciAddress (StdHeader, Socket, 0, &IntNode0PciAddress, &IgnoredSts); - if (Core == 0) { - IntNode0PciAddress.Address.Function = FUNC_3; - IntNode0PciAddress.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - if (((HTC_REGISTER *) &PciData)->HtcTmpLmt == 0) { - ((HTC_REGISTER *) &PciData)->HtcTmpLmt = 0x7F; - } - ((HTC_REGISTER *) &PciData)->HtcEn = 1; - IDS_OPTION_HOOK (IDS_HTC_CTRL, &PciData, StdHeader); - LibAmdPciWrite (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - } - - // Step 11 --- Write OriginalPstate to MSR_C001_0062[PstateCmd] - LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) OriginalPstate; - LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); - - // Step 12 --- If (MSR_C001_0061[CurPstateLimit] > OriginalPstate) - // Wait for (MSR_C001_0063[CurPstate] == MSR_C001_0061[CurPstateLimit]) - // Else - // Wait for (MSR_C001_0063[CurPstate] == OriginalPstate - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - CurPstateLimit = (UINT8) ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->CurPstateLimit; - PstateToWaitFor = (CurPstateLimit > OriginalPstate) ? CurPstateLimit : OriginalPstate; - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) PstateToWaitFor); - - // Step 13 --- Write F3x64[HtcPstateLimit] and F3xA8[PopDownPstate] with the value from - // F3xDC[PstateMaxVal] and exit the sequence - if (Core == 0) { - ((HTC_REGISTER *) &PciData)->HtcPstateLimit = PstateMaxVal; - LibAmdPciWrite (AccessWidth32, IntNode0PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = POPUP_PSTATE_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - ((POPUP_PSTATE_REGISTER *) &PciData)->PopDownPstate = PstateMaxVal; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0, PciData, StdHeader); - } - } - return AGESA_SUCCESS; -} - - -CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport = -{ - 0, - (PF_LOW_PWR_PSTATE_IS_SUPPORTED) CommonReturnTrue, - F15OrInitializeLowPwrPstate -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c deleted file mode 100644 index f878acd0d6..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 06000425 for 6010 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/Or - * @e \$Revision: 53746 $ @e \$Date: 2011-05-24 23:08:53 -0600 (Tue, 24 May 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypted Patch code 06000425 for 6010 and equivalent -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x08, - 0x04, - 0x25, - 0x04, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x10, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x55, - 0xbf, - 0xbd, - 0x55, - 0xea, - 0x96, - 0xd6, - 0xed, - 0x1a, - 0x82, - 0xda, - 0x4a, - 0xdc, - 0xc0, - 0x8a, - 0x21, - 0x02, - 0x4c, - 0x0f, - 0x68, - 0xc4, - 0x31, - 0x74, - 0xa8, - 0x32, - 0xfc, - 0xb3, - 0xad, - 0xbc, - 0x51, - 0x53, - 0x89, - 0x65, - 0xc5, - 0x49, - 0x28, - 0x9f, - 0x9c, - 0xe4, - 0xb8, - 0x90, - 0x02, - 0x27, - 0x30, - 0x5f, - 0x19, - 0xba, - 0x72, - 0x0b, - 0x8c, - 0x78, - 0xcb, - 0x2e, - 0x00, - 0x7c, - 0x2b, - 0x9b, - 0x0a, - 0xa2, - 0xd2, - 0x20, - 0x8b, - 0x6c, - 0xc0, - 0xce, - 0xae, - 0x0e, - 0x8f, - 0xe7, - 0xaf, - 0xc7, - 0x5d, - 0xf9, - 0xcb, - 0x35, - 0x79, - 0xc0, - 0x1e, - 0x33, - 0x5f, - 0x05, - 0x95, - 0x0c, - 0x6f, - 0x43, - 0xc7, - 0x85, - 0x52, - 0xd9, - 0x06, - 0x58, - 0xec, - 0xe7, - 0xdb, - 0x6d, - 0xba, - 0xb4, - 0x5b, - 0x32, - 0xeb, - 0xe4, - 0xb2, - 0xd5, - 0x77, - 0x1c, - 0xe6, - 0x84, - 0xaf, - 0x2c, - 0x12, - 0x18, - 0xf7, - 0x3c, - 0xbf, - 0xa8, - 0x90, - 0xcb, - 0x40, - 0x46, - 0xee, - 0x48, - 0x0c, - 0x53, - 0x80, - 0x9a, - 0x94, - 0x4d, - 0x73, - 0x3e, - 0x2f, - 0x98, - 0xc0, - 0x25, - 0x75, - 0xbd, - 0xe8, - 0x99, - 0x38, - 0xad, - 0xfa, - 0xda, - 0xcf, - 0x3f, - 0xe5, - 0x4b, - 0x38, - 0x76, - 0x3b, - 0xe5, - 0xa2, - 0xef, - 0x38, - 0x11, - 0xbd, - 0x8d, - 0x84, - 0x75, - 0x88, - 0x72, - 0xdd, - 0xd4, - 0xcd, - 0x85, - 0xcd, - 0xd1, - 0xc6, - 0xae, - 0xd1, - 0xc2, - 0xfa, - 0xb1, - 0xc4, - 0xc2, - 0xc9, - 0x35, - 0xc4, - 0xc1, - 0x3a, - 0xbe, - 0xcc, - 0x08, - 0x94, - 0xba, - 0x52, - 0x98, - 0xd6, - 0xd4, - 0x70, - 0x84, - 0x48, - 0x3b, - 0x9d, - 0xfd, - 0x24, - 0x81, - 0x50, - 0xbf, - 0xe2, - 0x2b, - 0xf5, - 0x5f, - 0x3b, - 0x99, - 0x76, - 0x98, - 0xc2, - 0xf2, - 0x36, - 0x1c, - 0x64, - 0xea, - 0xdc, - 0xd7, - 0x10, - 0x0f, - 0x76, - 0xcc, - 0x2c, - 0x9e, - 0x23, - 0x45, - 0x8b, - 0x0f, - 0x4e, - 0x4b, - 0x34, - 0x89, - 0x7d, - 0x5b, - 0x21, - 0x8a, - 0x25, - 0x5b, - 0x69, - 0xe3, - 0xde, - 0xb4, - 0xa9, - 0xf7, - 0x48, - 0x9a, - 0xea, - 0x40, - 0x3c, - 0x9c, - 0x41, - 0x8f, - 0x69, - 0x3c, - 0x10, - 0x6e, - 0xf8, - 0x11, - 0x7c, - 0x73, - 0xe9, - 0x96, - 0xed, - 0x90, - 0x9e, - 0x07, - 0x45, - 0x65, - 0x6b, - 0x68, - 0x5d, - 0x9d, - 0x72, - 0xdb, - 0xb2, - 0xbc, - 0x81, - 0x65, - 0xeb, - 0x84, - 0x33, - 0xdc, - 0xe9, - 0x0f, - 0xd5, - 0x0e, - 0xc8, - 0x5e, - 0x14, - 0x80, - 0x64, - 0x0b, - 0x9e, - 0x46, - 0xde, - 0xbe, - 0x9e, - 0x12, - 0xac, - 0x50, - 0xc4, - 0x33, - 0xce, - 0xf7, - 0xba, - 0xc7, - 0xdf, - 0x43, - 0x09, - 0x9b, - 0xa3, - 0x21, - 0xc5, - 0xe0, - 0x48, - 0xe6, - 0x19, - 0xd8, - 0xa6, - 0x6f, - 0x29, - 0xb3, - 0x0e, - 0xc4, - 0xc6, - 0xe6, - 0xdd, - 0x96, - 0xab, - 0x54, - 0xb9, - 0x80, - 0x73, - 0x61, - 0xe6, - 0x85, - 0x9b, - 0xe5, - 0x00, - 0xfa, - 0xe8, - 0x04, - 0xe5, - 0x33, - 0xfe, - 0x7e, - 0xae, - 0xe7, - 0x55, - 0x53, - 0xe4, - 0x63, - 0x6a, - 0xfa, - 0x76, - 0x9e, - 0x28, - 0x88, - 0xb8, - 0xc6, - 0x75, - 0x4c, - 0xa0, - 0x9f, - 0x01, - 0xf9, - 0x9e, - 0x89, - 0xf6, - 0xce, - 0x91, - 0xbf, - 0x4e, - 0xfe, - 0xbd, - 0x52, - 0xea, - 0xfe, - 0x06, - 0xc5, - 0xad, - 0xcf, - 0xb8, - 0xa0, - 0xec, - 0x78, - 0x4b, - 0xec, - 0x3b, - 0x80, - 0xf4, - 0x84, - 0xbe, - 0x69, - 0x5f, - 0x5e, - 0x7a, - 0x13, - 0x89, - 0x95, - 0x91, - 0x07, - 0x56, - 0xdb, - 0x5d, - 0xfa, - 0x10, - 0xfc, - 0x5d, - 0x99, - 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0x3d, - 0x12, - 0xeb, - 0x30, - 0x91, - 0xaa, - 0x40, - 0x63, - 0x23, - 0xe5, - 0xc2, - 0x83, - 0x1e, - 0xaa, - 0xe1, - 0x78, - 0xd4, - 0x9d, - 0x54, - 0xdc, - 0xb8, - 0xf3, - 0xd8, - 0x24, - 0x5e, - 0xe8, - 0x5b, - 0xcb, - 0x46, - 0x74, - 0x09, - 0x00, - 0xb2, - 0x75, - 0x9a, - 0xcf, - 0x36, - 0x0b, - 0xb6, - 0xfe, - 0xb4, - 0x5d, - 0x1d, - 0xb5, - 0x87, - 0x60, - 0xeb, - 0xba, - 0xba, - 0xe0, - 0x2e, - 0xb8, - 0xa5, - 0x3d, - 0x5b, - 0x4c, - 0xca, - 0x2c, - 0x16, - 0x19, - 0x62, - 0x1e, - 0xa2, - 0xbf, - 0xa9, - 0x68, - 0xde, - 0xbe, - 0x1b, - 0x2c, - 0x61, - 0x8d, - 0x52, - 0x06, - 0xb0, - 0x58, - 0xad, - 0x81, - 0xa6, - 0x1b, - 0x04, - 0x02, - 0xfa, - 0x37, - 0xf1, - 0xd3, - 0x13, - 0xed, - 0x37, - 0x88, - 0x6b, - 0x1f, - 0xc8, - 0x5c, - 0x3c, - 0x41, - 0x1e, - 0x84, - 0x73, - 0xef, - 0xc4, - 0x41, - 0x13, - 0xcf, - 0xae, - 0xcf, - 0xbd, - 0x10, - 0xf7, - 0x5a, - 0x67, - 0x8d, - 0x48, - 0xc0, - 0xae, - 0x3a, - 0x68, - 0xc8, - 0x38, - 0x37, - 0x3c, - 0x22, - 0x9c, - 0x0a, - 0x73, - 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0x83, - 0x1d, - 0x97, - 0x13, - 0x2e, - 0xef, - 0x4f, - 0x76, - 0x26, - 0xea, - 0x22, - 0x06, - 0xc5, - 0xd9, - 0xc0, - 0x62, - 0xce, - 0x68, - 0xde, - 0xc8, - 0xf3, - 0x2f, - 0xb7, - 0xae, - 0xdb, - 0xbc, - 0x37, - 0x8e, - 0x7c, - 0x3f, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c deleted file mode 100644 index 918ef27412..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +++ /dev/null @@ -1,2674 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 0600050D for 6011 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55872 $ @e \$Date: 2011-07-01 09:09:22 -0600 (Fri, 01 Jul 2011) $ - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600050D for 6011 and equivalent - -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x27, - 0x06, - 0x0d, - 0x05, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x11, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x5b, - 0x94, - 0xa0, - 0x0d, - 0x78, - 0xaf, - 0xb3, - 0xa7, - 0x4b, - 0xbb, - 0x6b, - 0x18, - 0x7e, - 0xe0, - 0x91, - 0x2a, - 0x6e, - 0xb5, - 0x40, - 0x6e, - 0x39, - 0x62, - 0x3b, - 0x83, - 0xe9, - 0x47, - 0x50, - 0xba, - 0xb5, - 0x7d, - 0x40, - 0x26, - 0xf6, - 0x46, - 0xbc, - 0x45, - 0x3d, - 0xd6, - 0xa3, - 0xa8, - 0x94, - 0x33, - 0xb9, - 0xd3, - 0xa0, - 0xb5, - 0x50, - 0xe2, - 0x6d, - 0x90, - 0x1e, - 0xc9, - 0x30, - 0x91, - 0x70, - 0x3d, - 0xef, - 0x48, - 0xc1, - 0xc5, - 0x21, - 0x73, - 0x94, - 0x26, - 0xce, - 0x40, - 0xb6, - 0x24, - 0x2c, - 0x33, - 0xf9, - 0x64, - 0x2f, - 0xf7, - 0x6f, - 0xf0, - 0x38, - 0x02, - 0x2e, - 0x4d, - 0xfd, - 0x82, - 0x64, - 0x50, - 0x6d, - 0xf0, - 0xb5, - 0xed, - 0xff, - 0xb1, - 0xb9, - 0x8a, - 0xbc, - 0xab, - 0xf9, - 0x2c, - 0x9c, - 0x99, - 0x36, - 0x79, - 0x07, - 0x80, - 0xf8, - 0xa7, - 0x68, - 0xdd, - 0x06, - 0xbe, - 0xd7, - 0xa3, - 0xe0, - 0x74, - 0x25, - 0x9f, - 0xe5, - 0x9d, - 0xff, - 0xee, - 0x08, - 0x44, - 0x78, - 0x16, - 0x3f, - 0xbe, - 0xa9, - 0xf2, - 0xb1, - 0xd1, - 0x01, - 0x20, - 0x8f, - 0xa7, - 0x82, - 0x75, - 0x96, - 0xed, - 0xbe, - 0x6f, - 0xf4, - 0x76, - 0x4b, - 0xc5, - 0x87, - 0x72, - 0xde, - 0x21, - 0x9f, - 0x6c, - 0xa3, - 0x9f, - 0x37, - 0x9a, - 0xf0, - 0xbb, - 0x6c, - 0x9b, - 0xeb, - 0x9d, - 0xeb, - 0xf9, - 0xe2, - 0x40, - 0x1f, - 0x3b, - 0x7f, - 0x8a, - 0x96, - 0x58, - 0x1f, - 0x80, - 0x75, - 0x19, - 0xb1, - 0xdb, - 0xcc, - 0xbe, - 0x6b, - 0x03, - 0x21, - 0xf3, - 0x30, - 0x50, - 0xe7, - 0x39, - 0x59, - 0x9a, - 0xf5, - 0x58, - 0x6b, - 0x02, - 0xac, - 0x96, - 0xbc, - 0x0e, - 0x79, - 0x99, - 0x6c, - 0xda, - 0x46, - 0xcf, - 0x47, - 0xb4, - 0x54, - 0x7d, - 0x83, - 0x95, - 0x6e, - 0x2d, - 0x76, - 0x44, - 0x59, - 0x1e, - 0x86, - 0x08, - 0xcb, - 0x82, - 0x4d, - 0x83, - 0x85, - 0x24, - 0xe5, - 0x05, - 0x3b, - 0x31, - 0x3d, - 0x19, - 0x10, - 0x49, - 0xb9, - 0xa0, - 0xd2, - 0x97, - 0x46, - 0x19, - 0x2b, - 0xc7, - 0x3f, - 0x01, - 0xda, - 0x36, - 0x5c, - 0x50, - 0xc6, - 0xc5, - 0x75, - 0x2d, - 0x1b, - 0x67, - 0x87, - 0x37, - 0xae, - 0x97, - 0x69, - 0xea, - 0x0b, - 0x03, - 0x3e, - 0x98, - 0x93, - 0x94, - 0xa7, - 0x56, - 0x26, - 0x1b, - 0x1f, - 0xb2, - 0x41, - 0x02, - 0x6d, - 0xd5, - 0xcb, - 0xac, - 0x73, - 0x2f, - 0xcb, - 0xf9, - 0x49, - 0xbb, - 0xa6, - 0x65, - 0x6b, - 0x97, - 0x2c, - 0xd6, - 0x71, - 0xd8, - 0xeb, - 0xbb, - 0x77, - 0x7f, - 0xfe, - 0x7c, - 0xc9, - 0x95, - 0xbd, - 0xe0, - 0x0d, - 0x7c, - 0xea, - 0x13, - 0x8d, - 0xb4, - 0xbd, - 0x9f, - 0xa6, - 0x70, - 0x9a, - 0x72, - 0x67, - 0x21, - 0xe5, - 0xf5, - 0xb9, - 0x92, - 0x18, - 0xe6, - 0xd2, - 0x48, - 0xfb, - 0x9b, - 0xae, - 0xd9, - 0x2b, - 0x78, - 0x42, - 0xff, - 0x84, - 0x51, - 0x89, - 0x5c, - 0xab, - 0x46, - 0x8c, - 0x77, - 0x11, - 0x45, - 0x43, - 0x7d, - 0x17, - 0x2c, - 0x10, - 0xf6, - 0x81, - 0x28, - 0x1b, - 0xc4, - 0x4b, - 0x21, - 0xe1, - 0x75, - 0x22, - 0x80, - 0x74, - 0xe7, - 0x2b, - 0x7b, - 0x09, - 0xf6, - 0x64, - 0x05, - 0x24, - 0x87, - 0x4a, - 0xe5, - 0xa5, - 0x94, - 0x96, - 0x1d, - 0x16, - 0x2d, - 0xec, - 0x07, - 0x55, - 0x5e, - 0x0c, - 0xd5, - 0x89, - 0xb1, - 0xd5, - 0x85, - 0xe9, - 0x9d, - 0x85, - 0x68, - 0x3a, - 0x9d, - 0xc0, - 0x30, - 0xc0, - 0xcf, - 0x44, - 0xe0, - 0x3a, - 0x7f, - 0x4c, - 0xc7, - 0x9c, - 0x3e, - 0x1a, - 0x0f, - 0xfc, - 0x3e, - 0x46, - 0xd3, - 0x88, - 0x93, - 0x83, - 0x39, - 0x8e, - 0x9a, - 0xd1, - 0xe3, - 0x98, - 0xfd, - 0x79, - 0xeb, - 0x3d, - 0xe4, - 0x3f, - 0xc7, - 0x49, - 0xd9, - 0xec, - 0xe5, - 0x25, - 0x94, - 0xb0, - 0x46, - 0xaf, - 0x04, - 0x0b, - 0x66, - 0x9e, - 0x01, - 0x1c, - 0xe2, - 0xd9, - 0xf2, - 0xf6, - 0x77, - 0x97, - 0x5a, - 0xe2, - 0xba, - 0x40, - 0x82, - 0x33, - 0x6a, - 0x6f, - 0x92, - 0xae, - 0xa6, - 0x03, - 0xda, - 0xc2, - 0xc5, - 0x4c, - 0xfe, - 0x19, - 0x52, - 0xde, - 0xea, - 0x35, - 0xd9, - 0x46, - 0xd9, - 0x90, - 0xfe, - 0x72, - 0x9e, - 0xfd, - 0x22, - 0x9e, - 0x2b, - 0xca, - 0xa2, - 0x98, - 0x25, - 0x74, - 0x4b, - 0x84, - 0x2a, - 0xde, - 0xd6, - 0x2d, - 0x12, - 0xb0, - 0xba, - 0xd8, - 0xc5, - 0xe9, - 0x6e, - 0x24, - 0x1f, - 0x53, - 0xee, - 0x2a, - 0x26, - 0xe1, - 0x1f, - 0xd6, - 0x3d, - 0xcd, - 0xc9, - 0xd5, - 0xde, - 0xdc, - 0x7d, - 0x30, - 0x81, - 0xdc, - 0x3d, - 0x62, - 0x7a, - 0xa4, - 0x9c, - 0x52, - 0x2e, - 0xb7, - 0xfa, - 0x9c, - 0x9b, - 0x4d, - 0x32, - 0xb2, - 0xbd, - 0xdf, - 0x21, - 0xa0, - 0x0b, - 0x09, - 0x44, - 0xc5, - 0xea, - 0x7a, - 0xb2, - 0x3b, - 0x75, - 0x74, - 0x4c, - 0x5e, - 0x77, - 0x88, - 0xfe, - 0x68, - 0x9d, - 0x64, - 0x24, - 0x18, - 0x74, - 0x8d, - 0xf7, - 0x92, - 0xf6, - 0xd9, - 0x92, - 0x85, - 0xce, - 0x3f, - 0xf7, - 0x00, - 0xdc, - 0x2c, - 0x90, - 0xfc, - 0x4c, - 0xc0, - 0xf5, - 0xf3, - 0x75, - 0x55, - 0x94, - 0x33, - 0xd8, - 0xdc, - 0x3e, - 0x93, - 0x66, - 0xb7, - 0xee, - 0x64, - 0x29, - 0xb5, - 0xf8, - 0x50, - 0xbf, - 0x08, - 0xa0, - 0xfd, - 0x2c, - 0x12, - 0xa7, - 0x45, - 0xae, - 0x45, - 0xaf, - 0x26, - 0x88, - 0xe1, - 0x6b, - 0xa5, - 0x75, - 0xac, - 0xf0, - 0x61, - 0x6d, - 0x09, - 0x95, - 0xba, - 0xc4, - 0x12, - 0xfe, - 0x0d, - 0xf5, - 0x32, - 0xd4, - 0xde, - 0xa8, - 0x29, - 0x0d, - 0x69, - 0xda, - 0x37, - 0x0e, - 0x2d, - 0xdd, - 0x59, - 0xff, - 0x6b, - 0x42, - 0x76, - 0x11, - 0x9f, - 0x39, - 0x30, - 0x84, - 0xf5, - 0xb8, - 0xd7, - 0x02, - 0x82, - 0xf9, - 0x0b, - 0xcf, - 0x4e, - 0xb6, - 0x95, - 0x8f, - 0xab, - 0x21, - 0xe7, - 0x69, - 0x1d, - 0xbb, - 0x96, - 0x77, - 0xfd, - 0xc9, - 0x30, - 0x05, - 0xa8, - 0x8c, - 0x16, - 0xd8, - 0xf9, - 0xe3, - 0x75, - 0xe8, - 0x87, - 0x8e, - 0xfc, - 0x8e, - 0xe5, - 0x32, - 0x86, - 0x57, - 0x85, - 0x64, - 0xfc, - 0x78, - 0xcd, - 0x24, - 0x32, - 0xe8, - 0xa4, - 0xd3, - 0x5f, - 0x87, - 0x5a, - 0x18, - 0xcf, - 0x4b, - 0x61, - 0x58, - 0x0d, - 0xde, - 0x2d, - 0xa3, - 0x36, - 0x46, - 0xd0, - 0x05, - 0x06, - 0x86, - 0x23, - 0xcf, - 0xb5, - 0x2b, - 0x12, - 0xb0, - 0x3b, - 0x92, - 0x36, - 0xbb, - 0x71, - 0xcf, - 0x05, - 0x9c, - 0x68, - 0xf8, - 0x17, - 0x2b, - 0x3c, - 0xb4, - 0x30, - 0xf1, - 0xad, - 0x21, - 0x05, - 0xf1, - 0x8f, - 0x09, - 0xbb, - 0x71, - 0x95, - 0xf8, - 0x5b, - 0x2e, - 0x78, - 0x02, - 0xdd, - 0xcf, - 0x20, - 0x01, - 0x45, - 0xf1, - 0xf0, - 0xc3, - 0x08, - 0x56, - 0xfe, - 0x00, - 0x3a, - 0x2f, - 0xc7, - 0xa1, - 0x92, - 0x37, - 0x47, - 0xf7, - 0x70, - 0xbb, - 0xc2, - 0x1f, - 0x4b, - 0x30, - 0x82, - 0xf1, - 0xa8, - 0x56, - 0x53, - 0x21, - 0x21, - 0x24, - 0xfb, - 0x57, - 0x13, - 0x92, - 0x2c, - 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0xa7, - 0xaa, - 0xee, - 0xfd, - 0x5d, - 0xf9, - 0x0d, - 0x8f, - 0x16, - 0xf0, - 0x46, - 0x63, - 0x09, - 0xce, - 0x16, - 0x02, - 0xc8, - 0x62, - 0x44, - 0x46, - 0x92, - 0x57, - 0xea, - 0xe4, - 0x8c, - 0x3b, - 0x39, - 0xa9, - 0x5f, - 0xdb, - 0xf2, - 0x06, - 0x04, - 0x9c, - 0x5b, - 0xf7, - 0x46, - 0x2c, - 0xbb, - 0x03, - 0xd6, - 0x22, - 0x00, - 0xe6, - 0xd2, - 0x46, - 0x3a, - 0xc0, - 0x1c, - 0xdc, - 0x2c, - 0xaf, - 0x2d, - 0x15, - 0x19, - 0x0d, - 0xa6, - 0x99, - 0x4d, - 0x21, - 0x5b, - 0xe2, - 0x47, - 0x47, - 0xea, - 0xad, - 0x5d, - 0x02, - 0x8f, - 0x4c, - 0xd7, - 0x0e, - 0xb5, - 0xad, - 0xf3, - 0x93, - 0xb8, - 0x6e, - 0x52, - 0x9b, - 0x2b, - 0x4f, - 0xdc, - 0xff, - 0xd4, - 0xbb, - 0xa6, - 0xc6, - 0x37, - 0x37, - 0x9d, - 0x3d, - 0xd7, - 0x05, - 0xad, - 0xc0, - 0xca, - 0xea, - 0xae, - 0x7e, - 0x09, - 0x6c, - 0x82, - 0xab, - 0x7f, - 0x21, - 0xab, - 0xf0, - 0x33, - 0x87, - 0xd9, - 0x02, - 0xc0, - 0x04, - 0x30, - 0x2a, - 0x63, - 0xbe, - 0x70, - 0x8b, - 0x8a, - 0xb3, - 0x7d, - 0xb9, - 0x6c, - 0x02, - 0x2a, - 0x37, - 0xa9, - 0x65, - 0x53, - 0xd5, - 0x1b, - 0x09, - 0x09, - 0xc9, - 0xe1, - 0x3e, - 0x38, - 0xf2, - 0x17, - 0xba, - 0x99, - 0x65, - 0x61, - 0xb2, - 0xfd, - 0xbf, - 0xc4, - 0x25, - 0xf0, - 0x98, - 0xec, - 0xab, - 0xad, - 0x4d, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c deleted file mode 100644 index 8c011ad785..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Or Microcode patch. - * - * F15Or Microcode Patch rev 06000624 for 6012 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60770 $ @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 06000624 for 6012 and equivalent - -CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc [IDS_PAD_4K] = -{ - 0x11, - 0x20, - 0x21, - 0x10, - 0x24, - 0x06, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x12, - 0x60, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x53, - 0x66, - 0x89, - 0xc4, - 0x38, - 0x90, - 0x15, - 0xbf, - 0xec, - 0xee, - 0x70, - 0xc6, - 0xdb, - 0x18, - 0x66, - 0x84, - 0xa6, - 0x2f, - 0x3a, - 0xe5, - 0x2e, - 0x91, - 0x6c, - 0x46, - 0x2f, - 0x1a, - 0xdb, - 0x02, - 0xdc, - 0x29, - 0x17, - 0xbd, - 0x66, - 0x14, - 0x13, - 0x10, - 0xba, - 0x9a, - 0xa7, - 0x1d, - 0x79, - 0x73, - 0x29, - 0x07, - 0x12, - 0x9d, - 0xaf, - 0x3d, - 0xdd, - 0x7d, - 0xa5, - 0x44, - 0x88, - 0x88, - 0x5b, - 0x0b, - 0xfd, - 0x07, - 0xd1, - 0x94, - 0x4f, - 0xdf, - 0xa2, - 0x0c, - 0xa4, - 0x2d, - 0x61, - 0x77, - 0x3d, - 0x0b, - 0x37, - 0xb8, - 0x21, - 0x82, - 0xe4, - 0xdb, - 0x21, - 0xc7, - 0x10, - 0x67, - 0x4f, - 0x68, - 0x90, - 0xec, - 0x65, - 0xe5, - 0x0e, - 0x49, - 0x91, - 0x85, - 0xaa, - 0x07, - 0x98, - 0xbe, - 0x64, - 0xaf, - 0x48, - 0xb7, - 0x17, - 0x5f, - 0xcf, - 0x34, - 0x4b, - 0x2f, - 0x9f, - 0x9c, - 0xf0, - 0xcd, - 0xfa, - 0xb2, - 0x29, - 0x92, - 0xa0, - 0xc8, - 0x80, - 0xcf, - 0x03, - 0x69, - 0x8a, - 0xb0, - 0x70, - 0x8d, - 0x1a, - 0x9c, - 0xab, - 0xe9, - 0x0b, - 0x69, - 0x3d, - 0xc5, - 0x73, - 0x40, - 0xab, - 0x2c, - 0x50, - 0xeb, - 0x7c, - 0x66, - 0x4b, - 0x36, - 0x71, - 0x18, - 0x38, - 0xf3, - 0x02, - 0x87, - 0x89, - 0x92, - 0xc6, - 0xae, - 0x04, - 0x29, - 0xa9, - 0x26, - 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0x5c, - 0x9a, - 0x07, - 0xf1, - 0xec, - 0x96, - 0x9c, - 0xdd, - 0x0c, - 0x8e, - 0xd9, - 0x8a, - 0x81, - 0x5a, - 0xfd, - 0x8b, - 0x9c, - 0x2f, - 0xb3, - 0x29, - 0xd2, - 0x19, - 0x6f, - 0xfd, - 0x04, - 0x6d, - 0x75, - 0x3d, - 0x5e, - 0x4e, - 0x0a, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c deleted file mode 100644 index 4173492b31..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c +++ /dev/null @@ -1,112 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[]; -extern CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns a table containing the appropriate microcode patches. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] OrUcodePtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrMicroCodePatchesStruct ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **OrUcodePtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = CpuF15OrNumberOfMicrocodePatches; - *OrUcodePtr = &CpuF15OrMicroCodePatchArray[0]; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c deleted file mode 100644 index f7e148d80b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c +++ /dev/null @@ -1,305 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Message-Based C1e feature support functions. - * - * Provides the functions necessary to initialize the message-based C1e feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53157 $ @e \$Date: 2011-05-16 13:46:21 -0600 (Mon, 16 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuFeatures.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuMsgBasedC1e.h" -#include "cpuApicUtilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "F15PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrInitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Should message-based C1e be enabled - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's Messsage based C1e family services. - * @param[in] Socket Processor socket to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Messsage based C1e is supported. - * - */ -BOOLEAN -STATIC -F15OrIsMsgBasedC1eSupported ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT32 Socket, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader); - return ((BOOLEAN) ((LogicalId.Revision & AMD_F15_ALL) != 0)); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Core 0 task to enable message-based C1e on a family 15h CPU. - * - * @param[in] MsgBasedC1eServices Pointer to this CPU's Messsage based C1e family services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @return AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -STATIC -F15OrInitializeMsgBasedC1e ( - IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 Core; - UINT32 Module; - UINT32 OrMask; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 PackageType; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - PackageType = LibAmdGetPackageType (StdHeader); - // Note that this core 0 does NOT have the ability to launch - // any of its cores. Attempting to do so could lead to a system - // hang. - - // Set F3xA0[IdleExitEn] = 1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - AndMask = 0xFFFFFFFF; - OrMask = 0; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0 - - // Set F4x128[CstateMsgDis] = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - OrMask = 0; - ((CSTATE_POLICY_CTRL1_REGISTER *) &AndMask)->CstateMsgDis = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x128 - - // Read F4x128[CoreCstateMode] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - AndMask = 0xFFFFFFFF; - OrMask = 0; - // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 - if ((LocalPciRegister & 0x00000001) == 1) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltCtl = 7; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC - } else { - // Set F4x118[CacheFlushEn] = 1 or 0 (if AM3r2) - // Set F4x11C[CacheFlushEn] = 1 - PciAddress.Address.Register = CSTATE_CTRL1_REG; - if (PackageType == PACKAGE_TYPE_AM3r2) { - ((CSTATE_CTRL1_REGISTER *) &AndMask)->CacheFlushEnCstAct0 = 0; - } else { - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct0 = 1; - } - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct1 = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x118 - } - - // Set F3xD4[MTC1eEn] = 1 - // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled - // Set F3xD4[CacheFlushImmOnAllHalt] = 1 or 0 (if AM3r2) - AndMask = 0xFFFFFFFF; - OrMask = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->CacheFlushImmOnAllHalt = 0; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC0_REG; - if (IsDramScrubberEnabled (PciAddress, StdHeader)) { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1; - } else { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0; - } - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= AndMask; - LocalPciRegister |= OrMask; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - - } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) { - // At early, this core 0 can launch its subordinate cores. - TaskPtr.FuncAddress.PfApTaskI = F15OrInitializeMsgBasedC1eOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); - } - - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Enable message-based C1e on a family 15h Orochi core. - * - * @param[in] BmStsAddress System I/O address of the bus master status bit. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrInitializeMsgBasedC1eOnCore ( - IN VOID *BmStsAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 LocalMsrRegister; - - LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader); - ((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0; - ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); - LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader); - - // Set MSRC001_0015[HltXSpCycEn] = 1 - LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader); - LocalMsrRegister |= BIT12; - LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Check to see if the DRAM background scrubbers are enabled or not. - * - * @param[in] PciAddress Address of F15 Orochi socket/module to check. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE Memory scrubbers are enabled on the current node. - * @retval FALSE Memory scrubbers are disabled on the current node. - */ -BOOLEAN -STATIC -IsDramScrubberEnabled ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x58; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0)); -} - - -CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e = -{ - 0, - F15OrIsMsgBasedC1eSupported, - F15OrInitializeMsgBasedC1e -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c deleted file mode 100644 index b1c09f26e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c +++ /dev/null @@ -1,234 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi MSR tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60740 $ @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "F15PackageType.h" -#include "cpuF15OrPowerMgmt.h" -#include "GeneralServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -F15OrDisUcodeWorkaroundForErratum671 ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrMsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_MC4_CTL_MASK (0xC0010048) -// bit[10] GartTblWkEn = 1 -// bits[22:19] RtryHtEn = 1111b - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC4_CTL_MASK, // MSR Address - 0x0000000000780400, // OR Mask - 0x0000000000780400, // NAND Mask - }} - }, -// MSR 0xC0011000 -// bit[16] = 1, Erratum #608 for all OR revisions - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - 0xC0011000, // MSR Address - 0x0000000000010000, // OR Mask - 0x0000000000010000, // NAND Mask - }} - }, -// MSR_CPUID_EXT_FEATS (0xC0011005) -// bit[56] PerfCtrExtNB = 1 -// bit[55] PerfCtrExtCore = 1 -// bit[51] NodeId = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CPUID_EXT_FEATS, // MSR Address - 0x0188000000000000, // OR Mask - 0x0188000000000000, // NAND Mask - }} - }, -// MSR_OSVW_ID_Length (0xC0010140) -// bit[15:0] = 4 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_OSVW_ID_Length, // MSR Address - 0x0000000000000004, // OR Mask - 0x000000000000FFFF, // NAND Mask - }} - }, -// MSR_IBS_OP_DATA3 (0xC0011037) -// bit[16] IbsDcMabHit = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_IBS_OP_DATA3, // MSR Address - 0x0000000000000000, // OR Mask - 0x0000000000010000, // NAND Mask - }} - } -}; - -// MSRs with Special Programming Requirements Table - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrAM3MsrWorkarounds[] = -{ - // Disable Microcode workaround for Erratum #671 - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_B2 - }, - {AMD_PF_ALL}, - {{ - F15OrDisUcodeWorkaroundForErratum671, - 0x00000000 - }} - }, -}; - - -CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable = { - AllCores, - (sizeof (F15OrMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrMsrRegisters, -}; - -CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable = { - AllCores, - (sizeof (F15OrAM3MsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrAM3MsrWorkarounds, -}; - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to disable the microcode workaround for Erratum #671 - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrDisUcodeWorkaroundForErratum671 ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MsrData; - UINT32 PackageType; - - // Is this processor AM3? - PackageType = LibAmdGetPackageType (StdHeader); - - if (PackageType == PACKAGE_TYPE_AM3r2) { - // Apply the enhancement. - LibAmdMsrRead (0xC0011000, &MsrData, StdHeader); - MsrData = (MsrData | BIT17); - LibAmdMsrWrite (0xC0011000, &MsrData, StdHeader); - } -} - - - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c deleted file mode 100644 index 0c9290d709..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c +++ /dev/null @@ -1,749 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables from Multi-Link BKDG paragraph recommended settings. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 41897 $ @e \$Date: 2010-11-12 12:39:18 +0800 (Fri, 12 Nov 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -#include "F15PackageType.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrMultiLinkPciRegisters[] = -{ - // Function 0 - -// F0x68 - Link Transaction Control -// bit[14:13], BufRelPri = 01h - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL, // CpuRevision rev C or less. - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00002000, // regData - 0x00006000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 3 - // 17:16 NpReqData: 3 - // 15:12 ProbeCmd: 8 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 4 -{ - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x008F8944, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 0 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 7 - // 4:0 NpReqCmd: 14 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // link features - 0x10, // address - 0x008402EE, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 3 - // 17:16 NpReqData: 3 - // 15:12 ProbeCmd: 4 - // 11:8 RspCmd: 9 - // 7:5 PReq: 2 - // 4:0 NpReqCmd: 8 - { - HtHostPerfPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - HT_HOST_FEAT_COHERENT, // link features - 0x10, // address - 0x008F4948, // data - 0x0FFFFFFF // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - HT_HOST_FEAT_COHERENT, // link features - 0x14, // address - 0x00010000, // data - 0x1FFF0000 // mask - }} - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, - -// Function 3 - Misc. Control - -// NOTE: Order is important. Do not re-order -// the entries for F3x140. - -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // SCM - PACKAGE_TYPE_SCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 9 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, - (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00900300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 1 -// bits[23:20] FreeTok = 11 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // MCM2 - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00B00100, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // MCM4h - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 1 -// bits[23:20] FreeTok = 9 - { - TokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PACKAGE_TYPE_MCM, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00900100, // regData - 0x00F00300, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), // SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C1AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000001AA, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 3)), // MCM2 or MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000016A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00000196, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550155, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // MCM1 or MCM2h. - PERFORMANCE_PROBEFILTER, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x00550165, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 2 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (3, 3)), // MCM2 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01558155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 1 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (IGNORE_PROCESSOR_0 | DEGREE_RANGE_1 (2, 2)), // MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x41550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 1 -// bits[3:2] PReqTok0 = 1 -// bits[5:4] RspTok0 = 1 -// bits[7:6] ProbeTok0 = 1 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 1 -// bits[19:18] PReqTok1 = 1 -// bits[21:20] RspTok1 = 1 -// bits[23:22] ProbeTok1= 1 -// bits[24] IsocReqTok1 = 1 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x01550155, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), //SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C12A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE), // MCM1 or MCM2h or MCM2 or MCM4h - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000012A, // regData - 0xD5FFFFFF, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 2 -// bits[9:8] IsocReqTok0 = 2 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 0 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, // platformFeatures - {{ - (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // MCM4 - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x000002AA, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_MULTI_LINK}, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000000, - 0x0000000F - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrMultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrMultiLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c deleted file mode 100644 index ce07817575..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c +++ /dev/null @@ -1,962 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 59564 $ @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrPciRegisters[] = -{ -// F0x68 - Link Transaction Control -// bit[11] , RespPassPW = 1 -// bits[14:13], BufRelPri = 1 -// bit[19:17], for 8bit APIC config -// bit[22:21], DsNpReqLmt = 10b -// bit [25] CHtExtAddrEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x024E2800, // regData - 0x026E6800, // regMask - }} - }, -// F0x6C - Link Initialization Control -// bit[23] TxSSBusPwrSaveEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address - 0x00800000, // regData - 0x00800000, // regMask - }} - }, -// F0x[E4,A4,C4,84] Link Control Register -// bit [15] Addr64bitEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, - {{ - HT_HOST_FEAT_NONCOHERENT, - 0x4, - 0x00008000, - 0x00008000, - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit[13] LdtStopTriEn = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00002000, // regData - 0x00002000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 0 default - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_NFCM | AMD_PF_UMA) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00000000, // regData - 0x00001000, // regMask - }} - }, -// F0x[E4,C4,A4,84] - Link 0 Control Register -// bit [12] IsocEn = 1 for Isochronous control flow modes. - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU) }, - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x04, // Address - 0x00001000, // regData - 0x00001000, // regMask - }} - }, -// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count -// bit[31] LockBc = 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - HT_HOST_FEATURES_ALL, // link feats - 0x10, // Address - 0x80000000, // regData - 0x80000000, // regMask - }} - }, -// F0x150 - Link Global Retry Control Register -// bit[18:16] TotalRetryAttempts = 7 -// bit[13] HtRetryCrcDatInsDynEn = 1 -// bit[12]HtRetryCrcCmdPackDynEn = 1 -// bit[11:9] HtRetryCrcDatIns = leave default reset value (erratum #600) -// bit[8] HtRetryCrcCmdPack = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address - 0x00073100, // regData - 0x00073100, // regMask - }} - }, -// F0x16C - Link Global Extended Control Register -// bit[22:17] FullT0Time = 0x33 -// bit[15:13] ForceFullT0 = 7 -// bit[7:6] InLnSt = 01b (PHY_OFF) -// bit[5:0] T0Time = 0x26 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address - 0x0066E066, // regData - 0x007EE0FF, // regMask - }} - }, -// F0x[18C:170] - Link Extended Control Register - All connected links. -// bit[8] LS2En = 1 - { - HtLinkPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - HT_HOST_FEATURES_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x1B0 - Extended Memory Controller Configuration Low -// bits[10:8], CohPrefPrbLmt = 0 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address - 0x00000000, // regData - 0x00000700, // regMask - }} - }, -// Function 3 - Misc. Control - -// F3x40 - MCA NB Control -// -// bit[8], MstrAbrtEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F3x44 - MCA NB Configuration -// bit[30] SyncOnDramAdrParErrEn = 1 -// bit[27] NB MCA to Master CPU Enable = 1 -// bit[25] DisPciCfgCpuErrRsp = 1 -// bit[21] SyncFloodOnAnyUcErr = 1 -// bit[20] SyncOnWDTEn = 1 -// bit[6] CpuErrDis = 1 -// bit[4] SyncPktPropDis = 0 -// bit[3] SyncPktGenDis = 0 -// bit[2] SyncOnUcEccEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address - 0x4A300044, // regData - 0x4A30005C, // regMask - }} - }, -// F3x70 - SRI_to_XBAR Command Buffer Count -// bits[30:28] IsocRspCBC = 1 -// bits[26:24] IsocPreqCBC = 0 -// bits[22:20] IsocReqCBC = 1 -// bits[18:16] UpRspCBC = 7 -// bits[14:12] DnPreqCBC = 1 -// bits[10:8] UpPreqCBC = 1 -// bits[7:6] DnRspCBC = 1 -// bits[5:4] DnReqCBC = 1 -// bits[2:0] UpReqCBC = 5 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address - 0x10171155, // regData - 0x777777F7, // regMask - }} - }, -// F3x74 - XBAR_to_SRI Command Buffer Count -// bits[31:28] DRReqCBC = 0 -// bits[26:24] IsocPreqCBC = 0 -// bits[23:20] IsocReqCBC = 1 -// bits[19:16] ProbeCBC = 7 -// bits[14:12] DnPreqCBC = 2 -// bits[10:8] UpPreqCBC = 1 -// bits[6:4] DnReqCBC = 1 -// bits[2:0] UpReqCBC = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address - 0x00172111, // regData - 0xF7FF7777, // regMask - }} - }, -// F3x78 - MCT to XBAR Buffer Count -// bits[12:8] ProbeCBC = 0Eh -// bits[4:0] RspCBC = 12h - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78), // Address - 0x00000E12, // regData - 0x00001F1F, // regMask - }} - }, -// F3x78 - MCT to XBAR Buffer Count -// bits[12:8] ProbeCBC = 0Ch -// bits[4:0] RspCBC = 14h - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78), // Address - 0x00000C14, // regData - 0x00001F1F, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[26:23] SrqExtFreeListBC = 8 -// bits[22:20] Sri2XbarFreeRspDBC = 0 -// bits[19:16] Sri2XbarFreeXreqDBC = 0xD -// bits[15:12] Sri2XbarFreeRspCBC = 0 -// bits[11:8] Sri2XbarFreeXreqCBC = 0xF - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x040D0F00, // regData - 0x07FFFF00, // regMask - }} - }, -// F3x7C - Free List Buffer Count -// bits[4:0] Xbar2SriFreeListCBC = 0x16 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address - 0x00000016, // regData - 0x0000001F, // regMask - }} - }, -// F3x80 - ACPI Power State Control -// ACPI State C2 -// bit[0] CpuPrbEn = 1 -// bit[1] NbLowPwrEn = 0 -// bit[2] NbGateEn = 0 -// bits[7:5] ClkDivisor = 4 -// ACPI State C3, C1E or Link init -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// NB P-state changes -// bit[0] CpuPrbEn = 1 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 1 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 0 -// S1 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address - 0xE20BE281, // regData - 0xFFFFFFE7, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State S3 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State S4/S5 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 1 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 -// ACPI State C1 -// bit[0] CpuPrbEn = 0 -// bit[1] NbLowPwrEn = 0 -// bit[2] NbGateEn = 0 -// bit[3] NbCofChg = 0 -// bit[4] Reserved = 0 -// bits[7:5] ClkDivisor = 7 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0xE0E200E2, // regData - 0xEFFF00FF, // regMask - }} - }, -// F3x84 - ACPI Power State Control -// ACPI State C1 -// bits[0] CpuPrbEn = 0 -// bits[1] NbLowPwrEn = 0 -// bits[2] NbGateEn = 0 -// bits[7:5] ClkDivisor = 4 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_CORE}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address - 0x80000000, // regData - 0xE7000000, // regMask - }} - }, -// F3x90 - GART Aperture Control -// bit[6] = DisGartTblWlkPrb, Erratum 540 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x90), // Address - 0x00000040, // regData - 0x00000040, // regMask - }} - }, -// F3xA0 - Power Control Miscellaneous -// bit[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F3xD4 - Clock Power Timing Control 0 -// bits[11:8] ClkRampHystSel = 0xF -// bits[15] StutterScrubEn = 0 -// bits[14] CacheFlushImmOnAllHalt = 0 -// bits[13] MTC1eEn = 0 -// bits[17:16] LnkPllLock = 1 -// bits[30:28] NbClkDiv = 4 -// bits[31] NbClkDivApplyAll = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address - 0xC0010F00, // regData - 0xF003EF00, // regMask - }} - }, -// F3xD8 - Clock Power Timing Control 1 -// bits[6:4] VSRampSlamTime = 1 -// bits[27:24] ReConDel = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address - 0x03000010, // regData - 0x0F000070, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[1:0] UpReqTok = 1 -// bits[3:2] DnReqTok = 1 -// bits[5:4] UpPreqTok = 1 -// bits[7:6] DnPreqTok = 1 -// bits[11:10] DnRspTok = 1 -// bits[13:12] IsocReqTok = 1 -// bits[15:14] IsocPreqTok = 0 -// bits[17:16] IsocRspTok = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00011455, // regData - 0x0003FCFF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 5 -// bits[7:4] ProbeTok = 5 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROFILE_ALL, - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000055, // regData - 0x000000FF, // regMask - }} - }, -// F3x144 - MCT to XCS Token Count -// bits[3:0] RspTok = 8 -// bits[7:4] ProbeTok = 2 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_PROBEFILTER, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address - 0x00000028, // regData - 0x000000FF, // regMask - }} - }, -// F3x160 - NB Machine Check Misc 0 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x160), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x168 - NB Machine Check Misc 1 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x168), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x170 - NB Machine Check Misc 2 -// bits[23:20] LvtOffset = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x170), // Address - 0x00100000, // regData - 0x00F00000, // regMask - }} - }, -// F3x180 - NB Extended Configuration -// bit[1] SyncFloodOnUsPwDatErr = 1 -// bit[5] DisPciCfgCpuMstAbtRsp = 1 -// bit[6] SyncFloodOnDatErr = 1 -// bit[7] SyncFloodOnTgtAbtErr = 1 -// bit[8] SyncFloodOnHtProtEn = 1 -// bit[9] SyncOnUCNbAryEn = 1 -// bit[20] SyncFloodOnL3LeakErr = 1 -// bit[21] SyncFloodOnCpuLeakErr = 1 -// bit[22] SyncFloodOnTblWalkErr = 1 -// bit[24] McaLogErrAddrWdtErr = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address - 0x017003E2, // regData - 0x017003E2, // regMask - }} - }, -// F3x188 - NB Configuration 2 Register -// bit[9] DisL3HiPriFreeListAlloc = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address - 0x00000200, // regData - 0x00000200, // regMask - }} - }, -// F3x1A0 - L3 Buffer Count -// bits[17:16] CpuToNbFreeBufCnt = 3 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address - 0x00030000, // regData - 0x00030000, // regMask - }} - }, -// F3x1B8 - L3 Control 1 -// bit[12] L3PrivReplEn = 1 -// bit[18] Reserved = 1, Erratum #504 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address - 0x00041000, // regData - 0x00041000, // regMask - }} - }, -// F3x1E4 - SBI Control -// bits[11:8] LvtOffset = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1E4), // Address - 0x00000300, // regData - 0x00000F00, // regMask - }} - }, -// F4x104 - TDP Accumulator Divisor Control -// bits[1:0] TdpAccDivVal = 1 -// bits[13:2] TdpAccDivRate = 0x0C8 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address - 0x00000321, // regData - 0x00003FFF, // regMask - }} - }, -// F4x110 - Sample and Residency Timer -// bits[11:0] CSampleTimer = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address - 0x00000001, // regData - 0x00000FFF, // regMask - }} - }, -// F4x118 - C-state Control 1 -// bit [0] CpuPrbEnCstAct0 = 0 -// bit [1] CacheFlushEnCstAct0 = 0 -// bits[3:2] CacheFlushTmrSelCstAct0 = 0 -// bits[7:5] ClkDivisorCstAct0 = 0 -// bit [8] PwrGateEnCstAct0 = 0 -// bit [16] CpuPrbEnCstAct1 = 0 -// bit [17] CacheFlushEnCstAct1 = 0 -// bits[19:18] CacheFlushTmrSelCstAct1 = 0 -// bits[23:21] ClkDivisorCstAct1 = 0 -// bit [24] PwrGateEnCstAct1 = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address - 0x00000000, // regData - 0x01EF01EF, // regMask - }} - }, -// F4x11C - C-state Control 2 -// bit [0] CpuPrbEnCstAct2 = 0 -// bit [1] CacheFlushEnCstAct2 = 0 -// bits[3:2] CacheFlushTmrSelCstAct2 = 0 -// bits[7:5] ClkDivisorCstAct2 = 0 -// bit [8] PwrGateEnCstAct2 = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x11C), // Address - 0x00000000, // regData - 0x000001EF, // regMask - }} - }, -// F4x128 - C-state Policy Control 1 -// bits[20:18] CacheFlushSucMonThreshold = 4 -// bits[11:5] CacheFlushTmr = 0x28 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x128), // Address - 0x00100500, // regData - 0x001C0FE0, // regMask - }} - }, -// F4x16C - APM TDP Control -// bit[4] ApmTdpLimitIntEn = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address - 0x00000010, // regData - 0x00000010, // regMask - }} - }, -// F4x1C4 - L3 Power Control Register -// bits[8] L3PwrSavEn = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - PERFORMANCE_L3_CACHE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F4x1CC - L3 Control 2 -// bit[4] ImplRdAnySubUnavail = 1 -// bits[8:6] ImplRdProjDelayThresh = 2 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1CC), // Address - 0x00000090, // regData - 0x000001D0, // regMask - }} - }, -// F5x88 - Northbridge Configuration 4 -// bit[5] Reserved, BIOS must set - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - 0x04, // Features - MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address - 0x00000020, // regData - 0x00000020, // regMask - }} - }, -// F5x88 - Northbridge Configuration 4 -// bit[14] Reserved, BIOS must set - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_Bx // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address - 0x00004000, // regData - 0x00004000, // regMask - }} - }, -// F5xE0 - Processor TDP Running Average -// bits[3:0] RunAvgRange = 0xE - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address - 0x0000000E, // regData - 0x0000000F, // regMask - }} - } -}; - -CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrPciRegisters, -}; - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c deleted file mode 100644 index b339d2d983..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c +++ /dev/null @@ -1,317 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi NB COF VID Initialization - * - * Performs the "BIOS Northbridge COF and VID Configuration" as - * described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 51891 $ @e \$Date: 2011-04-28 12:39:55 -0600 (Thu, 28 Apr 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "OptionMultiSocket.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "F15OrPmNbCofVidInit.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmNbCofVidInitOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the "Mixed Northbridge Frequency - * Configuration Sequence" - * - * BIOS must match F5x1[6C:60][NbFid, NbDid, NbPstateEn] between all - * processors of a multi-socket system. The lowest setting from all - * processors is used as the common F5x1[6C:60][NbFid, NbDid]. All - * processors must have the same number of NB P-states. - * - * For each node in the system { - * For (i = 0; i <= F5x170[NbPstateMaxVal]; i++) { - * NewNbFreq = the lowest NBCOF from all processors for NB P-state i - * NewNbFid = F5x1[6C:60][NbFid] that corresponds to NewNbFreq - * NewNbDid = F5x1[6C:60][NbDid] that corresponds to NewNbFreq - * Write NewNbFid and NewNbDid to F5x1[6C:60][NbFid, NbDid] indexed - * by NB P-state i - * } - * If (F5x170[NbPstateMaxVal] == 0) { - * Save F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * Copy F5x1[6C:60] indexed by NB P-state 0 to F5x1[6C:60] indexed by NB P-state 1 - * Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - * Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - * Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] and F5x174[CurNbFid, CurNb- - * Did]=[NbFid, NbDid] from F5x1[6C:60] indexed by F5x170[NbPstateLo] - * Restore F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - * } - * } - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service related parameters (unused). - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 i; - UINT32 NbFreq; - UINT32 NbDiv; - UINT32 LocalPciRegister; - UINT32 AndMask; - UINT32 OrMask; - UINT32 Ignored; - UINT32 NbPsCtrl; - UINT32 TaskedCore; - BOOLEAN PstateSettingsChanged; - BOOLEAN PstatesMatch; - BOOLEAN PstateEnabledAll; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - // Get the local node ID - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Core == 0); - - PstateSettingsChanged = FALSE; - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - for (i = 0; i <= ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal; i++) { - if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings (i, &CpuEarlyParamsPtr->PlatformConfig, &NbFreq, &NbDiv, &PstatesMatch, &PstateEnabledAll, StdHeader)) { - if (PstateEnabledAll) { - // Valid system-wide NB P-state - if (!PstatesMatch) { - // Configure NbPstate[i] to match the slowest - PciAddress.Address.Register = (NB_PSTATE_0 + (4 * i)); - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - OrMask = 0x00000000; - ((NB_PSTATE_REGISTER *) &OrMask)->NbFid = ((NbFreq / 200) - 4); - ((NB_PSTATE_REGISTER *) &OrMask)->NbDid = (UINT32) LibAmdBitScanForward (NbDiv); - if ((((NB_PSTATE_REGISTER *) &OrMask)->NbFid != ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid) || - (((NB_PSTATE_REGISTER *) &OrMask)->NbDid != ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid)) { - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_REGISTER *) &AndMask)->NbFid = 0; - ((NB_PSTATE_REGISTER *) &AndMask)->NbDid = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - PstateSettingsChanged = TRUE; - } - } - } else { - // At least one processor in the system does not have NbPstate[i] - PciAddress.Address.Register = NB_PSTATE_CTRL; - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->NbPstateMaxVal = 0; - OrMask = 0; - if (i != 0) { - ((NB_PSTATE_CTRL_REGISTER *) &OrMask)->NbPstateMaxVal = (i - 1); - } - // Modify NbPstateMaxVal to reflect the system value - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Disable this NB P-state - PciAddress.Address.Register = (NB_PSTATE_0 + (4 * i)); - AndMask = 0xFFFFFFFF; - ((NB_PSTATE_REGISTER *) &AndMask)->NbPstateEn = 0; - OrMask = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Log error for the invalid configuration - PutEventLog (AGESA_ERROR, - CPU_ERROR_PM_NB_PSTATE_MISMATCH, - Socket, i, 0, 0, StdHeader); - break; - } - } - } - - if (PstateSettingsChanged) { - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal == 0) { - // Launch one core per node. - TaskPtr.FuncAddress.PfApTask = F15OrPmNbCofVidInitOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { - if (TaskedCore != 0) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); - } - } -} - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbCofVidInit to perform the actual NB P-state transition - * to the leveled NB P-state settings on one core of each die in a family 15h socket. - * - * The following steps are performed: - * 1. Save F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * 2. Copy F5x1[6C:60] indexed by NB P-state 0 to F5x1[6C:60] indexed by NB P-state 1 - * 3, Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - * 4. Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - * 5. Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] and F5x174[CurNbFid, CurNb- - * Did]=[NbFid, NbDid] from F5x1[6C:60] indexed by F5x170[NbPstateLo] - * 6. Restore F5x170 and F5x1[6C:60] indexed by NB P-state 1 - * 7. Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmNbCofVidInitOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - UINT32 NbPs0; - UINT32 NbPs1; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - // Save F5x170 and F5x164 - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - PciAddress.Address.Register = NB_PSTATE_0; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPs0, StdHeader); - PciAddress.Address.Register = NB_PSTATE_1; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPs1, StdHeader); - - // Copy F5x160 to F5x164 - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPs0, StdHeader); - - // Write 1 to F5x170[NbPstateMaxVal, NbPstateLo] - PciAddress.Address.Register = NB_PSTATE_CTRL; - LocalPciRegister = NbPsCtrl; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal = 1; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateLo = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Write 0 to F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold] - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->SwNbPstateLoDis = 0; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateDisOnP0 = 0; - ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateThreshold = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // Wait for F5x174[CurNbPstate] = F5x170[NbPstateLo] (written to 1 above) and - // F5x174[CurNbFid, CurNbDid] = F5x164[NbFid, NbDid] - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while ((((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbPstate != 1) && - (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid != ((NB_PSTATE_REGISTER *) &NbPs0)->NbFid) && - (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid != ((NB_PSTATE_REGISTER *) &NbPs0)->NbDid)); - - // Restore F5x170 and F5x164 - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - PciAddress.Address.Register = NB_PSTATE_1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPs1, StdHeader); - - // Wait for F5x174[CurNbPstate] = F5x170[NbPstateHi] - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } while (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h deleted file mode 100644 index 69652474df..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi NB COF VID Initialization - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ -#define _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmNbCofVidInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_PM_NB_COF_VID_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c deleted file mode 100644 index 7cc2e82dce..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c +++ /dev/null @@ -1,177 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Management related initialization table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "cpuPowerMgmtSystemTables.h" -#include "cpuF15OrCoreAfterReset.h" -#include "cpuF15OrNbAfterReset.h" -#include "cpuF15OrSoftwareThermal.h" -#include "F15OrPowerPlane.h" -#include "cpuF15PowerCheck.h" -#include "F15OrPmNbCofVidInit.h" -#include "F15OrUtilities.h" - -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -GetF15OrSysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* Family 15h Only Table */ -/* ---------------------- */ -CONST SYS_PM_TBL_STEP ROMDATA CpuF15OrSysPmTableArray[] = -{ - - IDS_INITIAL_F15_OR_PM_STEP - - // Step 1 - Configure F3x[84:80]. Handled by PCI register table. - // Step 2 - Power Plane Initialization - // Execute both cold & warm - { - 0, // ExeFlags - F15OrPmPwrPlaneInit // Function Pointer - }, - - // Step x - Disable NB Pstate, if required - // Execute both cold & warm - { - 0, // ExeFlags - F15OrNbPstateDis // Function Pointer - }, - - // Step 3 - Configure Northbridge COF and VID. - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmNbCofVidInit // Function Pointer - }, - - // Step 4 - Core Minimum P-state Transition Sequence After Warm Reset - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmCoreAfterReset // Function Pointer - }, - - // Step 5 - NB COF and VID Transition Sequence After Warm Reset - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmNbAfterReset // Function Pointer - }, - - // Step 6 - Power Check - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15PmPwrCheck // Function Pointer - }, - - // Step 7 - Software Thermal Control Init - // Execute only after warm reset - { - PM_EXEFLAGS_WARM_ONLY, // ExeFlags - F15OrPmThermalInit // Function Pointer - } -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the appropriate table of steps to perform to initialize the power management - * subsystem. - * - * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] SysPmTblPtr Points to the first entry in the table. - * @param[out] NumberOfElements Number of valid entries in the table. - * @param[in] StdHeader Header for library and services. - * - */ -VOID -GetF15OrSysPmTable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT CONST VOID **SysPmTblPtr, - OUT UINT8 *NumberOfElements, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - *NumberOfElements = (sizeof (CpuF15OrSysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); - *SysPmTblPtr = CpuF15OrSysPmTableArray; -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c deleted file mode 100644 index 317f9d62ad..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c +++ /dev/null @@ -1,236 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Plane Initialization - * - * Performs the "BIOS Requirements for Power Plane Initialization" as described - * in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "Table.h" -#include "OptionMultiSocket.h" -#include "F15OrPowerPlane.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h core 0 entry point for performing power plane initialization. - * - * The steps are as follows: - * 1. Configure D18F3xD8[VSRampSlamTime] based on platform - * requirements. - * 2. Configure F3xD4[PowerStepUp & PowerStepDown] - * 3. Optionally configure F3xA0[PsiVidEn & PsiVid] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 Core; - UINT32 LocalPciRegister; - UINT32 AndMask; - UINT32 OrMask; - PLATFORM_FEATS Features; - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - // Configure D18F3xD8[VSRampSlamTime] based on platform requirements. - // Before characterization has taken place, no calculations are necessary. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC1_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - OrMask = 0x00000000; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSRampSlamTime = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - // Configure PowerStepUp/PowerStepDown - PciAddress.Address.Register = CPTC0_REG; - AndMask = 0xFFFFFFFF; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0; - OrMask = 0x00000000; - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader); - if (Features.PlatformFeatures.PlatformSingleLink == 1) { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 8; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 8; - } else { - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = 3; - ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = 3; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - - if (IsWarmReset (StdHeader)) { - // Configure PsiVid - F15OrPmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Sets up PSI_L operation. - * - * This function implements the LowPowerThreshold parameter. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter. - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmVrmLowPowerModeEnable ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Pstate; - UINT32 PstateCurrent; - UINT32 NextPstateCurrent; - UINT32 AndMask; - UINT32 OrMask; - UINT32 PreviousVID; - UINT32 PstateVID; - UINT32 HwPsMaxVal; - UINT64 PstateMsr; - BOOLEAN EnablePsi; - - if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) { - EnablePsi = FALSE; - PreviousVID = 0x7F; // Initialize to invalid zero volt VID code - PstateVID = 0x7F; - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - - for (Pstate = 0; Pstate <= (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; Pstate++) { - if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) { - LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader); - PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid); - if ((Pstate + 1) > (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal) { - NextPstateCurrent = 0; - } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) { - NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit + NextPstateCurrent; - } - if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (PstateVID != PreviousVID)) { - EnablePsi = TRUE; - break; - } - PreviousVID = PstateVID; - } - } - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PW_CTL_MISC_REG; - OrMask = 0x00000000; - AndMask = 0xFFFFFFFF; - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0; - if (EnablePsi) { - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID; - ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1; - } else { - ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0; - } - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h deleted file mode 100644 index 8396bf3146..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Power Plane related functions and structures - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F15_OR_POWER_PLANE_H_ -#define _F15_OR_POWER_PLANE_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmPwrPlaneInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _F15_OR_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c deleted file mode 100644 index 311e210134..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c +++ /dev/null @@ -1,376 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Shared MSR table with values as defined in BKDG - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 53046 $ @e \$Date: 2011-05-13 20:20:37 -0600 (Fri, 13 May 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuServices.h" -#include "GeneralServices.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -F15OrFpCfgInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - -// MSR_TOM2 (0xC001001D) -// bits[63:0] - TOP_MEM2 = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_TOM2, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0xFFFFFFFFFFFFFFFF, // NAND Mask - }} - }, - -// MSR_SYS_CFG (0xC0010010) -// bit[21] MtrrTom2En = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_SYS_CFG, // MSR Address - Shared - (1 << 21), // OR Mask - (1 << 21), // NAND Mask - }} - }, - -// MSR_MC1_CTL_MASK (0xC0010045) -// bit[15] BSRP = 1, Erratum #593, OR-ALL -// bit[18] DEIBP = 1, Erratum #586, OR-ALL - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_MC1_CTL_MASK, // MSR Address - 0x0000000000048000, // OR Mask - 0x0000000000048000, // NAND Mask - }} - }, - -// MSR_CU_CFG (0xC0011023) -// bit[10] PbForceRespInOrder = 0 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG, // MSR Address - Shared - 0, // OR Mask - 0x00000400, // NAND Mask - }} - }, - -// MSR_DE_CFG (0xC0011029) -// bit[10] ResyncPredSingleDispDis = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_DE_CFG, // MSR Address - Shared - 0x0000000000000400, // OR Mask - 0x0000000000000400, // NAND Mask - }} - }, - -// MSR_CU_CFG2 (0xC001102A) -// bit[50] = 1 -// bit[11] = 1, Erratum #503, OR-ALL -// bit[10] = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG2, // MSR Address - Shared - 0x0004000000000C00, // OR Mask - 0x0004000000000C00, // NAND Mask - }} - }, - -// MSR_CU_CFG3 (0xC001102B) -// bit[42] PwcDisableWalkerSharing = 1 - { - MsrRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - MSR_CU_CFG3, // MSR Address - 0x0000040000000000, // OR Mask - 0x0000040000000000, // NAND Mask - }} - }, -}; - - -// Compute Unit Count Dependent MSR Table - -STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrCuRegisters[] = -{ -// M S R T a b l e s -// ---------------------- - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 0 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000000, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 1 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000040, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 2 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (3, 3) | COUNT_RANGE_NONE)}, // 3 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x0000000000000080, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, - - // MSR_CU_CFG2 (0xC001102A) - // bits[7:6] - ThrottleNbInterface[1:0] = 3 - // bits[37:36] - ThrottleNbInterface[3:2] = 0 - { - CompUnitCountsMsr, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - {(COMPUTE_UNIT_RANGE_0 (4, 4) | COUNT_RANGE_NONE)}, // 4 compute units - { - MSR_CU_CFG2, // MSR Address - Shared - 0x00000000000000C0, // OR Mask - 0x00000030000000C0, // NAND Mask - } - }} - }, -}; - -// Shared MSRs with Special Programming Requirements Table - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrSharedMsrWorkarounds[] = -{ - // MSR_FP_CFG (0xC0011028) - // bit[16] - DiDtMode = F3x1FC[0] - // bits[22:18] - DiDtCfg0 = F3x1FC[5:1] - // bits[34:27] - DiDtCfg1 = F3x1FC[13:6] - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_ALL - }, - {AMD_PF_ALL}, - {{ - F15OrFpCfgInit, - 0x00000000 - }} - }, -}; - - - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrRegisters, -}; - - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrCuRegisters, -}; - -CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable = { - CorePairPrimary, - (sizeof (F15OrSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *) &F15OrSharedMsrWorkarounds, -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Update the FP_CFG MSR in current processor for Family15h OR. - * - * This function satisfies the programming requirements for the FP_CFG MSR. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrFpCfgInit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProductInfo; - UINT64 FpCfg; - PCI_ADDR PciAddress; - - if (IsWarmReset (StdHeader)) { - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = PRCT_INFO_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); - - LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader); - ((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode; - ((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0; - ((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1; - ((FP_CFG_MSR *) &FpCfg)->AlwaysOnThrottle = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->AlwaysOnThrottle; - ((FP_CFG_MSR *) &FpCfg)->Pipe3ThrottleDis = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->Pipe3ThrottleDis; - LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader); - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c deleted file mode 100644 index 5df3ffa252..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c +++ /dev/null @@ -1,321 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi PCI tables in Recommended Settings for Single Link Processors. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 41897 $ @e \$Date: 2010-11-12 12:39:18 +0800 (Fri, 12 Nov 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// P C I T a b l e s -// ---------------------- - -STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15OrSingleLinkPciRegisters[] = -{ -// F0x68 - Link Transaction Control -// bit[14:13], BufPriRel = 01b - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00002000, // regData - 0x00006000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x00000000, // regData - 0x01000000, // regMask - }} - }, -// F0x68 - Link Transaction Control -// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset. - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_UMA}, // platform Features - {{ - PERFORMANCE_IS_WARM_RESET, - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address - 0x01000000, // regData - 0x01000000, // regMask - }} - }, - // F0x[F0,D0,B0,90] Link Base Buffer Count Register - // 27:25 FreeData: 0 - // 24:20 FreeCmd: 8 - // 19:18 RspData: 1 - // 17:16 NpReqData: 0 - // 15:12 ProbeCmd: 0 - // 11:8 RspCmd: 2 - // 7:5 PReq: 7 - // 4:0 NpReqCmd: 14 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x10, // Address - 0x008402EE, // Data - 0x0FFFFFFF // Mask - }}, - }, - // F0x[F4,D4,B4,94] Link Base Buffer Count Register - // 28:27 IsocRspData: 0 - // 26:25 IsocNpReqData: 0 - // 24:22 IsocRspCmd: 0 - // 21:19 IsocPReq: 0 - // 18:16 IsocNpReqCmd: 1 - { - HtHostPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), // Link Features - 0x14, // Address - 0x00010000, // Data - 0x1FFF0000 // Mask - }}, - }, -// F0x170 - Link Extended Control Register - Link 0, sublink 0 -// bit[8] LS2En = 1 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address - 0x00000100, // regData - 0x00000100, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 10b -// bits[31:28] MctVarPriCntLmt = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x00002000, // regData - 0xF0003000, // regMask - }} - }, -// F2x118 - Memory Controller Configuration Low Register -// bits[13:12] MctPriIsoc = 11b -// bits[31:28] MctVarPriCntLmt = 1 - { - ProfileFixup, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_UMA | AMD_PF_UMA_IFCM) }, // platform Features - {{ - PERFORMANCE_MCT_ISOC_VARIABLE, // Features - MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address - 0x10003000, // regData - 0xF0003000, // regMask - }} - }, -// F3x140 - SRI_to_XCS Token Count -// bits[9:8] UpRspTok = 3 -// bits[23:20] FreeTok = 10 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platform Features - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address - 0x00A00300, // regData - 0x00F00300, // regMask - }} - }, -// F3x148 - Link to XCS Token Count -// bits[1:0] ReqTok0 = 2 -// bits[3:2] PReqTok0 = 2 -// bits[5:4] RspTok0 = 2 -// bits[7:6] ProbeTok0 = 0 -// bits[9:8] IsocReqTok0 = 1 -// bits[11:10] IsocPreqTok0 = 0 -// bits[13:12] IsocRspTok0 = 0 -// bits[15:14] FreeTok[1:0] = 3 -// bits[17:16] ReqTok1 = 0 -// bits[19:18] PReqTok1 = 0 -// bits[21:20] RspTok1 = 0 -// bits[23:22] ProbeTok1= 0 -// bits[24] IsocReqTok1 = 0 -// bits[26] IsocPreqTok1 = 0 -// bits[28] IsocRspTok1 = 0 -// bits[31:30] FreeTok[3:2] = 0 - { - HtTokenPciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, // platformFeatures - {{ - (COUNT_RANGE_ALL | COUNT_RANGE_NONE), //SCM - PERFORMANCE_PROFILE_ALL, - (HT_HOST_AND | HT_HOST_FEAT_NONCOHERENT | HT_HOST_FEAT_GANGED), - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address - 0x0000C12A, // regData - 0xD5FFFFFF, // regMask - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 0 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - {AMD_PF_SINGLE_LINK}, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000000, - 0x0000000F - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, - 0x0000000F - }} - }, - // F3x158 - Link to XCS Token Count Registers - // bits [3:0]LnkToXcsDRToken = 3 - { - PciRegister, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_OR_ALL // CpuRevision - }, - { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address - 0x00000003, - 0x0000000F - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable = { - PrimaryCores, - (sizeof (F15OrSingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), - F15OrSingleLinkPciRegisters, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c deleted file mode 100644 index ed2e460516..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c +++ /dev/null @@ -1,939 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 models 0 - 0Fh specific utility functions. - * - * Provides numerous utility functions specific to family 15h OR. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 58928 $ @e \$Date: 2011-09-08 16:43:14 -0600 (Thu, 08 Sep 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuApicUtilities.h" -#include "cpuServices.h" -#include "cpuEarlyInit.h" -#include "GeneralServices.h" -#include "OptionMultiSocket.h" -#include "F15OrUtilities.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/** - * Node ID MSR register fields. - * Provide the layout of fields in the Node ID MSR. - */ -typedef struct { - UINT64 NodeId:3; ///< The core is on the node with this node id. - UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor. - UINT64 BiosScratch:6; ///< BiosScratch, use as the AP core heap index. - UINT64 :(63 - 11); ///< Reserved. -} NODE_ID_MSR_FIELDS; - -/// Node ID MSR. -typedef union { - NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields - UINT64 Value; ///< Access the register value. -} NODE_ID_MSR; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -VOID -STATIC -F15OrNbPstateDisCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Get CPU pstate current. - * - * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. - * - * This function returns the ProcIddMax. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Pstate The P-state to check. - * @param[out] ProcIddMax P-state current in mA. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE P-state is enabled - * @retval FALSE P-state is disabled - */ -BOOLEAN -F15OrGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 IddDiv; - UINT32 NumberOfPhysicalCores; - UINT32 MsrAddress; - UINT64 PstateMsr; - BOOLEAN IsPstateEnabled; - CPUID_DATA CpuId; - - IsPstateEnabled = FALSE; - - MsrAddress = (UINT32) (Pstate + PS_REG_BASE); - ASSERT (MsrAddress <= PS_MAX_REG); - - LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); - if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { - switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { - case 0: - IddDiv = 1000; - break; - case 1: - IddDiv = 100; - break; - case 2: - IddDiv = 10; - break; - default: // IddDiv = 3 is reserved. Use 10 - IddDiv = 10; - break; - } - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - NumberOfPhysicalCores = ((CpuId.ECX_Reg & 0xFF) + 1); - - *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * NumberOfPhysicalCores; - IsPstateEnabled = TRUE; - } - return IsPstateEnabled; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set down core register on Orochi - * - * This function set F3x190 Downcore Control Register[5:0] - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket Socket ID. - * @param[in] Module Module ID in socket. - * @param[in] LeveledCores Number of core. - * @param[in] CoreLevelMode Core level mode. - * @param[in] StdHeader Header for library and services. - * - * @retval TRUE Down Core register is updated. - * @retval FALSE Down Core register is not updated. - */ -BOOLEAN -F15OrSetDownCoreRegister ( - IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, - IN UINT32 *Socket, - IN UINT32 *Module, - IN UINT32 *LeveledCores, - IN CORE_LEVELING_TYPE CoreLevelMode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Xbar2SriFreeListCBC; - UINT8 L3FreeListCBC; - UINT32 TempVar32_a; - UINT32 CoreDisableBits; - UINT32 NumberOfEnabledCores; - UINT32 NumberOfEnabledCU; - PCI_ADDR PciAddress; - BOOLEAN IsUpdated; - AGESA_STATUS AgesaStatus; - NB_CAPS_REGISTER NbCaps; - FREE_LIST_BUFFER_COUNT_REGISTER FreeListBufferCount; - L3_BUFFER_COUNT_REGISTER L3BufferCnt; - - IsUpdated = FALSE; - - if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) { - switch (*LeveledCores) { - case 1: - CoreDisableBits = DOWNCORE_MASK_SINGLE; - break; - case 2: - CoreDisableBits = DOWNCORE_MASK_DUAL_COMPUTE_UNIT; - break; - case 3: - CoreDisableBits = DOWNCORE_MASK_TRI_COMPUTE_UNIT; - break; - case 4: - CoreDisableBits = DOWNCORE_MASK_FOUR_COMPUTE_UNIT; - break; - default: - CoreDisableBits = 0; - break; - } - - } else { - switch (*LeveledCores) { - case 1: - CoreDisableBits = DOWNCORE_MASK_SINGLE; - break; - case 2: - CoreDisableBits = DOWNCORE_MASK_DUAL; - break; - case 4: - CoreDisableBits = DOWNCORE_MASK_FOUR; - break; - case 6: - CoreDisableBits = DOWNCORE_MASK_SIX; - break; - default: - CoreDisableBits = 0; - break; - } - } - - if (CoreDisableBits != 0) { - if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - TempVar32_a = (TempVar32_a & 0xFF) + 1; - TempVar32_a = (1 << TempVar32_a) - 1; - CoreDisableBits &= TempVar32_a; - NumberOfEnabledCores = ~(CoreDisableBits | ~(TempVar32_a)); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = DOWNCORE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - if ((TempVar32_a | CoreDisableBits) != TempVar32_a) { - TempVar32_a |= CoreDisableBits; - LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader); - IsUpdated = TRUE; - - for (NumberOfEnabledCU = 0; NumberOfEnabledCores != 0; NumberOfEnabledCores >>= 2) { - NumberOfEnabledCU += ((NumberOfEnabledCores & 3) != 0) ? 1 : 0; - } - switch (NumberOfEnabledCU) { - case 1: - Xbar2SriFreeListCBC = 0x16; - L3FreeListCBC = 0x1C; - break; - case 2: - Xbar2SriFreeListCBC = 0x14; - L3FreeListCBC = 0x18; - break; - case 3: - Xbar2SriFreeListCBC = 0x12; - L3FreeListCBC = 0x14; - break; - case 4: - Xbar2SriFreeListCBC = 0x10; - L3FreeListCBC = 0x10; - break; - default: - Xbar2SriFreeListCBC = 0x16; - L3FreeListCBC = 0xE; - break; - } - //D18F3x1A0[8:4] L3FreeListCBC: - //BIOS: IF (NumOfCompUnitsOnNode==1) THEN 1Ch ELSEIF (NumOfCompUnitsOnNode==2) - //THEN 18h ELSEIF (NumOfCompUnitsOnNode==3) THEN 14h ELSEIF - //(NumOfCompUnitsOnNode==4) THEN 10h ELSEIF (NumOfCompUnitsOnNode==5) THEN 11h - //ELSE 0Eh ENDIF. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = L3_BUFFER_COUNT_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &L3BufferCnt, StdHeader); - L3BufferCnt.L3FreeListCBC = L3FreeListCBC; - LibAmdPciWrite (AccessWidth32, PciAddress, &L3BufferCnt, StdHeader); - - //D18F3x7C[4:0]Xbar2SriFreeListCBC: - //BIOS: IF (L3Enabled) THEN 16h ELSEIF (D18F5x80[Enabled[3]]==1) THEN 10h ELSEIF - //(D18F5x80[Enabled[2]]==1) THEN 12h ELSEIF (D18F5x80[Enabled[1]]==1) THEN 14h ELSE 16h ENDIF. - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); - if (NbCaps.L3Capable == 0) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = FREE_LIST_BUFFER_COUNT_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &FreeListBufferCount, StdHeader); - FreeListBufferCount.Xbar2SriFreeListCBC = Xbar2SriFreeListCBC; - LibAmdPciWrite (AccessWidth32, PciAddress, &FreeListBufferCount, StdHeader); - } - } - } - } - - return IsUpdated; -} - - -CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling = -{ - 0, - F15OrSetDownCoreRegister -}; - - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. - * @param[in] StdHeader Header for library and services. - * - * @return AGESA_SUCCESS FrequencyInMHz is valid. - */ -AGESA_STATUS -F15OrGetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbFid; - UINT32 NbDid; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_STATUS; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - NbFid = ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid; - NbDid = ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid; - *FrequencyInMHz = (((NbFid + 4) * 200) / (1 << NbDid)); - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the node's minimum and maximum northbridge frequency. - * - * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[out] MinFreqInMHz The node's minimum northbridge frequency. - * @param[out] MaxFreqInMHz The node's maximum northbridge frequency. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Northbridge frequency is valid - */ -AGESA_STATUS -F15OrGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - INT8 NbPsMaxVal; - UINT32 LocalPciRegister; - UINT32 FreqNumerator; - UINT32 FreqDivisor; - BOOLEAN CustomNbPs; - AGESA_STATUS AgesaStatus; - - CustomNbPs = FALSE; - AgesaStatus = AGESA_ERROR; - - // Obtain the max NB frequency on the node - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_0; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - FreqNumerator = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - - *MaxFreqInMHz = (FreqNumerator / FreqDivisor); - AgesaStatus = AGESA_SUCCESS; - } - - // If platform configuration disable NB P-states, return the NB P0 frequency - // as both the min and max frequency on the node. - if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { - *MinFreqInMHz = *MaxFreqInMHz; - } else { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; - - // Obtain the min NB frequency on the node, starting from NB Pmin - for (; NbPsMaxVal >= 0; NbPsMaxVal--) { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal)); - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - // Ensure that the NB Pstate is enabled - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - FreqNumerator = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - - *MinFreqInMHz = (FreqNumerator / FreqDivisor); - AgesaStatus = AGESA_SUCCESS; - break; - } - } - } - IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, MinFreqInMHz, StdHeader); - return AgesaStatus; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Determines the NB clock on the desired node. - * - * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. - * @param[in] NbPstate The NB P-state number to check. - * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. - * @param[out] FreqDivisor The desired node's frequency divisor. - * @param[out] VoltageInuV The desired node's voltage in microvolts. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval TRUE NbPstate is valid - * @retval FALSE NbPstate is disabled or invalid - */ -BOOLEAN -F15OrGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - BOOLEAN PstateIsValid; - - PstateIsValid = FALSE; - - // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled - if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { - PciAddress->Address.Function = FUNC_5; - PciAddress->Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - if (NbPstate <= ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal) { - PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPstate)); - LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); - - // Ensure that requested NbPstate is enabled - if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { - *FreqNumeratorInMHz = ((((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200); - *FreqDivisor = (1 << ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid); - *VoltageInuV = (1550000 - (12500 * (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbVid))); - PstateIsValid = TRUE; - } - } - } - return PstateIsValid; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Get the number of physical cores of current processor. - * - * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The number of physical cores. - */ -UINT8 -F15OrGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CmpCap; - UINT32 CmpCapOnNode; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredSts; - - CmpCap = 0; - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - CmpCapOnNode = (UINT8) (LocalPciRegister & 0xFF); - CmpCapOnNode++; - CmpCap += CmpCapOnNode; - } - } - return ((UINT8) CmpCap); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Use the Mailbox Register to get the Ap Mailbox info for the current core. - * - * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. - * - * Access the mailbox register used with this NB family. This is valid until the - * point that some init code initializes the mailbox register for its normal use. - * The Machine Check Misc (Thresholding) register is available as both a PCI config - * register and a MSR, so it can be used as a mailbox from HT to other functions. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[out] ApMailboxInfo The AP Mailbox info - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrGetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 MailboxInfo; - - LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); - LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader); - // Mailbox info is in bits 32 thru 43, 12 bits. - ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Set the system AP core number in the AP's Mailbox. - * - * @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}. - * - * Access the mailbox register used with this NB family. This is only intended to - * run on the BSC at the time of initial AP launch. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] Socket The AP's socket - * @param[in] Module The AP's module - * @param[in] ApCoreNumber The AP's unique core number - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrSetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - AGESA_STATUS IgnoredStatus; - - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x170; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((AP_MAIL_EXT_INFO *) &LocalPciRegister)->Fields.HeapIndex = ApCoreNumber; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Get this AP's system core number from hardware. - * - * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. - * - * Returns the system core number from the scratch MSR, where - * it was saved at heap initialization. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @return The AP's unique core number - */ -UINT32 -F15OrGetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - NODE_ID_MSR NodeIdMsr; - - LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader); - return (UINT32) NodeIdMsr.Fields.BiosScratch; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Move the AP's core number from the mailbox to hardware. - * - * @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}. - * - * Transfers this AP's system core number from the mailbox to - * the NodeId MSR and initializes the other NodeId fields. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - */ -VOID -F15OrTransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - AP_MAILBOXES Mailboxes; - NODE_ID_MSR NodeIdMsr; - UINT64 ExtFeatures; - - NodeIdMsr.Value = 0; - FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader); - NodeIdMsr.Fields.BiosScratch = Mailboxes.ApMailExtInfo.Fields.HeapIndex; - NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node; - NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType; - LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader); - - // Indicate that the NodeId MSR is supported. - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); - ExtFeatures = (ExtFeatures | BIT51); - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader); -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Disable NB P-state. - * - clear F5x1[6C:64] - * - clear F5x170[NbPstateMaxVal] - * - set F5x170[SwNbPstateLoDis] - * - clear MSRC001_00[6B:64][NbPstate] - * - * @param[in] FamilySpecificServices The current Family Specific Services - * @param[in] CpuEarlyParamsPtr Service Parameters - * @param[in] StdHeader Handle of Header for calling lib functions and services. - */ -VOID -F15OrNbPstateDis ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 PciData; - UINT32 AndMask; - AP_TASK TaskPtr; - PCI_ADDR PciAddress; - - // Check whether NB P-state is disabled - if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { - - IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstates disabled\n"); - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - AndMask = 0x00000000; - // If NbPstateHi is not NB P0, get the Pstate pointed to by NbPstateHi and copy it's value to NB P0 - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - if (((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi != 0) { - PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi * 4); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciAddress.Address.Register = NB_PSTATE_0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - } - - // Clear F5x1[6C:64] - for (i = 1; i < NM_NB_PS_REG; i++) { - PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, AndMask, StdHeader); - } - - // Clear F5x170[NbPstateMaxVal] and set F5x170[SwNbPstateLoDis] - PciAddress.Address.Register = NB_PSTATE_CTRL; - AndMask = 0xFFFFFFFF; - PciData = 0x00000000; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->NbPstateMaxVal = 0; - ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - - // Clear MSRC001_00[6B:64][NbPstate] on cores - TaskPtr.FuncAddress.PfApTask = F15OrNbPstateDisCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.DataTransfer.DataPtr = NULL; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Once we are done disabling NB Pstates, clear F5x170[SwNbPstateLoDis] - AndMask = 0xFFFFFFFF; - PciData = 0x00000000; - ((NB_PSTATE_CTRL_REGISTER *) &AndMask)->SwNbPstateLoDis = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); - } -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Disable NB P-state on core. - * - clear MSRC001_00[6B:64][NbPstate]. - * - * @param[in] StdHeader Handle of Header for calling lib functions and services. - */ -VOID -STATIC -F15OrNbPstateDisCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT64 MsrData; - - // Only one core per compute unit needs to clear NbPstate in P-state MSRs - if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { - for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) { - LibAmdMsrRead (i, &MsrData, StdHeader); - ((PSTATE_MSR *) &MsrData)->NbPstate = 0; - LibAmdMsrWrite (i, &MsrData, StdHeader); - } - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to override CPU TDP Limit 2 setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrOverrideNodeTdpLimit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 OrMask; - UINT32 LocalPciRegister; - BOOLEAN IsMultiNodeCpu; - PCI_ADDR PciAddress; - - IsMultiNodeCpu = FALSE; - // check if it is MCM part - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - IsMultiNodeCpu = (BOOLEAN) (((NB_CAPS_REGISTER *) &LocalPciRegister)->MultiNodeCpu == 1); - } - - if (IsMultiNodeCpu) { - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = 0x10C; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - // The correct value is the half of the fused value - OrMask = LocalPciRegister & 0xFFFFF000; - LocalPciRegister = ((LocalPciRegister & 0x00000FFF) >> 1) | OrMask; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to override CPU Node TDP Accumulator Throttle Threshold setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrOverrideNodeTdpAccumulatorThrottleThreshold ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 CmpCap; - UINT32 OrMask; - UINT32 CUStatus; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = 0x84; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - CmpCap = (UINT8) (LocalPciRegister & 0x000000FF); - CmpCap++; - - // check if the part is fused with 1 core enabled per compute unit - PciAddress.Address.Register = 0x80; - LibAmdPciRead (AccessWidth32, PciAddress, &CUStatus, StdHeader); - if ((CUStatus & 0x000F0000) != 0) { - CmpCap = CmpCap >> 1; - } - - PciAddress.Address.Register = 0xBC; - LibAmdPciRead (AccessWidth32, PciAddress, &OrMask, StdHeader); - OrMask = (UINT32) ((OrMask & 0x000FFFFF) * CmpCap); - - PciAddress.Address.Register = 0xB4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - // The correct value is F5xBC[CmpUnitTdpAccThrottleThreshold] x ((F5x84[CmpCap] + 1) / 2). - LocalPciRegister = (LocalPciRegister & 0xFFF00000) | (OrMask & 0x000FFFFF); - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * A Family Specific Workaround method, to sync internal node 1 SbiAddr setting. - * - * \@TableTypeFamSpecificInstances. - * - * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. - * @param[in] StdHeader Config params for library, services. - */ -VOID -F15OrSyncInternalNode1SbiAddr ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 DataOr; - UINT32 DataAnd; - UINT32 ModuleType; - PCI_ADDR PciAddress; - AGESA_STATUS AgesaStatus; - UINT32 SyncToModule; - AP_MAIL_INFO ApMailboxInfo; - UINT32 LocalPciRegister; - - ApMailboxInfo.Info = 0; - - GetApMailbox (&ApMailboxInfo.Info, StdHeader); - ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); - ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); - Socket = ApMailboxInfo.Fields.Socket; - Module = ApMailboxInfo.Fields.Module; - ModuleType = ApMailboxInfo.Fields.ModuleType; - - // sync is just needed on multinode cpu - if (ModuleType != 0) { - // check if it is internal node 0 of every socket - if (Module == 0) { - if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // read internal node 0 F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - DataOr = LocalPciRegister & ((UINT32) (7 << 4)); - DataAnd = ~(UINT32) (7 << 4); - for (SyncToModule = 1; SyncToModule < GetPlatformNumberOfModules (); SyncToModule++) { - if (GetPciAddress (StdHeader, Socket, SyncToModule, &PciAddress, &AgesaStatus)) { - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = 0x1E4; - // sync the other internal node F3x1E4[6:4] - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - LocalPciRegister &= DataAnd; - LocalPciRegister |= DataOr; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } - } - } - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h deleted file mode 100644 index a52491a2b4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h +++ /dev/null @@ -1,169 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific utility functions. - * - * Provides numerous utility functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 57155 $ @e \$Date: 2011-07-28 02:27:47 -0600 (Thu, 28 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _F15_OR_UTILITES_H_ -#define _F15_OR_UTILITES_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ - -UINT8 -F15OrGetNumberOfPhysicalCores ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrGetApMailboxFromHardware ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT AP_MAILBOXES *ApMailboxInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrNbPstateDis ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrGetProcIddMax ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT8 Pstate, - OUT UINT32 *ProcIddMax, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetCurrentNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetMinMaxNbFrequency ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - OUT UINT32 *MinFreqInMHz, - OUT UINT32 *MaxFreqInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -F15OrGetNbPstateInfo ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PCI_ADDR *PciAddress, - IN UINT32 NbPstate, - OUT UINT32 *FreqNumeratorInMHz, - OUT UINT32 *FreqDivisor, - OUT UINT32 *VoltageInuV, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrSetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN UINT32 Socket, - IN UINT32 Module, - IN UINT32 ApCoreNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT32 -F15OrGetApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrTransferApCoreNumber ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrOverrideNodeTdpLimit ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrOverrideNodeTdpAccumulatorThrottleThreshold ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrSyncInternalNode1SbiAddr ( - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _F15_OR_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c deleted file mode 100644 index 7ee0a2d32f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c +++ /dev/null @@ -1,134 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Models 0x00 - 0x0F Specific Workaround table - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/FAMILY/0x15/OR - * @e \$Revision: 57155 $ @e \$Date: 2011-07-28 02:27:47 -0600 (Thu, 28 Jul 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15Utilities.h" -#include "F15OrUtilities.h" -#include "Filecode.h" -CODE_GROUP (G2_PEI) -RDATA_GROUP (G2_PEI) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -// F a m i l y S p e c i f i c W o r k a r o u n d T a b l e s -// ----------------------------------------------------------------- - -STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15OrWorkarounds[] = -{ -// F0x6C - Link Initialization Control Register -// Request for warm reset in AmdInitEarly -// [5, BiosRstDet] = 1b - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, // CpuFamily - AMD_F15_ALL // CpuRevision - }, - {AMD_PF_ALL}, // platformFeatures - {{ - SetWarmResetAtEarly, // function call - 0x00000000, // data - }} - }, - // HT PHY DLL Compensation setting for rev B and later - { - FamSpecificWorkaround, - { - AMD_FAMILY_15, - AMD_F15_OR_GT_Ax - }, - {AMD_PF_ALL}, - {{ - F15HtPhyOverrideDllCompensation, - 0x00000001 - }} - }, - // Internal Node 1 SbiAddr sync for OR - { - FamSpecificWorkaround, - { - AMD_FAMILY_15_OR, - AMD_F15_OR_ALL - }, - {AMD_PF_ALL}, - {{ - F15OrSyncInternalNode1SbiAddr, - 0x00000000 - }} - }, -}; - -CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable = { - PrimaryCores, - (sizeof (F15OrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), - (TABLE_ENTRY_FIELDS *)F15OrWorkarounds, -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc deleted file mode 100644 index f28c5f7d09..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/Makefile.inc +++ /dev/null @@ -1,32 +0,0 @@ -libagesa-y += F15OrC6State.c -libagesa-y += F15OrCpb.c -libagesa-y += F15OrEarlySamples.c -libagesa-y += F15OrEquivalenceTable.c -libagesa-y += F15OrHtPhyTables.c -libagesa-y += F15OrInitEarlyTable.c -libagesa-y += F15OrIoCstate.c -libagesa-y += F15OrL3Features.c -libagesa-y += F15OrLogicalIdTables.c -libagesa-y += F15OrLowPwrPstate.c -libagesa-y += F15OrMicrocodePatch06000425.c -libagesa-y += F15OrMicrocodePatch0600050D_Enc.c -libagesa-y += F15OrMicrocodePatch06000624_Enc.c -libagesa-y += F15OrMicrocodePatchTables.c -libagesa-y += F15OrMsgBasedC1e.c -libagesa-y += F15OrMsrTables.c -libagesa-y += F15OrMultiLinkPciTables.c -libagesa-y += F15OrPciTables.c -libagesa-y += F15OrPmNbCofVidInit.c -libagesa-y += F15OrPowerMgmtSystemTables.c -libagesa-y += F15OrPowerPlane.c -libagesa-y += F15OrSharedMsrTable.c -libagesa-y += F15OrSingleLinkPciTables.c -libagesa-y += F15OrUtilities.c -libagesa-y += F15OrWorkaroundsTable.c -libagesa-y += cpuF15OrCacheFlushOnHalt.c -libagesa-y += cpuF15OrCoreAfterReset.c -libagesa-y += cpuF15OrDmi.c -libagesa-y += cpuF15OrFeatureLeveling.c -libagesa-y += cpuF15OrNbAfterReset.c -libagesa-y += cpuF15OrPstate.c -libagesa-y += cpuF15OrSoftwareThermal.c diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c deleted file mode 100644 index 1692eb9d44..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c +++ /dev/null @@ -1,184 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD CPU Cache Flush On Halt Function for Family 15h Orochi. - * - * Contains code to initialize Cache Flush On Halt feature for Family 15h Orochi. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - *---------------------------------------------------------------------------- - */ - - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuFeatures.h" -#include "F15PackageType.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE - -/*---------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *---------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------- - * TYPEDEFS AND STRUCTURES - * - *---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ -VOID -SetF15OrCacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * P U B L I C F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * Enable Cpu Cache Flush On Halt Function - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] EntryPoint Timepoint designator. - * @param[in] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - */ -VOID -SetF15OrCacheFlushOnHaltRegister ( - IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, - IN UINT64 EntryPoint, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AndMask; - UINT32 OrMask; - PCI_ADDR PciAddress; - - if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { - // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - OrMask = 0; - AndMask = 0xFC00FFFF; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltCtl = 7; - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->CacheFlushOnHaltTmr = 0x28; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC - - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_CTRL1_REG; - OrMask = 0; - AndMask = 0xFF11FF11; - // D18F4x118[CpuPrbEnCstAct0] = 1 - // D18F4x118[CpuPrbEnCstAct1] = 1 - // D18F4x118[CacheFlushEnCstAct0] = 1 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct0 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CpuPrbEnCstAct1 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct0 = 1; - - // Set C-state Action Field 0 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct0 = 2; - // Set C-state Action Field 1 - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushEnCstAct1 = 1; - ((CSTATE_CTRL1_REGISTER *) &OrMask)->CacheFlushTmrSelCstAct1 = 1; - - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x118 - - // D18F4x128[CacheFlushSucMonThreshold] = 0 - PciAddress.Address.Function = FUNC_4; - PciAddress.Address.Register = CSTATE_POLICY_CTRL1_REG; - OrMask = 0; - AndMask = 0xFFFFFFFF; - ((CSTATE_POLICY_CTRL1_REGISTER *) &AndMask)->CacheFlushSucMonThreshold = 0; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x128 - - // D18F3x84[ClkDivisorSmafAct7] = 0 - // D18F3x84[CpuPrbEnSmafAct7] = 1 - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = ACPI_PWR_STATE_CTRL_HI_REG; - OrMask = 0; - AndMask = 0xFFFFFFFF; - ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &AndMask)->ClkDivisorSmafAct7 = 0; - ((ACPI_PWR_STATE_CTRL_HI_REGISTER *) &OrMask)->CpuPrbEnSmafAct7 = 1; - OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x84 - - //Override the default setting - IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); - } -} - -CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt = -{ - 0, - SetF15OrCacheFlushOnHaltRegister -}; diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c deleted file mode 100644 index 4e763517e2..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c +++ /dev/null @@ -1,250 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for core P-states - * - * Performs the "Core Minimum P-State Transition Sequence After Warm Reset" - * as described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrCoreAfterReset.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase1OnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -F15OrPmCoreAfterResetPhase2OnCore ( - IN VOID *HwPsMaxVal, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the necessary steps for core - * P-states after a warm reset has occurred. - * - * The steps are as follows: - * 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. - * 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - * MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - * 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all - * cores in the processor. - * 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - * MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal]. - * 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for - * MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by - * MSRC001_0061[PstateMaxVal]. - * 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmCoreAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 HwPsMaxVal; - PCI_ADDR PciAddress; - AP_TASK TaskPtr; - IDS_SKIP_HOOK (IDS_SKIP_PM_TRANSITION_STEP, CpuEarlyParamsPtr, StdHeader) { - - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); - HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; - - // Launch each local core to perform steps 1 through 3. - TaskPtr.FuncAddress.PfApTask = F15OrPmCoreAfterResetPhase1OnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - - // Launch each local core to perform steps 4 through 6. - TaskPtr.FuncAddress.PfApTaskI = F15OrPmCoreAfterResetPhase2OnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 1; - TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; - TaskPtr.DataTransfer.DataTransferFlags = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - } -} - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all - * cores of a family 15h socket. - * - * This function implements steps 1 - 3 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase1OnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CofvidSts; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; - - // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. - PstateCtrl = 0; - LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - - // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); - LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || - (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); - - // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all - // cores in the processor. - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; - LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmCoreAfterReset to perform MSR initialization on all - * cores of a family 15h socket. - * - * This function implements steps 4 - 6 on each core. - * - * @param[in] HwPsMaxVal Index of the highest enabled HW P-state. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmCoreAfterResetPhase2OnCore ( - IN VOID *HwPsMaxVal, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 TargetPsMsr; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; - - // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from - // MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal]. - LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader); - do { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) || - (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid)); - - // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for - // MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by - // MSRC001_0061[PstateMaxVal]. - if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) { - do { - LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuVid != ((PSTATE_MSR *) &TargetPsMsr)->CpuVid)); - } - - // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. - LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - do { - LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h deleted file mode 100644 index a2a3e748f0..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for core P-states - * - * Contains code that provide power management functionality - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_CORE_AFTER_RESET_H_ -#define _CPU_F15_OR_CORE_AFTER_RESET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmCoreAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_CORE_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c deleted file mode 100644 index 838612acbd..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD DMI Record Creation API, and related functions for Fmaily15h Orichi. - * - * Contains code that produce the DMI related information. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 58290 $ @e \$Date: 2011-08-25 00:02:47 -0600 (Thu, 25 Aug 2011) $ - * - */ -/***************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuFamilyTranslation.h" -#include "cpuPstateTables.h" -#include "cpuLateInit.h" -#include "cpuF15Dmi.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuServices.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ -CONST CHAR8 ROMDATA str_Opteron_62[] = "AMD Opteron(tm) Processor 62"; -CONST CHAR8 ROMDATA str_Opteron_63[] = "AMD Opteron(tm) Processor 63"; -CONST CHAR8 ROMDATA str_Opteron_42[] = "AMD Opteron(tm) Processor 42"; -CONST CHAR8 ROMDATA str_Opteron_3[] = "AMD Opteron(tm) Processor 3"; -CONST CHAR8 ROMDATA str_FX_AM3[] = "AMD FX(tm)-"; -/*--------------------------------------------------------------------------------------- - * Processor Family Table - * 03Dh = "AMD Opteron(TM) 6200 Processor Family" - * 04Dh = "AMD Opteron(TM) 6300 Processor Family" - * 03Eh = "AMD Opteron(TM) 4200 Processor Family" - * 03Fh = "AMD FX(TM) Series Processor" - *-------------------------------------------------------------------------------------*/ -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrG34T4ProcFamily[] = -{ - {str_Opteron_62, 0x3D}, - {str_Opteron_63, 0x4D} -}; - -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrC32T4ProcFamily[] = -{ - {str_Opteron_42, 0x3E} -}; - -CONST CPU_T4_PROC_FAMILY ROMDATA F15OrAM3T4ProcFamily[] = -{ - {str_FX_AM3, 0x3F}, - {str_Opteron_3, 0xE4} -}; -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -DmiF15OrGetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF15OrGetT4ProcFamily ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT8 -DmiF15OrGetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -DmiF15OrGetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -UINT16 -DmiF15OrGetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetInfo - * - * Get CPU type information - * - * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetInfo ( - IN OUT CPU_TYPE_INFO *CpuInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 NumOfCoresPerCU; - CPUID_DATA CpuId; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 - CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 - CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 - CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 - CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 - - CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - // Family 15h Orochi doesn't have CPUID_8000_0001_EBX[BrandId] - CpuInfoPtr->BrandId.Pg = 0; - CpuInfoPtr->BrandId.String1 = 0; - CpuInfoPtr->BrandId.Model = 0; - CpuInfoPtr->BrandId.String2 = 0; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); - CpuInfoPtr->TotalCoreNumber--; - - LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); - CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 - - switch (CpuInfoPtr->PackageType) { - case OR_SOCKET_AM3: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3; - break; - case OR_SOCKET_G34: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34; - break; - case OR_SOCKET_C32: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32; - break; - default: - CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; - break; - } - - switch (GetComputeUnitMapping (StdHeader)) { - case AllCoresMapping: - NumOfCoresPerCU = 1; - break; - case EvenCoresMapping: - NumOfCoresPerCU = 2; - break; - default: - NumOfCoresPerCU = 2; - } - LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader); - CpuInfoPtr->L1CacheSize = (UINT32) (((UINT8) ((CpuId.ECX_Reg >> 24) * NumOfCoresPerCU) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); - - LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); - CpuInfoPtr->L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetT4ProcFamily - * - * Get type 4 processor family information - * - * @param[in,out] T4ProcFamily Pointer to type 4 processor family information. - * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service - * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetT4ProcFamily ( - IN OUT UINT8 *T4ProcFamily, - IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, - IN CPU_TYPE_INFO *CpuInfo, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CHAR8 NameString[49]; - CONST CHAR8 *DmiString; - CONST VOID *DmiStringTable; - UINT8 NumberOfDmiString; - UINT8 i; - - // Get name string from MSR_C001_00[30:35] - GetNameString (NameString, StdHeader); - // Get DMI String - DmiStringTable = NULL; - switch (CpuInfo->PackageType) { - case OR_SOCKET_G34: - DmiStringTable = (CONST VOID *) &F15OrG34T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrG34T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - case OR_SOCKET_C32: - DmiStringTable = (CONST VOID *) &F15OrC32T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrC32T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - case OR_SOCKET_AM3: - DmiStringTable = (CONST VOID *) &F15OrAM3T4ProcFamily[0]; - NumberOfDmiString = sizeof (F15OrAM3T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); - break; - default: - DmiStringTable = NULL; - NumberOfDmiString = 0; - break; - } - - // Find out which DMI string matches currect processor's name string - *T4ProcFamily = P_FAMILY_UNKNOWN; - if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) { - for (i = 0; i < NumberOfDmiString; i++) { - DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart; - if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) { - *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting; - } - } - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetVoltage - * - * Get the voltage value according to SMBIOS SPEC's requirement. - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval Voltage - CPU Voltage. - * - */ -UINT8 -DmiF15OrGetVoltage ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 MaxVid; - UINT8 Voltage; - UINT8 NumberBoostStates; - UINT32 CurrentNodeNum; - UINT64 MsrData; - PCI_ADDR TempAddr; - CPB_CTRL_REGISTER CpbCtrl; - - // Voltage = 0x80 + (voltage at boot time * 10) - GetCurrentNodeNum (&CurrentNodeNum, StdHeader); - TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_4, CPB_CTRL_REG); - LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C - NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; - - LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - - - if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { - Voltage = 0; - } else { - Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000); - } - - Voltage += 0x80; - return (Voltage); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetMemInfo - * - * Get memory information. - * - * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. - * @param[in] StdHeader Standard Head Pointer - * - */ -VOID -DmiF15OrGetMemInfo ( - IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 PciData; - PCI_ADDR PciAddress; - - CpuGetMemInfoPtr->EccCapable = FALSE; - // Orochi uses the different way of access to each DCT - // - // Switch to DCT 0 - // - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData &= 0xFFFFFFFE; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x90[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } else { - // - // Switch to DCT 1 - // - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData |= 0x00000001; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - // Check if F2x90[DimmEccEn] is set - if ((PciData & 0x00080000) != 0) { - CpuGetMemInfoPtr->EccCapable = TRUE; - } - } - // Errata #505 - PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_1, 0x10C); - LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); - PciData &= 0xFFFFFFFE; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); - // Partition Row Position - 0 is for dual channel memory - CpuGetMemInfoPtr->PartitionRowPosition = 0; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * DmiF15OrGetExtClock - * - * Get the external clock Speed - * - * @param[in] StdHeader Standard Head Pointer - * - * @retval ExtClock - CPU external clock Speed. - * - */ -UINT16 -DmiF15OrGetExtClock ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return (EXTERNAL_CLOCK_DFLT); -} - -CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15OrDmiTable = -{ -// This table is for Processor family 15h Orochi - AMD_FAMILY_15_OR, // ID for Family 15h Orochi - DmiF15OrGetInfo, // Transfer vectors for family - DmiF15OrGetT4ProcFamily, // Get type 4 processor family information - DmiF15OrGetVoltage, // specific routines (above) - DmiF15GetMaxSpeed, - DmiF15OrGetExtClock, - DmiF15OrGetMemInfo, // Get memory information - 0, - NULL -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c deleted file mode 100644 index b1aa42f173..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c +++ /dev/null @@ -1,422 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific feature leveling functions. - * - * Provides feature leveling functions specific to family 15h models 00h-0Fh. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "cpuPostInit.h" -#include "cpuF15OrFeatureLeveling.h" -#include "cpuFamilyTranslation.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function get features which CPU supports. - * - * @CpuServiceMethod{::F_CPU_SAVE_FEATURES}. - * - * Read features from MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F15OrSaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - BOOLEAN *FirstTime; - BOOLEAN *NeedLeveling; - CPU_F15_OR_FEATURES *CpuF15OrFeatures; - CPU_F15_OR_EXT_FEATURES *CpuF15OrExtFeatures; - CPU_FEATURES_LIST thisCoreCpuFeatureList; - - FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST)); - NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); - - LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader); - LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - CpuF15OrFeatures = (CPU_F15_OR_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.APIC = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.APIC; - thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CLFSH; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.DE; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.FXSR; - thisCoreCpuFeatureList.HTT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.HTT; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MMX; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.MTRR; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PAE; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE36; - thisCoreCpuFeatureList.SSE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE; - thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE2; - thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.SysEnterSysExit; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesLo.VME; - - thisCoreCpuFeatureList.AES = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.AES; - thisCoreCpuFeatureList.AVX = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.AVX; - thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.CMPXCHG16B; - thisCoreCpuFeatureList.Monitor = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.Monitor; - thisCoreCpuFeatureList.OSXSAVE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.OSXSAVE; - thisCoreCpuFeatureList.PCLMULQDQ = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.PCLMULQDQ; - thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.POPCNT; - thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE3; - thisCoreCpuFeatureList.SSE41 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE41; - thisCoreCpuFeatureList.SSE42 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE42; - thisCoreCpuFeatureList.SSSE3 = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.SSSE3; - thisCoreCpuFeatureList.X2APIC = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.X2APIC; - thisCoreCpuFeatureList.XSAVE = (UINT8) CpuF15OrFeatures->CpuF15OrFeaturesHi.XSAVE; - - LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); - CpuF15OrExtFeatures = (CPU_F15_OR_EXT_FEATURES *) &CpuMsrData; - - thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNow; - thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNowExt; - thisCoreCpuFeatureList.APIC = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.APIC; - thisCoreCpuFeatureList.CMOV = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMOV; - thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMPXCHG8B; - thisCoreCpuFeatureList.DE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.DE; - thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FFXSR; - thisCoreCpuFeatureList.FPU = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FPU; - thisCoreCpuFeatureList.FXSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FXSR; - thisCoreCpuFeatureList.LM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.LM; - thisCoreCpuFeatureList.MCA = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCA; - thisCoreCpuFeatureList.MCE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCE; - thisCoreCpuFeatureList.MMX = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MMX; - thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MmxExt; - thisCoreCpuFeatureList.MSR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MSR; - thisCoreCpuFeatureList.MTRR = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MTRR; - thisCoreCpuFeatureList.NX = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.NX; - thisCoreCpuFeatureList.PAE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAE; - thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.Page1GB; - thisCoreCpuFeatureList.PAT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAT; - thisCoreCpuFeatureList.PGE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PGE; - thisCoreCpuFeatureList.PSE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE; - thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE36; - thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.RDTSCP; - thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.SysCallSysRet; - thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.TimeStampCounter; - thisCoreCpuFeatureList.VME = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.VME; - - thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ThreeDNowPrefetch; - thisCoreCpuFeatureList.ABM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ABM; - thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.AltMovCr8; - thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.CmpLegacy; - thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ExtApicSpace; - thisCoreCpuFeatureList.IBS = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.IBS; - thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LahfSahf; - thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.MisAlignSse; - thisCoreCpuFeatureList.OSVW = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.OSVM; - thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SKINIT; - thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SSE4A; - thisCoreCpuFeatureList.SVM = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SVM; - thisCoreCpuFeatureList.WDT = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.WDT; - thisCoreCpuFeatureList.NodeId = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.NodeId; - thisCoreCpuFeatureList.XOP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.XOP; - thisCoreCpuFeatureList.TBM0 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TBM0; - thisCoreCpuFeatureList.LWP = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LWP; - thisCoreCpuFeatureList.FMA4 = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.FMA4; - thisCoreCpuFeatureList.TCE = (UINT8) CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TCE; - - if (*FirstTime) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *FirstTime = FALSE; - } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) { - updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList); - *NeedLeveling = TRUE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function set features which All CPUs support. - * - * @CpuServiceMethod{::F_CPU_WRITE_FEATURES}. - * - * Write least common features to MSR_C0011004 and MSR_C0011005. - * - * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct. - * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct. - * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. - * - */ -VOID -F15OrWriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT64 CpuMsrData; - CPU_F15_OR_FEATURES *CpuF15OrFeatures; - CPU_F15_OR_EXT_FEATURES *CpuF15OrExtFeatures; - - CpuMsrData = 0; - CpuF15OrFeatures = (CPU_F15_OR_FEATURES *) &CpuMsrData; - - CpuF15OrFeatures->CpuF15OrFeaturesLo.APIC = cpuFeatureList->APIC; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CLFSH = cpuFeatureList->CLFSH; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF15OrFeatures->CpuF15OrFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF15OrFeatures->CpuF15OrFeaturesLo.DE = cpuFeatureList->DE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.FPU = cpuFeatureList->FPU; - CpuF15OrFeatures->CpuF15OrFeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.HTT = cpuFeatureList->HTT; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MCA = cpuFeatureList->MCA; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MCE = cpuFeatureList->MCE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MMX = cpuFeatureList->MMX; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MSR = cpuFeatureList->MSR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PAE = cpuFeatureList->PAE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PAT = cpuFeatureList->PAT; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PGE = cpuFeatureList->PGE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE = cpuFeatureList->PSE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE = cpuFeatureList->SSE; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SSE2 = cpuFeatureList->SSE2; - CpuF15OrFeatures->CpuF15OrFeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit; - CpuF15OrFeatures->CpuF15OrFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF15OrFeatures->CpuF15OrFeaturesLo.VME = cpuFeatureList->VME; - - CpuF15OrFeatures->CpuF15OrFeaturesHi.AES = cpuFeatureList->AES; - CpuF15OrFeatures->CpuF15OrFeaturesHi.AVX = cpuFeatureList->AVX; - CpuF15OrFeatures->CpuF15OrFeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B; - CpuF15OrFeatures->CpuF15OrFeaturesHi.Monitor = cpuFeatureList->Monitor; - CpuF15OrFeatures->CpuF15OrFeaturesHi.OSXSAVE = cpuFeatureList->OSXSAVE; - CpuF15OrFeatures->CpuF15OrFeaturesHi.PCLMULQDQ = cpuFeatureList->PCLMULQDQ; - CpuF15OrFeatures->CpuF15OrFeaturesHi.POPCNT = cpuFeatureList->POPCNT; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE3 = cpuFeatureList->SSE3; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE41 = cpuFeatureList->SSE41; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSE42 = cpuFeatureList->SSE42; - CpuF15OrFeatures->CpuF15OrFeaturesHi.SSSE3 = cpuFeatureList->SSSE3; - CpuF15OrFeatures->CpuF15OrFeaturesHi.X2APIC = cpuFeatureList->X2APIC; - CpuF15OrFeatures->CpuF15OrFeaturesHi.XSAVE = cpuFeatureList->XSAVE; - - LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader); - - CpuMsrData = 0; - CpuF15OrExtFeatures = (CPU_F15_OR_EXT_FEATURES *) &CpuMsrData; - - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.APIC = cpuFeatureList->APIC; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMOV = cpuFeatureList->CMOV; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.DE = cpuFeatureList->DE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FPU = cpuFeatureList->FPU; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.FXSR = cpuFeatureList->FXSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.LM = cpuFeatureList->LM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCA = cpuFeatureList->MCA; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MCE = cpuFeatureList->MCE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MMX = cpuFeatureList->MMX; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MSR = cpuFeatureList->MSR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.MTRR = cpuFeatureList->MTRR; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.NX = cpuFeatureList->NX; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAE = cpuFeatureList->PAE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PAT = cpuFeatureList->PAT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PGE = cpuFeatureList->PGE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE = cpuFeatureList->PSE; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.PSE36 = cpuFeatureList->PSE36; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesLo.VME = cpuFeatureList->VME; - - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ABM = cpuFeatureList->ABM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.IBS = cpuFeatureList->IBS; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.OSVM = cpuFeatureList->OSVW; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.SVM = cpuFeatureList->SVM; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.WDT = cpuFeatureList->WDT; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.NodeId = cpuFeatureList->NodeId; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.XOP = cpuFeatureList->XOP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TBM0 = cpuFeatureList->TBM0; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.LWP = cpuFeatureList->LWP; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.FMA4 = cpuFeatureList->FMA4; - CpuF15OrExtFeatures->CpuF15OrExtFeaturesHi.TCE = cpuFeatureList->TCE; - - LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * cpuFeatureListNeedUpdate - * - * Compare global CPU feature list with this core feature list to see if global CPU feature list - * needs updated. - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - * @retval FALSE globalCpuFeatureList is equal to thisCoreCpuFeatureList - * @retval True globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList - */ -BOOLEAN -STATIC -cpuFeatureListNeedUpdate ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - BOOLEAN flag; - UINT8 *global; - UINT8 *thisCore; - UINT8 i; - - flag = FALSE; - global = (UINT8 *) globalCpuFeatureList; - thisCore = (UINT8 *) thisCoreCpuFeatureList; - - for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) { - if ((*global) != (*thisCore)) { - flag = TRUE; - break; - } - global++; - thisCore++; - } - return flag; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * updateCpuFeatureList - * - * Update global CPU feature list - * - * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List. - * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List. - * - */ -VOID -STATIC -updateCpuFeatureList ( - IN CPU_FEATURES_LIST *globalCpuFeatureList, - IN CPU_FEATURES_LIST *thisCoreCpuFeatureList - ) -{ - UINT8 *globalFeatureList; - UINT8 *thisCoreFeatureList; - UINT32 sizeInByte; - - globalFeatureList = (UINT8 *) globalCpuFeatureList; - thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList; - - for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) { - *globalFeatureList &= *thisCoreFeatureList; - globalFeatureList++; - thisCoreFeatureList++; - } -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h deleted file mode 100644 index dd644d6392..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h +++ /dev/null @@ -1,211 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi specific feature leveling functions. - * - * Provides feature leveling functions specific to family 15h. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_FEATURE_LEVELING_H_ -#define _CPU_F15_OR_FEATURE_LEVELING_H_ - -#include "cpuFamilyTranslation.h" -#include "cpuPostInit.h" -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ -/// F15 Orochi CPU Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 :1; ///< Bit10 - UINT32 SysEnterSysExit:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 :1; ///< Bit18 - UINT32 CLFSH:1; ///< Bit19 - UINT32 :3; ///< Bit20~22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 SSE:1; ///< Bit25 - UINT32 SSE2:1; ///< Bit26 - UINT32 :1; ///< Bit27 - UINT32 HTT:1; ///< Bit28 - UINT32 :3; ///< Bit29~31 -} CPU_F15_OR_FEATURES_LO; - -/// F15 Orochi CPU Feature High -typedef struct { - UINT32 SSE3:1; ///< Bit0 - UINT32 PCLMULQDQ:1; ///< Bit1 - UINT32 :1; ///< Bit2 - UINT32 Monitor:1; ///< Bit3 - UINT32 :5; ///< Bit4~8 - UINT32 SSSE3:1; ///< Bit9 - UINT32 :3; ///< Bit10~12 - UINT32 CMPXCHG16B:1; ///< Bit13 - UINT32 :5; ///< Bit14~18 - UINT32 SSE41:1; ///< Bit19 - UINT32 SSE42:1; ///< Bit20 - UINT32 X2APIC:1; ///< Bit21 - UINT32 :1; ///< Bit22 - UINT32 POPCNT:1; ///< Bit23 - UINT32 :1; ///< Bit24 - UINT32 AES:1; ///< Bit25 - UINT32 XSAVE:1; ///< Bit26 - UINT32 OSXSAVE:1; ///< Bit27 - UINT32 AVX:1; ///< Bit28 - UINT32 :3; ///< Bit29~32 -} CPU_F15_OR_FEATURES_HI; - -/// F15 Orochi CPU Feature -typedef struct { - CPU_F15_OR_FEATURES_LO CpuF15OrFeaturesLo; ///< Low - CPU_F15_OR_FEATURES_HI CpuF15OrFeaturesHi; ///< High -} CPU_F15_OR_FEATURES; - -/// F15 Orochi CPU Extended Feature Low -typedef struct { - UINT32 FPU:1; ///< Bit0 - UINT32 VME:1; ///< Bit1 - UINT32 DE:1; ///< Bit2 - UINT32 PSE:1; ///< Bit3 - UINT32 TimeStampCounter:1; ///< Bit4 - UINT32 MSR:1; ///< Bit5 - UINT32 PAE:1; ///< Bit6 - UINT32 MCE:1; ///< Bit7 - UINT32 CMPXCHG8B:1; ///< Bit8 - UINT32 APIC:1; ///< Bit9 - UINT32 :1; ///< Bit10 - UINT32 SysCallSysRet:1; ///< Bit11 - UINT32 MTRR:1; ///< Bit12 - UINT32 PGE:1; ///< Bit13 - UINT32 MCA:1; ///< Bit14 - UINT32 CMOV:1; ///< Bit15 - UINT32 PAT:1; ///< Bit16 - UINT32 PSE36:1; ///< Bit17 - UINT32 :2; ///< Bit18~19 - UINT32 NX:1; ///< Bit20 - UINT32 :1; ///< Bit21 - UINT32 MmxExt:1; ///< Bit22 - UINT32 MMX:1; ///< Bit23 - UINT32 FXSR:1; ///< Bit24 - UINT32 FFXSR:1; ///< Bit25 - UINT32 Page1GB:1; ///< Bit26 - UINT32 RDTSCP:1; ///< Bit27 - UINT32 :1; ///< Bit28 - UINT32 LM:1; ///< Bit29 - UINT32 ThreeDNowExt:1; ///< Bit30 - UINT32 ThreeDNow:1; ///< Bit31 -} CPU_F15_OR_EXT_FEATURES_LO; - -/// F15 Orochi CPU Extended Feature High -typedef struct { - UINT32 LahfSahf:1; ///< Bit0 - UINT32 CmpLegacy:1; ///< Bit1 - UINT32 SVM:1; ///< Bit2 - UINT32 ExtApicSpace:1; ///< Bit3 - UINT32 AltMovCr8:1; ///< Bit4 - UINT32 ABM:1; ///< Bit5 - UINT32 SSE4A:1; ///< Bit6 - UINT32 MisAlignSse:1; ///< Bit7 - UINT32 ThreeDNowPrefetch:1; ///< Bit8 - UINT32 OSVM:1; ///< Bit9 - UINT32 IBS:1; ///< Bit10 - UINT32 XOP:1; ///< Bit11 - UINT32 SKINIT:1; ///< Bit12 - UINT32 WDT:1; ///< Bit13 - UINT32 TBM0:1; ///< Bit14 - UINT32 LWP:1; ///< Bit15 - UINT32 FMA4:1; ///< Bit16 - UINT32 TCE:1; ///< Bit17 - UINT32 :1; ///< Bit18 - UINT32 NodeId:1; ///< Bit19 - UINT32 :12; ///< Bit20~31 -} CPU_F15_OR_EXT_FEATURES_HI; - -/// F15 Orochi CPU Extended Feature -typedef struct { - CPU_F15_OR_EXT_FEATURES_LO CpuF15OrExtFeaturesLo; ///< Low - CPU_F15_OR_EXT_FEATURES_HI CpuF15OrExtFeaturesHi; ///< High -} CPU_F15_OR_EXT_FEATURES; -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrSaveFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -F15OrWriteFeatures ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN OUT CPU_FEATURES_LIST *cpuFeatureList, - IN AMD_CONFIG_PARAMS *StdHeader - ); -#endif // _CPU_F15_OR_FEATURE_LEVELING_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c deleted file mode 100644 index 0d6b115b9d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c +++ /dev/null @@ -1,349 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for NB P-states - * - * Performs the "NB COF and VID Transition Sequence After Warm Reset" - * as described in the BKDG. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "cpuRegisters.h" -#include "cpuApicUtilities.h" -#include "cpuFamilyTranslation.h" -#include "GeneralServices.h" -#include "cpuServices.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrNbAfterReset.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrPmNbAfterResetOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -TransitionToNbLow ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -TransitionToNbHigh ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -STATIC -WaitForNbTransitionToComplete ( - IN PCI_ADDR PciAddress, - IN UINT32 PstateIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family 15h Orochi core 0 entry point for performing the necessary steps after - * a warm reset has occurred. - * - * The steps are as follows: - * 1. Temp1 = D18F5x170[SwNbPstateLoDis]. - * 2. Temp2 = D18F5x170[NbPstateDisOnP0]. - * 3. Temp3 = D18F5x170[NbPstateThreshold]. - * 4. If MSRC001_0070[NbPstate] = 1, go to step 9. - * 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - * 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - * 7. Set D18F5x170[SwNbPstateLoDis] = 1. - * 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - * Go to step 13. - * 9. Set D18F5x170[SwNbPstateLoDis] = 1. - * 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - * 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - * 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - * CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - * 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and - * D18F5x170[NbPstateThreshold] = Temp3. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -F15OrPmNbAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT32 TaskedCore; - UINT32 Ignored; - AP_TASK TaskPtr; - AGESA_STATUS IgnoredSts; - - IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); - - ASSERT (Core == 0); - - // Launch one core per node. - TaskPtr.FuncAddress.PfApTask = F15OrPmNbAfterResetOnCore; - TaskPtr.DataTransfer.DataSizeInDwords = 0; - TaskPtr.ExeFlags = WAIT_FOR_CORE; - for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { - if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { - if (TaskedCore != 0) { - ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); - } - } - } - ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); -} - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterReset to perform MSR initialization on one - * core of each die in a family 15h socket. - * - * This function implements steps 1 - 13 on each core. - * - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -F15OrPmNbAfterResetOnCore ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrlOnEntry; - UINT32 NbPsCtrlOnExit; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - // 1. Temp1 = D18F5x170[SwNbPstateLoDis]. - // 2. Temp2 = D18F5x170[NbPstateDisOnP0]. - // 3. Temp3 = D18F5x170[NbPstateThreshold]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader); - - // Check if NB P-states were disabled, and if so, prevent any changes from occurring. - if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateMaxVal != 0) { - // 4. If MSRC001_0070[NbPstate] = 1, go to step 9 - LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); - if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) { - // 5. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - // 6. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - TransitionToNbLow (PciAddress, StdHeader); - - // 7. Set D18F5x170[SwNbPstateLoDis] = 1. - // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - // Go to step 13. - TransitionToNbHigh (PciAddress, StdHeader); - } else { - // 9. Set D18F5x170[SwNbPstateLoDis] = 1. - // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - TransitionToNbHigh (PciAddress, StdHeader); - - // 11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - TransitionToNbLow (PciAddress, StdHeader); - } - - // 13. Set D18F5x170[SwNbPstateLoDis] = Temp1, D18F5x170[NbPstateDisOnP0] = Temp2, and - // D18F5x170[NbPstateThreshold] = Temp3. - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterResetOnCore to transition to the low NB P-state. - * - * This function implements steps 5, 6, 11, and 12 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -TransitionToNbLow ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - - // 5/11. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0; - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - // 6/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. - WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmNbAfterResetOnCore to transition to the high NB P-state. - * - * This function implements steps 7, 8, 9, and 10 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -TransitionToNbHigh ( - IN PCI_ADDR PciAddress, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NbPsCtrl; - - // 7/9. Set D18F5x170[SwNbPstateLoDis] = 1. - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); - - // 8/10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, - // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. - WaitForNbTransitionToComplete (PciAddress, ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi, StdHeader); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Support routine for F15OrPmAfterResetCore to wait for NB FID and DID to - * match a specific P-state. - * - * This function implements steps 6, 8, 10, and 12 as needed. - * - * @param[in] PciAddress Segment, bus, device number of the node to transition. - * @param[in] PstateIndex P-state settings to match. - * @param[in] StdHeader Config handle for library and services. - * - */ -VOID -STATIC -WaitForNbTransitionToComplete ( - IN PCI_ADDR PciAddress, - IN UINT32 PstateIndex, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TargetNbPs; - UINT32 NbPsSts; - - PciAddress.Address.Function = FUNC_5; - PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2); - LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader); - PciAddress.Address.Register = NB_PSTATE_STATUS; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); - } while ((((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbPstate != PstateIndex || - (((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbFid != ((NB_PSTATE_REGISTER *) &TargetNbPs)->NbFid)) || - (((NB_PSTATE_STS_REGISTER *) &NbPsSts)->CurNbDid != ((NB_PSTATE_REGISTER *) &TargetNbPs)->NbDid)); -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h deleted file mode 100644 index 710d43db4f..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi after warm reset sequence for NB P-states - * - * Contains code that provide power management functionality - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_NB_AFTER_RESET_H_ -#define _CPU_F15_OR_NB_AFTER_RESET_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmNbAfterReset ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_NB_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h deleted file mode 100644 index 5d66252c9b..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h +++ /dev/null @@ -1,534 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Power Management related stuff - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 60669 $ @e \$Date: 2011-10-19 17:17:41 -0600 (Wed, 19 Oct 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_POWERMGMT_H_ -#define _CPU_F15_OR_POWERMGMT_H_ - -/* - * Family 15h Orochi CPU Power Management MSR definitions - * - */ - - -/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */ -#define MSR_INTPEND 0xC0010055 - -/// Interrupt Pending and CMP-Halt MSR Register -typedef struct { - UINT64 IoMsgAddr:16; ///< IO message address - UINT64 IoMsgData:8; ///< IO message data - UINT64 IntrPndMsgDis:1; ///< Interrupt pending message disable - UINT64 IntrPndMsg:1; ///< Interrupt pending message - UINT64 IoRd:1; ///< IO read - UINT64 :2; ///< Reserved - UINT64 BmStsClrOnHltEn:1; ///< Clear BM status bit on server C1e entry - UINT64 :34; ///< Reserved -} INTPEND_MSR; - - -/* P-state Registers 0xC001006[B:4] */ - -/// P-state MSR -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 :6; ///< Reserved - UINT64 NbPstate:1; ///< NbPstate - UINT64 :9; ///< Reserved - UINT64 IddValue:8; ///< IddValue - UINT64 IddDiv:2; ///< IddDiv - UINT64 :21; ///< Reserved - UINT64 PsEnable:1; ///< Pstate Enable -} PSTATE_MSR; - - -/* COFVID Control Register 0xC0010070 */ -#define MSR_COFVID_CTL 0xC0010070 - -/// COFVID Control MSR Register -typedef struct { - UINT64 CpuFid:6; ///< CpuFid - UINT64 CpuDid:3; ///< CpuDid - UINT64 CpuVid:7; ///< CpuVid - UINT64 PstateId:3; ///< Pstate ID - UINT64 :3; ///< Reserved - UINT64 NbPstate:1; ///< Northbridge P-state - UINT64 :41; ///< Reserved -} COFVID_CTRL_MSR; - - -/* COFVID Status Register 0xC0010071 */ -#define MSR_COFVID_STS 0xC0010071 - -/// COFVID Status MSR Register -typedef struct { - UINT64 CurCpuFid:6; ///< Current CpuFid - UINT64 CurCpuDid:3; ///< Current CpuDid - UINT64 CurCpuVid:7; ///< Current CpuVid - UINT64 CurPstate:3; ///< Current Pstate - UINT64 :3; ///< Reserved - UINT64 CurNbDid:1; ///< Current NbDid - UINT64 :2; ///< Reserved - UINT64 CurNbVid:7; ///< Current NbVid - UINT64 StartupPstate:3; ///< Startup Pstate - UINT64 MaxVid:7; ///< MaxVid - UINT64 MinVid:7; ///< MinVid - UINT64 MaxCpuCof:6; ///< MaxCpuCof - UINT64 :1; ///< Reserved - UINT64 CurPstateLimit:3; ///< Current Pstate Limit - UINT64 MaxNbCof:5; ///< MaxNbCof -} COFVID_STS_MSR; - -/* Floating Point Configuration Register 0xC0011028 */ -#define MSR_FP_CFG 0xC0011028 - -/// Floating Point Configuration MSR Register -typedef struct { - UINT64 :16; ///< Reserved - UINT64 DiDtMode:1; ///< Di/Dt Mode - UINT64 :1; ///< Reserved - UINT64 DiDtCfg0:5; ///< Di/Dt Config 0 - UINT64 :2; ///< Reserved - UINT64 AlwaysOnThrottle:2; ///< AlwaysOnThrottle - UINT64 DiDtCfg1:8; ///< Di/Dt Config 1 - UINT64 :5; ///< Reserved - UINT64 Pipe3ThrottleDis:1; ///< Pipe3ThrottleDis - UINT64 :23; ///< Reserved -} FP_CFG_MSR; - -/* - * Family 15h Orochi CPU Power Management PCI definitions - * - */ - -/* Link transaction control register F0x68 */ -#define LTC_REG 0x68 - -/// Link Transaction Control Register -typedef struct { - UINT32 :12; ///< Reserved - UINT32 ATMModeEn:1; ///< Accelerated transition to modified mode enable - UINT32 :19; ///< Reserved -} LTC_REGISTER; - -/* DRAM Configuration High Register F2x[1,0]94 */ -#define DRAM_CFG_HI_REG0 0x94 -#define DRAM_CFG_HI_REG1 0x194 - -/// DRAM Configuration High PCI Register -typedef struct { - UINT32 MemClkFreq:5; ///< Memory clock frequency - UINT32 :2; ///< Reserved - UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid - UINT32 :2; ///< Reserved - UINT32 ZqcsInterval:2; ///< ZQ calibration short interval - UINT32 :1; ///< Reserved - UINT32 DisSimulRdWr:1; ///< Disable simultaneous read and write - UINT32 DisDramInterface:1; ///< Disable the DRAM interface - UINT32 PowerDownEn:1; ///< Power down mode enable - UINT32 PowerDownMode:1; ///< Power down mode - UINT32 FourRankRDimm1:1; ///< Four rank registered DIMM 1 - UINT32 FourRankRDimm0:1; ///< Four rank registered DIMM 0 - UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable - UINT32 SlowAccessMode:1; ///< Slow access mode - UINT32 FreqChgInProg:1; ///< Frequency change in progress - UINT32 BankSwizzleMode:1; ///< Bank swizzle mode - UINT32 ProcOdtDis:1; ///< Processor on-die termination disable - UINT32 DcqBypassMax:4; ///< DRAM controller queue bypass maximum - UINT32 :4; ///< Reserved -} DRAM_CFG_HI_REGISTER; - - -/* Scrub Rate Control Register F3x58 */ -#define SCRUB_RATE_CTRL_REG 0x58 - -/// Scrub Rate Control PCI Register -typedef struct { - UINT32 DramScrub:5; ///< DRAM scrub rate - UINT32 :19; ///< Reserved - UINT32 L3Scrub:5; ///< L3 cache scrub rate - UINT32 :3; ///< Reserved -} SCRUB_RATE_CTRL_REGISTER; - -/* DRAM Scrub Address Low Register F3x5C */ -#define DRAM_SCRUB_ADDR_LOW_REG 0x5C - -/// DRAM Scrub Address Low PCI Register -typedef struct { - UINT32 ScrubReDirEn:1; ///< DRAM scrubber redirect enable - UINT32 :5; ///< Reserved - UINT32 ScrubAddr:26; ///< DRAM scrubber address bits[31:6] -} DRAM_SCRUB_ADDR_LOW_REGISTER; - -/* Free List Buffer Count Register F3x7C */ -#define FREE_LIST_BUFFER_COUNT_REG 0x7C - -/// Free List Buffer Count PCI Register -typedef struct { - UINT32 Xbar2SriFreeListCBC:5; ///< XBAR to SRI free list command buffer count - UINT32 :3; ///< Reserved - UINT32 Sri2XbarFreeXreqCBC:4; ///< SRI to XBAR free request and posted request command buffer count - UINT32 Sri2XbarFreeRspCBC:4; ///< SRI to XBAR free response command buffer count - UINT32 Sri2XbarFreeXreqDBC:4; ///< SRI to XBAR free request and posted request data buffer count - UINT32 Sri2XbarFreeRspDBC:3; ///< SRI to XBAR free response data buffer count - UINT32 SrqExtFreeListBc:4; ///< extend SRQ freelist tokens - UINT32 :1; ///< Reserved - UINT32 Xbar2SriFreeListCbInc:3; ///< XBAR to SRI free list command buffer increment - UINT32 :1; ///< Reserved -} FREE_LIST_BUFFER_COUNT_REGISTER; - -/* ACPI Power State Control High F3x84 */ -#define ACPI_PWR_STATE_CTRL_HI_REG 0x84 - -/// ACPI Power State Control High PCI Register -typedef struct { - UINT32 CpuPrbEnSmafAct4:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct4:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct4:1; ///< NB gate enable - UINT32 NbCofChgSmafAct4:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct4:3; ///< clock divisor - UINT32 :8; ///< Reserved - UINT32 CpuPrbEnSmafAct6:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct6:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct6:1; ///< NB gate enable - UINT32 NbCofChgSmafAct6:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct6:3; ///< clock divisor - UINT32 CpuPrbEnSmafAct7:1; ///< CPU direct probe enable - UINT32 NbLowPwrEnSmafAct7:1; ///< NB low-power enable - UINT32 NbGateEnSmafAct7:1; ///< NB gate enable - UINT32 NbCofChgSmafAct7:1; ///< NB FID change - UINT32 :1; ///< Reserved - UINT32 ClkDivisorSmafAct7:3; ///< clock divisor -} ACPI_PWR_STATE_CTRL_HI_REGISTER; - -/* Power Control Miscellaneous Register F3xA0 */ -#define PW_CTL_MISC_REG 0xA0 - -/// Power Control Miscellaneous PCI Register -typedef struct { - UINT32 PsiVid:7; ///< PSI_L VID threshold - UINT32 PsiVidEn:1; ///< PSI_L VID enable - UINT32 :1; ///< Reserved - UINT32 SviHighFreqSel:1; ///< SVI high frequency select - UINT32 IdleExitEn:1; ///< IDLEEXIT_L Enable - UINT32 PllLockTime:3; ///< PLL synchronization lock time - UINT32 :2; ///< Reserved - UINT32 ConfigId:12; ///< Configuration ID - UINT32 NbPstateForce:1; ///< NB P-state force on next LDTSTOP assertion - UINT32 :2; ///< Reserved - UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed -} POWER_CTRL_MISC_REGISTER; - - -/* Clock Power/Timing Control 0 Register F3xD4 */ -#define CPTC0_REG 0xD4 -#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) - -/// Clock Power Timing Control PCI Register -typedef struct { - UINT32 NbFid:5; ///< NbFid - UINT32 NbFidEn:1; ///< NbFidEn - UINT32 :2; ///< Reserved - UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select - UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control - UINT32 MTC1eEn:1; ///< Message Triggered C1e Enable - UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt - UINT32 StutterScrubEn:1; ///< Stutter Mode Scrub Enable - UINT32 LnkPllLock:2; ///< Link PLL Lock - UINT32 :2; ///< Reserved - UINT32 PowerStepDown:4; ///< Power Step Down - UINT32 PowerStepUp:4; ///< Power Step Up - UINT32 NbClkDiv:3; ///< NbClkDiv - UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll -} CLK_PWR_TIMING_CTRL_REGISTER; - - -/* Clock Power/Timing Control 1 Register F3xD8 */ -#define CPTC1_REG 0xD8 -#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) - -/// Clock Power Timing Control 1 PCI Register -typedef struct { - UINT32 :4; ///< Reserved - UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time - UINT32 :17; ///< Reserved - UINT32 ReConDel:4; ///< Link reconnect delay - UINT32 :4; ///< Reserved -} CLK_PWR_TIMING_CTRL1_REGISTER; - - -/* Northbridge Capabilities Register F3xE8 */ -#define NB_CAPS_REG 0xE8 - -/// Northbridge Capabilities PCI Register -typedef struct { - UINT32 :1; ///< Reserved - UINT32 DualNode:1; ///< Dual-node multi-processor capable - UINT32 EightNode:1; ///< Eight-node multi-processor capable - UINT32 Ecc:1; ///< ECC capable - UINT32 Chipkill:1; ///< Chipkill ECC capable - UINT32 :3; ///< Reserved - UINT32 MctCap:1; ///< Memory controller capable - UINT32 SvmCapable:1; ///< SVM capable - UINT32 HtcCapable:1; ///< HTC capable - UINT32 LnkRtryCap:1; ///< Link error-retry capable - UINT32 :2; ///< Reserved - UINT32 MultVidPlane:1; ///< Multiple VID plane capable - UINT32 :1; ///< Reserved - UINT32 MpCap:3; ///< MP capability - UINT32 x2Apic:1; ///< x2Apic capability - UINT32 UnGangEn:4; ///< Link unganging enabled - UINT32 :1; ///< Reserved - UINT32 L3Capable:1; ///< L3 capable - UINT32 :3; ///< Reserved - UINT32 MultiNodeCpu:1; ///< Multinode processor - UINT32 IntNodeNum:2; ///< Internal node number -} NB_CAPS_REGISTER; - -/* L3 Buffer Count */ -#define L3_BUFFER_COUNT_REG 0x1A0 - -/// L3 Buffer Count -typedef struct { - UINT32 CpuCmdBufCnt:3; ///< CPU to SRI command buffer count - UINT32 :1; ///< Reserved - UINT32 L3FreeListCBC:5; ///< L3 free list command buffer counter for compute unit requests - UINT32 :3; ///< Reserved - UINT32 L3ToSriReqCBC:3; ///< L3 cache to SRI request command buffer count - UINT32 :1; ///< Reserved - UINT32 CpuToNbFreeBufCnt:2; ///< Cpu to Nb free buffer count - UINT32 :14; ///< Reserved -} L3_BUFFER_COUNT_REGISTER; - -/* L3 Control 1 */ -#define L3_CONTROL_1_REG 0x1B8 - -/// L3 Control 1 Register -typedef struct { - UINT32 :27; ///< Reserved - UINT32 L3ATMModeEn:1; ///< Enable Accelerated Transition to Modified protocol in L3 - UINT32 :4; ///< Reserved -} L3_CONTROL_1_REGISTER; - -/* L3 Cache Parameter Register F3x1C4 */ -#define L3_CACHE_PARAM_REG 0x1C4 - -/// L3 Cache Parameter PCI Register -typedef struct { - UINT32 L3SubcacheSize0:4; ///< L3 subcache size 0 - UINT32 L3SubcacheSize1:4; ///< L3 subcache size 1 - UINT32 L3SubcacheSize2:4; ///< L3 subcache size 2 - UINT32 L3SubcacheSize3:4; ///< L3 subcache size 3 - UINT32 :15; ///< Reserved - UINT32 L3TagInit:1; ///< L3 tag initialization -} L3_CACHE_PARAM_REGISTER; - - -/* Probe Filter Control Register F3x1D4 */ -#define PROBE_FILTER_CTRL_REG 0x1D4 - -/// Probe Filter Control PCI Register -typedef struct { - UINT32 PFMode:2; ///< Probe Filter Mode - UINT32 PFWayNum:2; ///< Probe Filter way number - UINT32 PFSubCacheSize0:2; ///< Probe filter subcache 0 size - UINT32 PFSubCacheSize1:2; ///< Probe filter subcache 1 size - UINT32 PFSubCacheSize2:2; ///< Probe filter subcache 2 size - UINT32 PFSubCacheSize3:2; ///< Probe filter subcache 3 size - UINT32 PFSubCacheEn:4; ///< Probe filter subcache enable - UINT32 DisDirectedPrb:1; ///< Disable directed probes - UINT32 PFWayHashEn:1; ///< Probe filter cache way hash enable - UINT32 :1; ///< Reserved - UINT32 PFInitDone:1; ///< Probe filter initialization done - UINT32 PFPreferredSORepl:2; ///< PF preferredSO replacement mode - UINT32 PFErrInt:2; ///< Probe filter error interrupt type - UINT32 LvtOffset:4; ///< Probe filter error interrupt LVT offset - UINT32 PFEccError:1; ///< Probe filter ECC error - UINT32 PFLoIndexHashEn:1; ///< Probe filter low index hash enable - UINT32 DisPrbFilterInit:1; ///< Disable probe filter initialization - UINT32 SmallPFDirEn:1; ///< Small probe filter directory enable -} PROBE_FILTER_CTRL_REGISTER; - - -/* Product Info Register F3x1FC */ -#define PRCT_INFO_REG 0x1FC - -/// Product Information PCI Register -typedef struct { - UINT32 DiDtMode:1; ///< DiDtMode - UINT32 DiDtCfg0:5; ///< DiDtCfg0 - UINT32 DiDtCfg1:8; ///< DiDtCfg1 - UINT32 AlwaysOnThrottle:2; ///< AlwaysOnThrottle - UINT32 Pipe3ThrottleDis:1; ///< Pipe3ThrottleDis - UINT32 :15; ///< Reserved -} PRODUCT_INFO_REGISTER; - - -/* C-state Control 1 Register D18F4x118 */ -#define CSTATE_CTRL1_REG 0x118 -#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) - -/// C-state Control 1 Register -typedef struct { - UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable - UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select - UINT32 :1; ///< Reserved - UINT32 ClkDivisorCstAct0:3; ///< Clock divisor - UINT32 PwrGateEnCstAct0:1; ///< Power gate enable - UINT32 :1; ///< Reserved - UINT32 :6; ///< Reserved - UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable - UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select - UINT32 :1; ///< Reserved - UINT32 ClkDivisorCstAct1:3; ///< Clock divisor - UINT32 PwrGateEnCstAct1:1; ///< Power gate enable - UINT32 :1; ///< Reserved - UINT32 :6; ///< Reserved -} CSTATE_CTRL1_REGISTER; - - -/* C-state Control 2 Register D18F4x11C */ -#define CSTATE_CTRL2_REG 0x11C -#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) - -/// C-state Control 2 Register -typedef struct { - UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable - UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable - UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select - UINT32 AltvidEnCstAct2:1; ///< Core altvid enable - UINT32 ClkDivisorCstAct2:3; ///< Clock divisor - UINT32 PwrGateEnCstAct2:1; ///< Power gate enable - UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3 - UINT32 :22; ///< Reserved -} CSTATE_CTRL2_REGISTER; - - -/* Cstate Policy Control 1 Register D18F4x128 */ -#define CSTATE_POLICY_CTRL1_REG 0x128 -#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG)) - -/// Cstate Policy Control 1 Register -typedef struct { - UINT32 CoreCStateMode:1; ///< Specifies C-State actions - UINT32 CoreCstatePolicy:1; ///< Specified processor arbitration of voltage and frequency - UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction - UINT32 CacheFlushTmr:7; ///< Cache flush timer - UINT32 CoreStateSaveDestnode:6; ///< Core state save destination node - UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold - UINT32 :10; ///< Reserved - UINT32 CstateMsgDis:1; ///< C-state messaging disable -} CSTATE_POLICY_CTRL1_REGISTER; - - -/* Core Performance Boost Control Register D18F4x15C */ - -/// Core Performance Boost Control Register -typedef struct { - UINT32 BoostSrc:2; ///< Boost source - UINT32 NumBoostStates:3; ///< Number of boosted states - UINT32 :2; ///< Reserved - UINT32 ApmMasterEn:1; ///< APM master enable - UINT32 :20; ///< Reserved - UINT32 TdpLimitPstate:3; ///< Highest performance pstate - UINT32 BoostLock:1; ///< -} CPB_CTRL_REGISTER; - - -/* Northbridge P-state [3:0] F5x1[6C:60] */ - -/// Northbridge P-state Register -typedef struct { - UINT32 NbPstateEn:1; ///< NB P-state enable - UINT32 NbFid:5; ///< NB frequency ID - UINT32 :1; ///< Reserved - UINT32 NbDid:1; ///< NB divisor ID - UINT32 :2; ///< Reserved - UINT32 NbVid:7; ///< NB VID - UINT32 :15; ///< Reserved -} NB_PSTATE_REGISTER; - - -/* Northbridge P-state Status */ -#define NB_PSTATE_CTRL 0x170 -#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL)) - -/// Northbridge P-state Control Register -typedef struct { - UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value - UINT32 :1; ///< Reserved - UINT32 NbPstateLo:2; ///< NB P-state low - UINT32 :1; ///< Reserved - UINT32 NbPstateHi:2; ///< NB P-state high - UINT32 :1; ///< Reserved - UINT32 NbPstateThreshold:3; ///< NB P-state threshold - UINT32 :1; ///< Reserved - UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 - UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable - UINT32 :17; ///< Reserved -} NB_PSTATE_CTRL_REGISTER; - - -/* Northbridge P-state Status */ -#define NB_PSTATE_STATUS 0x174 -#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS)) - -/// Northbridge P-state Status Register -typedef struct { - UINT32 NbPstateDis:1; ///< Nb pstate disable - UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number - UINT32 CurNbFid:5; ///< Current NB FID - UINT32 :1; ///< Reserved - UINT32 CurNbDid:1; ///< Current NB DID - UINT32 :2; ///< Reserved - UINT32 CurNbVid:7; ///< Current NB VID - UINT32 CurNbPstate:2; ///< Current NB Pstate - UINT32 :11; ///< Reserved -} NB_PSTATE_STS_REGISTER; - -#endif /* _CPU_F15_OR_POWERMGMT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c deleted file mode 100644 index 4a2251a4e4..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c +++ /dev/null @@ -1,920 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi Pstate feature support functions. - * - * Provides the functions necessary to initialize the Pstate feature. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "GeneralServices.h" -#include "cpuPstateTables.h" -#include "cpuRegisters.h" -#include "Table.h" -#include "cpuFamilyTranslation.h" -#include "cpuFamRegisters.h" -#include "cpuF15Utilities.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionMultiSocket.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -VOID -STATIC -F15OrGetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ); - -VOID -STATIC -F15OrGetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ); - -AGESA_STATUS -STATIC -F15OrGetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrPstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -F15OrGetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ); - - - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if PSD need to be generated. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD need to be generated - * @retval FALSE PSD does NOT need to be generated - * - */ -BOOLEAN -STATIC -F15OrIsPstatePsdNeeded ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - PLATFORM_FEATS Features; - - // Initialize the union - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, PlatformConfig, StdHeader); - - // - // For Single link processor, PSD needs to be generated - // For other processor, if D18F5x80[DualCore][0]=0, the _PSD object does not need to be generated. - // - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = COMPUTE_UNIT_STATUS; - PciAddress.Address.Function = FUNC_5; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if ((!Features.PlatformFeatures.PlatformSingleLink) && ((LocalPciRegister & 0x10000) == 0)) { - return FALSE; - } - return TRUE; -} - - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to check if Pstate PSD is dependent. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. - * @param[in] StdHeader Config Handle for library, services. - * - * @retval TRUE PSD is dependent. - * @retval FALSE PSD is independent. - * - */ -BOOLEAN -STATIC -F15OrIsPstatePsdDependent ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN OUT PLATFORM_CONFIGURATION *PlatformConfig, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PLATFORM_FEATS Features; - - // Initialize the union - Features.PlatformValue = 0; - GetPlatformFeatures (&Features, PlatformConfig, StdHeader); - - // - // For Single link has PSD option, default is dependent. - // If multi-link, always return independent. - // - if (Features.PlatformFeatures.PlatformSingleLink) { - if (PlatformConfig->ForcePstateIndependent) { - return FALSE; - } - return TRUE; - } - return FALSE; -} - -/** - * Family specific call to set core TscFreqSel. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StdHeader Config Handle for library, services. - * - */ -VOID -STATIC -F15OrSetTscFreqSel ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - //TscFreqSel: TSC frequency select. Read-only. Reset: 1. 1=The TSC increments at the P0 frequency. - //This field uses software P-state numbering. - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get Pstate Transition Latency. - * - * Calculate TransitionLatency by power step value and pll value. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer - * @param[in] PciAddress Pci address - * @param[out] TransitionLatency The transition latency. - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateTransLatency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, - IN PCI_ADDR *PciAddress, - OUT UINT32 *TransitionLatency, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempVar_b; - UINT32 TempVar_c; - UINT32 TempVar_d; - UINT32 TempVar8_a; - UINT32 TempVar8_b; - UINT32 Ignored; - UINT32 k; - UINT32 CpuFidSameFlag; - UINT8 PStateMaxValueOnCurrentCore; - UINT32 TransAndBusMastLatency; - - CpuFidSameFlag = 1; - - F15OrGetFrequencyXlatRegInfo ( - PstateCpuServices, - 0, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - - TempVar_d = TempVar_b; - PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue; - - // - //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states where - //MSRC001_00[6B:64][PstateEn]=1 - // - for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) { - if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { - F15OrGetFrequencyXlatRegInfo ( - PstateCpuServices, - (UINT8) k, - PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq, - &TempVar_b, - &TempVar_c, - &Ignored, - StdHeader - ); - } - - if (TempVar_d != TempVar_b) { - CpuFidSameFlag = 0; - break; - } - } - - PciAddress->Address.Register = 0xD4; - PciAddress->Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - // PowerStepDown - Bits 20:23 - TempVar8_a = (TempVar_d & 0x00F00000) >> 20; - - // PowerStepUp - Bits 24:27 - TempVar8_b = (TempVar_d & 0x0F000000) >> 24; - - // Convert the raw numbers in TempVar8_a and TempVar8_b into time - F15OrGetPowerStepValueInTime (&TempVar8_a); - F15OrGetPowerStepValueInTime (&TempVar8_b); - - // - //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us - // - TransAndBusMastLatency = - (12 * (TempVar8_a + TempVar8_b) + 999) / 1000; - - if (CpuFidSameFlag == 0) { - // - //+ F3xA0[PllLockTime] - // - PciAddress->Address.Register = 0xA0; - LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); - - TempVar8_a = (0x00003800 & TempVar_d) >> 11; - F15OrGetPllValueInTime (&TempVar8_a); - TransAndBusMastLatency += TempVar8_a; - } - - *TransitionLatency = TransAndBusMastLatency; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the frequency in megahertz of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber The hardware P-State to analyze. - * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always Succeeds. - */ -AGESA_STATUS -F15OrGetPstateFrequency ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *FrequencyInMHz, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 TempValue; - UINT32 CpuDid; - UINT32 CpuFid; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); - - switch (CpuDid) { - case 0: - TempValue = 1; - break; - case 1: - TempValue = 2; - break; - case 2: - TempValue = 4; - break; - case 3: - TempValue = 8; - break; - case 4: - TempValue = 16; - break; - default: - // CpuDid is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - TempValue = 1; - break; - } - *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue); - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] CpuAmdPState Gathered P-state data structure for whole system. - * @param[in] StdHeader Config for library and services. - * - * @retval AGESA_STATUS AGESA_SUCCESS Always succeeds. - * - */ -AGESA_STATUS -F15OrPstateLevelingCoreMsrModify ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN S_CPU_AMD_PSTATE *CpuAmdPState, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 Ignored; - UINT32 k; - UINT32 TempVar_d; - UINT32 TempVar_e; - UINT32 TempVar_f; - UINT32 LogicalSocketCount; - UINT32 LocalPciRegister; - UINT32 Socket; - UINT32 Module; - UINT32 Core; - UINT8 SwP0; - UINT64 MsrValue; - AGESA_STATUS Status; - PSTATE_LEVELING *PStateBufferPtr; - PSTATE_LEVELING *PStateBufferPtrTmp; - S_CPU_AMD_PSTATE *CpuAmdPstatePtr; - PCI_ADDR PciAddress; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); - ASSERT (FamilySpecificServices != NULL); - - Ignored = 0; - CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState; - PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc; - PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc; - LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem; - PciAddress.AddressValue = 0; - SwP0 = PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates; - - // - //Try to find the Pstate buffer specific to this core(socket). - // - IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status); - GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status); - for (i = 0; i < LogicalSocketCount; i++) { - CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader); - if (PStateBufferPtrTmp->SocketNumber == Socket) { - break; - } - } - - if (PStateBufferPtr[0].OnlyOneEnabledPState) { - // - //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores: - // - - //1. Write the appropriate CpuFid value resulting from the matched CPU COF to 'software P0'. - LibAmdMsrRead (MSR_PSTATE_0 + (UINT32) SwP0, &MsrValue, StdHeader); - Status = F15OrGetFrequencyXlatRegInfo (PstateCpuServices, SwP0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (MSR_PSTATE_0 + (UINT32) SwP0, &MsrValue, StdHeader); - - //2. Copy P0 to P1 - LibAmdMsrWrite (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - - //3. Increment F3xDC[PstatemaxVal] by 1. - PciAddress.Address.Register = CPTC2_REG; - PciAddress.Address.Function = FUNC_3; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal++; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - //4. Write 001b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); - - //5. Wait for MSRC001_0071[CurCpuFid] = P1[CpuFid]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d); - - //6. Write 000b to MSRC001_0062[PstateCmd]. - FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); - - //7. Wait for MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader); - } while (((COFVID_STS_MSR *) &MsrValue)->CurPstate != ((COFVID_STS_MSR *) &MsrValue)->CurPstateLimit); - - //8. Write 0b to P1[PstateEn]. - LibAmdMsrRead (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (MSR_PSTATE_1 + (UINT32) SwP0, &MsrValue, StdHeader); - - //9. Decrement F3xDC[PstateMaxVal] by 1 and exit the sequence (no further steps are required). - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal--; - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - - } else { - - TempVar_f = MSR_PSTATE_0 + (UINT32) SwP0; - - for (k = SwP0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) { - // If pState is not disabled then do update - LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader); - - if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) { - Status = F15OrGetFrequencyXlatRegInfo (PstateCpuServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader); - if (Status != AGESA_ERROR) { - // Bits 5:0 - ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d; - // Bits 8:6 - ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e; - } - - // Bits 39:32 - ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue; - // Bits 41:40 - ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv; - // Enable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 1; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } else { - // Disable the P-State - ((PSTATE_MSR *) &MsrValue)->PsEnable = 0; - LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader); - } - } - } - return AGESA_SUCCESS; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to calculates the power in milliWatts of the desired P-state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] StateNumber Which P-state to analyze - * @param[out] PowerInMw The Power in milliWatts of that P-State - * @param[in] StdHeader Header for library and services - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstatePower ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 StateNumber, - OUT UINT32 *PowerInMw, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 CpuVid; - UINT32 IddValue; - UINT32 IddDiv; - UINT32 V_x10000; - UINT32 Power; - UINT64 LocalMsrRegister; - - ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); - - if (CpuVid >= 0x7C) { - V_x10000 = 0; - } else { - V_x10000 = 15500L - (125L * CpuVid); - } - - Power = V_x10000 * IddValue; - - switch (IddDiv) { - case 0: - *PowerInMw = Power / 10L; - break; - case 1: - *PowerInMw = Power / 100L; - break; - case 2: - *PowerInMw = Power / 1000L; - break; - default: - // IddDiv is set to an undefined value. This is due to either a misfused CPU, or - // an invalid P-state MSR write. - ASSERT (FALSE); - *PowerInMw = 0; - break; - } - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate max state. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[out] MaxPStateNumber The max hw pstate value on the current socket. - * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateMaxState ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - OUT UINT32 *MaxPStateNumber, - OUT UINT8 *NumberOfBoostStates, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 NumBoostStates; - UINT64 MsrValue; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - LocalPciRegister = 0; - - // For F15 Orochi CPU, skip boosted p-state. The boosted p-state number = D[1F:18]F4x15C[NumBoostStates]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = CPB_CTRL_REG; - PciAddress.Address.Function = FUNC_4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C - - NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - *NumberOfBoostStates = (UINT8) NumBoostStates; - - // - // Read PstateMaxVal [6:4] from MSR C001_0061 - // So, we will know the max pstate state in this socket. - // - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; - - return (AGESA_SUCCESS); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Family specific call to get CPU pstate register information. - * - * @param[in] PstateCpuServices Pstate CPU services. - * @param[in] PState Input Pstate number for query. - * @param[out] PStateEnabled Boolean flag return pstate enable. - * @param[in,out] IddVal Pstate current value. - * @param[in,out] IddDiv Pstate current divisor. - * @param[out] SwPstateNumber Software P-state number. - * @param[in] StdHeader Handle of Header for calling lib functions and services. - * - * @retval AGESA_SUCCESS Always succeeds. - */ -AGESA_STATUS -F15OrGetPstateRegisterInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT32 PState, - OUT BOOLEAN *PStateEnabled, - IN OUT UINT32 *IddVal, - IN OUT UINT32 *IddDiv, - OUT UINT32 *SwPstateNumber, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 LocalPciRegister; - UINT64 LocalMsrRegister; - PCI_ADDR PciAddress; - - ASSERT (PState < NM_PS_REG); - - // For F15 Orochi CPU, skip boosted p-state. The boosted p-state number = D[1F:18]F4x15C[NumBoostStates]. - OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); - PciAddress.Address.Register = CPB_CTRL_REG; - PciAddress.Address.Function = FUNC_4; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C - - // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); - - *SwPstateNumber = PState; - - if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { - // PState enable = bit 63 - *PStateEnabled = TRUE; - // - // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. - // - if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { - *PStateEnabled = FALSE; - } else { - *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; - } - } else { - *PStateEnabled = FALSE; - } - - // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; - // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; - - return (AGESA_SUCCESS); -} - - -CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices = -{ - 0, - F15OrIsPstatePsdNeeded, - F15OrIsPstatePsdDependent, - F15OrSetTscFreqSel, - F15OrGetPstateTransLatency, - F15OrGetPstateFrequency, - F15OrPstateLevelingCoreMsrModify, - F15OrGetPstatePower, - F15OrGetPstateMaxState, - F15OrGetPstateRegisterInfo -}; - - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - - -/** - *--------------------------------------------------------------------------------------- - * - * F15OrGetPowerStepValueInTime - * - * Description: - * Convert power step value in time - * - * Parameters: - * @param[out] *PowerStepPtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F15OrGetPowerStepValueInTime ( - IN OUT UINT32 *PowerStepPtr - ) -{ - UINT32 TempVar_a; - - TempVar_a = *PowerStepPtr; - - if (TempVar_a < 0x4) { - *PowerStepPtr = 400 - (TempVar_a * 100); - } else if (TempVar_a < 0x9) { - *PowerStepPtr = 130 - (TempVar_a * 10); - } else { - *PowerStepPtr = 90 - (TempVar_a * 5); - } -} - -/** - *--------------------------------------------------------------------------------------- - * - * F15OrGetPllValueInTime - * - * Description: - * Convert PLL Value in time - * - * Parameters: - * @param[out] *PllLockTimePtr - * - * @retval VOID - * - *--------------------------------------------------------------------------------------- - **/ -VOID -STATIC -F15OrGetPllValueInTime ( - IN OUT UINT32 *PllLockTimePtr - ) -{ - if (*PllLockTimePtr < 4) { - *PllLockTimePtr = *PllLockTimePtr + 1; - } else if (*PllLockTimePtr == 4) { - *PllLockTimePtr = 8; - } else if (*PllLockTimePtr == 5) { - *PllLockTimePtr = 16; - } else - *PllLockTimePtr = 0; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * This function will return the CpuFid and CpuDid in MHz, using the formula - * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0 - * - * @param[in] PstateCpuServices The current Family Specific Services. - * @param[in] PStateNumber P-state number to check. - * @param[in] Frequency Leveled target frequency for PStateNumber. - * @param[out] *CpuFidPtr New leveled FID. - * @param[out] *CpuDidPtr1 New leveled DID info 1. - * @param[out] *CpuDidPtr2 New leveled DID info 2. - * @param[in] *StdHeader Header for library and services. - * - * @retval AGESA_WARNING This P-State does not need to be modified. - * @retval AGESA_SUCCESS This P-State must be modified to be level. - */ -AGESA_STATUS -STATIC -F15OrGetFrequencyXlatRegInfo ( - IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, - IN UINT8 PStateNumber, - IN UINT32 Frequency, - OUT UINT32 *CpuFidPtr, - OUT UINT32 *CpuDidPtr1, - OUT UINT32 *CpuDidPtr2, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 i; - UINT32 j; - AGESA_STATUS Status; - UINT32 FrequencyInMHz; - - FrequencyInMHz = 0; - *CpuDidPtr2 = 0xFFFF; - - Status = AGESA_SUCCESS; - - PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader); - if (FrequencyInMHz == Frequency) { - Status |= AGESA_WARNING; - } - - // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid) - // In this for loop i = 2^CpuDid - - - for (i = 1; i < 17; (i += i)) { - for (j = 0; j < 64; j++) { - if (Frequency == ((100 * (j + 0x10)) / i )) { - *CpuFidPtr = j; - if (i == 1) { - *CpuDidPtr1 = 0; - } else if (i == 2) { - *CpuDidPtr1 = 1; - } else if (i == 4) { - *CpuDidPtr1 = 2; - } else if (i == 8) { - *CpuDidPtr1 = 3; - } else if (i == 16) { - *CpuDidPtr1 = 4; - } else { - *CpuFidPtr = 0xFFFF; - *CpuDidPtr1 = 0xFFFF; - } - // Success - return Status; - } - } - } - - // Error Condition - *CpuFidPtr = 0x00FF; - *CpuDidPtr1 = 0x00FF; - *CpuDidPtr2 = 0x00FF; - - return AGESA_ERROR; -} - diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c deleted file mode 100644 index cd0dc48249..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c +++ /dev/null @@ -1,128 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi thermal initialization - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 55600 $ @e \$Date: 2011-06-23 12:39:18 -0600 (Thu, 23 Jun 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "amdlib.h" -#include "cpuRegisters.h" -#include "GeneralServices.h" -#include "cpuFamilyTranslation.h" -#include "cpuF15PowerMgmt.h" -#include "cpuF15OrPowerMgmt.h" -#include "OptionFamily15hEarlySample.h" -#include "OptionMultiSocket.h" -#include "cpuF15OrSoftwareThermal.h" -#include "Filecode.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -#define FILECODE PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -extern F15_OR_ES_CORE_SUPPORT F15OrEarlySampleCoreSupport; -extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------------------*/ -/** - * Main entry point for initializing the Thermal Control - * safety net feature. - * - * This must be run by all Family 15h Orochi core 0s in the system. - * - * @param[in] FamilySpecificServices The current Family Specific Services. - * @param[in] CpuEarlyParamsPtr Service parameters. - * @param[in] StdHeader Config handle for library and services. - */ -VOID -F15OrPmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Core; - UINT32 LocalPciRegister; - PCI_ADDR PciAddress; - - if (OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader)) { - GetCurrentCore (&Core, StdHeader); - ASSERT (Core == 0); - PciAddress.Address.Function = FUNC_3; - PciAddress.Address.Register = NB_CAPS_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) { - // Enable HTC - PciAddress.Address.Register = HTC_REG; - LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - ((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0; - ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; - F15OrEarlySampleCoreSupport.F15OrHtcInitHook (&LocalPciRegister, StdHeader); - IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader); - LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); - } - } -} diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h deleted file mode 100644 index 130c73df1d..0000000000 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Family_15 Orochi thermal initialization related functions and structures - * - * Performs processor thermal initialization. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/OR - * @e \$Revision: 45341 $ @e \$Date: 2011-01-14 15:49:18 -0700 (Fri, 14 Jan 2011) $ - * - */ -/* - ****************************************************************************** - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef _CPU_F15_OR_SOFTWARE_THERMAL_H_ -#define _CPU_F15_OR_SOFTWARE_THERMAL_H_ - - -/*--------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *--------------------------------------------------------------------------------------- - */ - - -/*--------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *--------------------------------------------------------------------------------------- - */ -VOID -F15OrPmThermalInit ( - IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, - IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _CPU_F15_OR_SOFTWARE_THERMAL_H_ |